1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Hexagon implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "HexagonInstrInfo.h" 15#include "Hexagon.h" 16#include "HexagonRegisterInfo.h" 17#include "HexagonSubtarget.h" 18#include "llvm/ADT/STLExtras.h" 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/CodeGen/DFAPacketizer.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/MachineMemOperand.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Support/MathExtras.h" 27#define GET_INSTRINFO_CTOR 28#define GET_INSTRMAP_INFO 29#include "HexagonGenInstrInfo.inc" 30#include "HexagonGenDFAPacketizer.inc" 31 32using namespace llvm; 33 34/// 35/// Constants for Hexagon instructions. 36/// 37const int Hexagon_MEMW_OFFSET_MAX = 4095; 38const int Hexagon_MEMW_OFFSET_MIN = -4096; 39const int Hexagon_MEMD_OFFSET_MAX = 8191; 40const int Hexagon_MEMD_OFFSET_MIN = -8192; 41const int Hexagon_MEMH_OFFSET_MAX = 2047; 42const int Hexagon_MEMH_OFFSET_MIN = -2048; 43const int Hexagon_MEMB_OFFSET_MAX = 1023; 44const int Hexagon_MEMB_OFFSET_MIN = -1024; 45const int Hexagon_ADDI_OFFSET_MAX = 32767; 46const int Hexagon_ADDI_OFFSET_MIN = -32768; 47const int Hexagon_MEMD_AUTOINC_MAX = 56; 48const int Hexagon_MEMD_AUTOINC_MIN = -64; 49const int Hexagon_MEMW_AUTOINC_MAX = 28; 50const int Hexagon_MEMW_AUTOINC_MIN = -32; 51const int Hexagon_MEMH_AUTOINC_MAX = 14; 52const int Hexagon_MEMH_AUTOINC_MIN = -16; 53const int Hexagon_MEMB_AUTOINC_MAX = 7; 54const int Hexagon_MEMB_AUTOINC_MIN = -8; 55 56 57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) 58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), 59 RI(ST, *this), Subtarget(ST) { 60} 61 62 63/// isLoadFromStackSlot - If the specified machine instruction is a direct 64/// load from a stack slot, return the virtual or physical register number of 65/// the destination along with the FrameIndex of the loaded stack slot. If 66/// not, return 0. This predicate must return 0 if the instruction has 67/// any side effects other than loading from the stack slot. 68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 69 int &FrameIndex) const { 70 71 72 switch (MI->getOpcode()) { 73 default: break; 74 case Hexagon::LDriw: 75 case Hexagon::LDrid: 76 case Hexagon::LDrih: 77 case Hexagon::LDrib: 78 case Hexagon::LDriub: 79 if (MI->getOperand(2).isFI() && 80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 81 FrameIndex = MI->getOperand(2).getIndex(); 82 return MI->getOperand(0).getReg(); 83 } 84 break; 85 } 86 return 0; 87} 88 89 90/// isStoreToStackSlot - If the specified machine instruction is a direct 91/// store to a stack slot, return the virtual or physical register number of 92/// the source reg along with the FrameIndex of the loaded stack slot. If 93/// not, return 0. This predicate must return 0 if the instruction has 94/// any side effects other than storing to the stack slot. 95unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 96 int &FrameIndex) const { 97 switch (MI->getOpcode()) { 98 default: break; 99 case Hexagon::STriw: 100 case Hexagon::STrid: 101 case Hexagon::STrih: 102 case Hexagon::STrib: 103 if (MI->getOperand(2).isFI() && 104 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 105 FrameIndex = MI->getOperand(0).getIndex(); 106 return MI->getOperand(2).getReg(); 107 } 108 break; 109 } 110 return 0; 111} 112 113 114unsigned 115HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 116 MachineBasicBlock *FBB, 117 const SmallVectorImpl<MachineOperand> &Cond, 118 DebugLoc DL) const{ 119 120 int BOpc = Hexagon::JMP; 121 int BccOpc = Hexagon::JMP_c; 122 123 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 124 125 int regPos = 0; 126 // Check if ReverseBranchCondition has asked to reverse this branch 127 // If we want to reverse the branch an odd number of times, we want 128 // JMP_cNot. 129 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 130 BccOpc = Hexagon::JMP_cNot; 131 regPos = 1; 132 } 133 134 if (FBB == 0) { 135 if (Cond.empty()) { 136 // Due to a bug in TailMerging/CFG Optimization, we need to add a 137 // special case handling of a predicated jump followed by an 138 // unconditional jump. If not, Tail Merging and CFG Optimization go 139 // into an infinite loop. 140 MachineBasicBlock *NewTBB, *NewFBB; 141 SmallVector<MachineOperand, 4> Cond; 142 MachineInstr *Term = MBB.getFirstTerminator(); 143 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, 144 false)) { 145 MachineBasicBlock *NextBB = 146 llvm::next(MachineFunction::iterator(&MBB)); 147 if (NewTBB == NextBB) { 148 ReverseBranchCondition(Cond); 149 RemoveBranch(MBB); 150 return InsertBranch(MBB, TBB, 0, Cond, DL); 151 } 152 } 153 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 154 } else { 155 BuildMI(&MBB, DL, 156 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 157 } 158 return 1; 159 } 160 161 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 162 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 163 164 return 2; 165} 166 167 168bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 169 MachineBasicBlock *&TBB, 170 MachineBasicBlock *&FBB, 171 SmallVectorImpl<MachineOperand> &Cond, 172 bool AllowModify) const { 173 TBB = NULL; 174 FBB = NULL; 175 176 // If the block has no terminators, it just falls into the block after it. 177 MachineBasicBlock::iterator I = MBB.end(); 178 if (I == MBB.begin()) 179 return false; 180 181 // A basic block may looks like this: 182 // 183 // [ insn 184 // EH_LABEL 185 // insn 186 // insn 187 // insn 188 // EH_LABEL 189 // insn ] 190 // 191 // It has two succs but does not have a terminator 192 // Don't know how to handle it. 193 do { 194 --I; 195 if (I->isEHLabel()) 196 return true; 197 } while (I != MBB.begin()); 198 199 I = MBB.end(); 200 --I; 201 202 while (I->isDebugValue()) { 203 if (I == MBB.begin()) 204 return false; 205 --I; 206 } 207 if (!isUnpredicatedTerminator(I)) 208 return false; 209 210 // Get the last instruction in the block. 211 MachineInstr *LastInst = I; 212 213 // If there is only one terminator instruction, process it. 214 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 215 if (LastInst->getOpcode() == Hexagon::JMP) { 216 TBB = LastInst->getOperand(0).getMBB(); 217 return false; 218 } 219 if (LastInst->getOpcode() == Hexagon::JMP_c) { 220 // Block ends with fall-through true condbranch. 221 TBB = LastInst->getOperand(1).getMBB(); 222 Cond.push_back(LastInst->getOperand(0)); 223 return false; 224 } 225 if (LastInst->getOpcode() == Hexagon::JMP_cNot) { 226 // Block ends with fall-through false condbranch. 227 TBB = LastInst->getOperand(1).getMBB(); 228 Cond.push_back(MachineOperand::CreateImm(0)); 229 Cond.push_back(LastInst->getOperand(0)); 230 return false; 231 } 232 // Otherwise, don't know what this is. 233 return true; 234 } 235 236 // Get the instruction before it if it's a terminator. 237 MachineInstr *SecondLastInst = I; 238 239 // If there are three terminators, we don't know what sort of block this is. 240 if (SecondLastInst && I != MBB.begin() && 241 isUnpredicatedTerminator(--I)) 242 return true; 243 244 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it. 245 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) || 246 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) && 247 LastInst->getOpcode() == Hexagon::JMP) { 248 TBB = SecondLastInst->getOperand(1).getMBB(); 249 Cond.push_back(SecondLastInst->getOperand(0)); 250 FBB = LastInst->getOperand(0).getMBB(); 251 return false; 252 } 253 254 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it. 255 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) && 256 LastInst->getOpcode() == Hexagon::JMP) { 257 TBB = SecondLastInst->getOperand(1).getMBB(); 258 Cond.push_back(MachineOperand::CreateImm(0)); 259 Cond.push_back(SecondLastInst->getOperand(0)); 260 FBB = LastInst->getOperand(0).getMBB(); 261 return false; 262 } 263 264 // If the block ends with two Hexagon:JMPs, handle it. The second one is not 265 // executed, so remove it. 266 if (SecondLastInst->getOpcode() == Hexagon::JMP && 267 LastInst->getOpcode() == Hexagon::JMP) { 268 TBB = SecondLastInst->getOperand(0).getMBB(); 269 I = LastInst; 270 if (AllowModify) 271 I->eraseFromParent(); 272 return false; 273 } 274 275 // Otherwise, can't handle this. 276 return true; 277} 278 279 280unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 281 int BOpc = Hexagon::JMP; 282 int BccOpc = Hexagon::JMP_c; 283 int BccOpcNot = Hexagon::JMP_cNot; 284 285 MachineBasicBlock::iterator I = MBB.end(); 286 if (I == MBB.begin()) return 0; 287 --I; 288 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc && 289 I->getOpcode() != BccOpcNot) 290 return 0; 291 292 // Remove the branch. 293 I->eraseFromParent(); 294 295 I = MBB.end(); 296 297 if (I == MBB.begin()) return 1; 298 --I; 299 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot) 300 return 1; 301 302 // Remove the branch. 303 I->eraseFromParent(); 304 return 2; 305} 306 307 308/// \brief For a comparison instruction, return the source registers in 309/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it 310/// compares against in CmpValue. Return true if the comparison instruction 311/// can be analyzed. 312bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI, 313 unsigned &SrcReg, unsigned &SrcReg2, 314 int &Mask, int &Value) const { 315 unsigned Opc = MI->getOpcode(); 316 317 // Set mask and the first source register. 318 switch (Opc) { 319 case Hexagon::CMPEHexagon4rr: 320 case Hexagon::CMPEQri: 321 case Hexagon::CMPEQrr: 322 case Hexagon::CMPGT64rr: 323 case Hexagon::CMPGTU64rr: 324 case Hexagon::CMPGTUri: 325 case Hexagon::CMPGTUrr: 326 case Hexagon::CMPGTri: 327 case Hexagon::CMPGTrr: 328 case Hexagon::CMPLTUrr: 329 case Hexagon::CMPLTrr: 330 SrcReg = MI->getOperand(1).getReg(); 331 Mask = ~0; 332 break; 333 case Hexagon::CMPbEQri_V4: 334 case Hexagon::CMPbEQrr_sbsb_V4: 335 case Hexagon::CMPbEQrr_ubub_V4: 336 case Hexagon::CMPbGTUri_V4: 337 case Hexagon::CMPbGTUrr_V4: 338 case Hexagon::CMPbGTrr_V4: 339 SrcReg = MI->getOperand(1).getReg(); 340 Mask = 0xFF; 341 break; 342 case Hexagon::CMPhEQri_V4: 343 case Hexagon::CMPhEQrr_shl_V4: 344 case Hexagon::CMPhEQrr_xor_V4: 345 case Hexagon::CMPhGTUri_V4: 346 case Hexagon::CMPhGTUrr_V4: 347 case Hexagon::CMPhGTrr_shl_V4: 348 SrcReg = MI->getOperand(1).getReg(); 349 Mask = 0xFFFF; 350 break; 351 } 352 353 // Set the value/second source register. 354 switch (Opc) { 355 case Hexagon::CMPEHexagon4rr: 356 case Hexagon::CMPEQrr: 357 case Hexagon::CMPGT64rr: 358 case Hexagon::CMPGTU64rr: 359 case Hexagon::CMPGTUrr: 360 case Hexagon::CMPGTrr: 361 case Hexagon::CMPbEQrr_sbsb_V4: 362 case Hexagon::CMPbEQrr_ubub_V4: 363 case Hexagon::CMPbGTUrr_V4: 364 case Hexagon::CMPbGTrr_V4: 365 case Hexagon::CMPhEQrr_shl_V4: 366 case Hexagon::CMPhEQrr_xor_V4: 367 case Hexagon::CMPhGTUrr_V4: 368 case Hexagon::CMPhGTrr_shl_V4: 369 case Hexagon::CMPLTUrr: 370 case Hexagon::CMPLTrr: 371 SrcReg2 = MI->getOperand(2).getReg(); 372 return true; 373 374 case Hexagon::CMPEQri: 375 case Hexagon::CMPGTUri: 376 case Hexagon::CMPGTri: 377 case Hexagon::CMPbEQri_V4: 378 case Hexagon::CMPbGTUri_V4: 379 case Hexagon::CMPhEQri_V4: 380 case Hexagon::CMPhGTUri_V4: 381 SrcReg2 = 0; 382 Value = MI->getOperand(2).getImm(); 383 return true; 384 } 385 386 return false; 387} 388 389 390void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 391 MachineBasicBlock::iterator I, DebugLoc DL, 392 unsigned DestReg, unsigned SrcReg, 393 bool KillSrc) const { 394 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { 395 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg); 396 return; 397 } 398 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { 399 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg); 400 return; 401 } 402 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { 403 // Map Pd = Ps to Pd = or(Ps, Ps). 404 BuildMI(MBB, I, DL, get(Hexagon::OR_pp), 405 DestReg).addReg(SrcReg).addReg(SrcReg); 406 return; 407 } 408 if (Hexagon::DoubleRegsRegClass.contains(DestReg) && 409 Hexagon::IntRegsRegClass.contains(SrcReg)) { 410 // We can have an overlap between single and double reg: r1:0 = r0. 411 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { 412 // r1:0 = r0 413 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 414 Hexagon::subreg_hireg))).addImm(0); 415 } else { 416 // r1:0 = r1 or no overlap. 417 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg, 418 Hexagon::subreg_loreg))).addReg(SrcReg); 419 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 420 Hexagon::subreg_hireg))).addImm(0); 421 } 422 return; 423 } 424 if (Hexagon::CRRegsRegClass.contains(DestReg) && 425 Hexagon::IntRegsRegClass.contains(SrcReg)) { 426 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg); 427 return; 428 } 429 if (Hexagon::PredRegsRegClass.contains(SrcReg) && 430 Hexagon::IntRegsRegClass.contains(DestReg)) { 431 BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg). 432 addReg(SrcReg, getKillRegState(KillSrc)); 433 return; 434 } 435 if (Hexagon::IntRegsRegClass.contains(SrcReg) && 436 Hexagon::PredRegsRegClass.contains(DestReg)) { 437 BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg). 438 addReg(SrcReg, getKillRegState(KillSrc)); 439 return; 440 } 441 442 llvm_unreachable("Unimplemented"); 443} 444 445 446void HexagonInstrInfo:: 447storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 448 unsigned SrcReg, bool isKill, int FI, 449 const TargetRegisterClass *RC, 450 const TargetRegisterInfo *TRI) const { 451 452 DebugLoc DL = MBB.findDebugLoc(I); 453 MachineFunction &MF = *MBB.getParent(); 454 MachineFrameInfo &MFI = *MF.getFrameInfo(); 455 unsigned Align = MFI.getObjectAlignment(FI); 456 457 MachineMemOperand *MMO = 458 MF.getMachineMemOperand( 459 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 460 MachineMemOperand::MOStore, 461 MFI.getObjectSize(FI), 462 Align); 463 464 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { 465 BuildMI(MBB, I, DL, get(Hexagon::STriw)) 466 .addFrameIndex(FI).addImm(0) 467 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 468 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { 469 BuildMI(MBB, I, DL, get(Hexagon::STrid)) 470 .addFrameIndex(FI).addImm(0) 471 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 472 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { 473 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) 474 .addFrameIndex(FI).addImm(0) 475 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 476 } else { 477 llvm_unreachable("Unimplemented"); 478 } 479} 480 481 482void HexagonInstrInfo::storeRegToAddr( 483 MachineFunction &MF, unsigned SrcReg, 484 bool isKill, 485 SmallVectorImpl<MachineOperand> &Addr, 486 const TargetRegisterClass *RC, 487 SmallVectorImpl<MachineInstr*> &NewMIs) const 488{ 489 llvm_unreachable("Unimplemented"); 490} 491 492 493void HexagonInstrInfo:: 494loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 495 unsigned DestReg, int FI, 496 const TargetRegisterClass *RC, 497 const TargetRegisterInfo *TRI) const { 498 DebugLoc DL = MBB.findDebugLoc(I); 499 MachineFunction &MF = *MBB.getParent(); 500 MachineFrameInfo &MFI = *MF.getFrameInfo(); 501 unsigned Align = MFI.getObjectAlignment(FI); 502 503 MachineMemOperand *MMO = 504 MF.getMachineMemOperand( 505 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 506 MachineMemOperand::MOLoad, 507 MFI.getObjectSize(FI), 508 Align); 509 if (RC == &Hexagon::IntRegsRegClass) { 510 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg) 511 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 512 } else if (RC == &Hexagon::DoubleRegsRegClass) { 513 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg) 514 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 515 } else if (RC == &Hexagon::PredRegsRegClass) { 516 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) 517 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 518 } else { 519 llvm_unreachable("Can't store this register to stack slot"); 520 } 521} 522 523 524void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 525 SmallVectorImpl<MachineOperand> &Addr, 526 const TargetRegisterClass *RC, 527 SmallVectorImpl<MachineInstr*> &NewMIs) const { 528 llvm_unreachable("Unimplemented"); 529} 530 531 532MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 533 MachineInstr* MI, 534 const SmallVectorImpl<unsigned> &Ops, 535 int FI) const { 536 // Hexagon_TODO: Implement. 537 return(0); 538} 539 540 541unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { 542 543 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 544 const TargetRegisterClass *TRC; 545 if (VT == MVT::i1) { 546 TRC = &Hexagon::PredRegsRegClass; 547 } else if (VT == MVT::i32 || VT == MVT::f32) { 548 TRC = &Hexagon::IntRegsRegClass; 549 } else if (VT == MVT::i64 || VT == MVT::f64) { 550 TRC = &Hexagon::DoubleRegsRegClass; 551 } else { 552 llvm_unreachable("Cannot handle this register class"); 553 } 554 555 unsigned NewReg = RegInfo.createVirtualRegister(TRC); 556 return NewReg; 557} 558 559bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { 560 // Constant extenders are allowed only for V4 and above. 561 if (!Subtarget.hasV4TOps()) 562 return false; 563 564 const MCInstrDesc &MID = MI->getDesc(); 565 const uint64_t F = MID.TSFlags; 566 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask) 567 return true; 568 569 // TODO: This is largely obsolete now. Will need to be removed 570 // in consecutive patches. 571 switch(MI->getOpcode()) { 572 // TFR_FI Remains a special case. 573 case Hexagon::TFR_FI: 574 return true; 575 default: 576 return false; 577 } 578 return false; 579} 580 581// This returns true in two cases: 582// - The OP code itself indicates that this is an extended instruction. 583// - One of MOs has been marked with HMOTF_ConstExtended flag. 584bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { 585 // First check if this is permanently extended op code. 586 const uint64_t F = MI->getDesc().TSFlags; 587 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask) 588 return true; 589 // Use MO operand flags to determine if one of MI's operands 590 // has HMOTF_ConstExtended flag set. 591 for (MachineInstr::const_mop_iterator I = MI->operands_begin(), 592 E = MI->operands_end(); I != E; ++I) { 593 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended) 594 return true; 595 } 596 return false; 597} 598 599bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const { 600 switch (MI->getOpcode()) { 601 default: return false; 602 // JMP_EQri 603 case Hexagon::JMP_EQriPt_nv_V4: 604 case Hexagon::JMP_EQriPnt_nv_V4: 605 case Hexagon::JMP_EQriNotPt_nv_V4: 606 case Hexagon::JMP_EQriNotPnt_nv_V4: 607 case Hexagon::JMP_EQriPt_ie_nv_V4: 608 case Hexagon::JMP_EQriPnt_ie_nv_V4: 609 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 610 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 611 612 // JMP_EQri - with -1 613 case Hexagon::JMP_EQriPtneg_nv_V4: 614 case Hexagon::JMP_EQriPntneg_nv_V4: 615 case Hexagon::JMP_EQriNotPtneg_nv_V4: 616 case Hexagon::JMP_EQriNotPntneg_nv_V4: 617 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 618 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 619 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 620 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 621 622 // JMP_EQrr 623 case Hexagon::JMP_EQrrPt_nv_V4: 624 case Hexagon::JMP_EQrrPnt_nv_V4: 625 case Hexagon::JMP_EQrrNotPt_nv_V4: 626 case Hexagon::JMP_EQrrNotPnt_nv_V4: 627 case Hexagon::JMP_EQrrPt_ie_nv_V4: 628 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 629 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 630 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 631 632 // JMP_GTri 633 case Hexagon::JMP_GTriPt_nv_V4: 634 case Hexagon::JMP_GTriPnt_nv_V4: 635 case Hexagon::JMP_GTriNotPt_nv_V4: 636 case Hexagon::JMP_GTriNotPnt_nv_V4: 637 case Hexagon::JMP_GTriPt_ie_nv_V4: 638 case Hexagon::JMP_GTriPnt_ie_nv_V4: 639 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 640 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 641 642 // JMP_GTri - with -1 643 case Hexagon::JMP_GTriPtneg_nv_V4: 644 case Hexagon::JMP_GTriPntneg_nv_V4: 645 case Hexagon::JMP_GTriNotPtneg_nv_V4: 646 case Hexagon::JMP_GTriNotPntneg_nv_V4: 647 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 648 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 649 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 650 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 651 652 // JMP_GTrr 653 case Hexagon::JMP_GTrrPt_nv_V4: 654 case Hexagon::JMP_GTrrPnt_nv_V4: 655 case Hexagon::JMP_GTrrNotPt_nv_V4: 656 case Hexagon::JMP_GTrrNotPnt_nv_V4: 657 case Hexagon::JMP_GTrrPt_ie_nv_V4: 658 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 659 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 660 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 661 662 // JMP_GTrrdn 663 case Hexagon::JMP_GTrrdnPt_nv_V4: 664 case Hexagon::JMP_GTrrdnPnt_nv_V4: 665 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 666 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 667 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 668 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 669 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 670 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 671 672 // JMP_GTUri 673 case Hexagon::JMP_GTUriPt_nv_V4: 674 case Hexagon::JMP_GTUriPnt_nv_V4: 675 case Hexagon::JMP_GTUriNotPt_nv_V4: 676 case Hexagon::JMP_GTUriNotPnt_nv_V4: 677 case Hexagon::JMP_GTUriPt_ie_nv_V4: 678 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 679 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 680 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 681 682 // JMP_GTUrr 683 case Hexagon::JMP_GTUrrPt_nv_V4: 684 case Hexagon::JMP_GTUrrPnt_nv_V4: 685 case Hexagon::JMP_GTUrrNotPt_nv_V4: 686 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 687 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 688 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 689 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 690 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 691 692 // JMP_GTUrrdn 693 case Hexagon::JMP_GTUrrdnPt_nv_V4: 694 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 695 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 696 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 697 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 698 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 699 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 700 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 701 return true; 702 } 703} 704 705bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const { 706 switch (MI->getOpcode()) { 707 default: return false; 708 // Store Byte 709 case Hexagon::STrib_nv_V4: 710 case Hexagon::STrib_indexed_nv_V4: 711 case Hexagon::STrib_indexed_shl_nv_V4: 712 case Hexagon::STrib_shl_nv_V4: 713 case Hexagon::STb_GP_nv_V4: 714 case Hexagon::POST_STbri_nv_V4: 715 case Hexagon::STrib_cPt_nv_V4: 716 case Hexagon::STrib_cdnPt_nv_V4: 717 case Hexagon::STrib_cNotPt_nv_V4: 718 case Hexagon::STrib_cdnNotPt_nv_V4: 719 case Hexagon::STrib_indexed_cPt_nv_V4: 720 case Hexagon::STrib_indexed_cdnPt_nv_V4: 721 case Hexagon::STrib_indexed_cNotPt_nv_V4: 722 case Hexagon::STrib_indexed_cdnNotPt_nv_V4: 723 case Hexagon::STrib_indexed_shl_cPt_nv_V4: 724 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4: 725 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4: 726 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4: 727 case Hexagon::POST_STbri_cPt_nv_V4: 728 case Hexagon::POST_STbri_cdnPt_nv_V4: 729 case Hexagon::POST_STbri_cNotPt_nv_V4: 730 case Hexagon::POST_STbri_cdnNotPt_nv_V4: 731 case Hexagon::STb_GP_cPt_nv_V4: 732 case Hexagon::STb_GP_cNotPt_nv_V4: 733 case Hexagon::STb_GP_cdnPt_nv_V4: 734 case Hexagon::STb_GP_cdnNotPt_nv_V4: 735 case Hexagon::STrib_abs_nv_V4: 736 case Hexagon::STrib_abs_cPt_nv_V4: 737 case Hexagon::STrib_abs_cdnPt_nv_V4: 738 case Hexagon::STrib_abs_cNotPt_nv_V4: 739 case Hexagon::STrib_abs_cdnNotPt_nv_V4: 740 case Hexagon::STrib_imm_abs_nv_V4: 741 case Hexagon::STrib_imm_abs_cPt_nv_V4: 742 case Hexagon::STrib_imm_abs_cdnPt_nv_V4: 743 case Hexagon::STrib_imm_abs_cNotPt_nv_V4: 744 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4: 745 746 // Store Halfword 747 case Hexagon::STrih_nv_V4: 748 case Hexagon::STrih_indexed_nv_V4: 749 case Hexagon::STrih_indexed_shl_nv_V4: 750 case Hexagon::STrih_shl_nv_V4: 751 case Hexagon::STh_GP_nv_V4: 752 case Hexagon::POST_SThri_nv_V4: 753 case Hexagon::STrih_cPt_nv_V4: 754 case Hexagon::STrih_cdnPt_nv_V4: 755 case Hexagon::STrih_cNotPt_nv_V4: 756 case Hexagon::STrih_cdnNotPt_nv_V4: 757 case Hexagon::STrih_indexed_cPt_nv_V4: 758 case Hexagon::STrih_indexed_cdnPt_nv_V4: 759 case Hexagon::STrih_indexed_cNotPt_nv_V4: 760 case Hexagon::STrih_indexed_cdnNotPt_nv_V4: 761 case Hexagon::STrih_indexed_shl_cPt_nv_V4: 762 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4: 763 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4: 764 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4: 765 case Hexagon::POST_SThri_cPt_nv_V4: 766 case Hexagon::POST_SThri_cdnPt_nv_V4: 767 case Hexagon::POST_SThri_cNotPt_nv_V4: 768 case Hexagon::POST_SThri_cdnNotPt_nv_V4: 769 case Hexagon::STh_GP_cPt_nv_V4: 770 case Hexagon::STh_GP_cNotPt_nv_V4: 771 case Hexagon::STh_GP_cdnPt_nv_V4: 772 case Hexagon::STh_GP_cdnNotPt_nv_V4: 773 case Hexagon::STrih_abs_nv_V4: 774 case Hexagon::STrih_abs_cPt_nv_V4: 775 case Hexagon::STrih_abs_cdnPt_nv_V4: 776 case Hexagon::STrih_abs_cNotPt_nv_V4: 777 case Hexagon::STrih_abs_cdnNotPt_nv_V4: 778 case Hexagon::STrih_imm_abs_nv_V4: 779 case Hexagon::STrih_imm_abs_cPt_nv_V4: 780 case Hexagon::STrih_imm_abs_cdnPt_nv_V4: 781 case Hexagon::STrih_imm_abs_cNotPt_nv_V4: 782 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4: 783 784 // Store Word 785 case Hexagon::STriw_nv_V4: 786 case Hexagon::STriw_indexed_nv_V4: 787 case Hexagon::STriw_indexed_shl_nv_V4: 788 case Hexagon::STriw_shl_nv_V4: 789 case Hexagon::STw_GP_nv_V4: 790 case Hexagon::POST_STwri_nv_V4: 791 case Hexagon::STriw_cPt_nv_V4: 792 case Hexagon::STriw_cdnPt_nv_V4: 793 case Hexagon::STriw_cNotPt_nv_V4: 794 case Hexagon::STriw_cdnNotPt_nv_V4: 795 case Hexagon::STriw_indexed_cPt_nv_V4: 796 case Hexagon::STriw_indexed_cdnPt_nv_V4: 797 case Hexagon::STriw_indexed_cNotPt_nv_V4: 798 case Hexagon::STriw_indexed_cdnNotPt_nv_V4: 799 case Hexagon::STriw_indexed_shl_cPt_nv_V4: 800 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4: 801 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4: 802 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4: 803 case Hexagon::POST_STwri_cPt_nv_V4: 804 case Hexagon::POST_STwri_cdnPt_nv_V4: 805 case Hexagon::POST_STwri_cNotPt_nv_V4: 806 case Hexagon::POST_STwri_cdnNotPt_nv_V4: 807 case Hexagon::STw_GP_cPt_nv_V4: 808 case Hexagon::STw_GP_cNotPt_nv_V4: 809 case Hexagon::STw_GP_cdnPt_nv_V4: 810 case Hexagon::STw_GP_cdnNotPt_nv_V4: 811 case Hexagon::STriw_abs_nv_V4: 812 case Hexagon::STriw_abs_cPt_nv_V4: 813 case Hexagon::STriw_abs_cdnPt_nv_V4: 814 case Hexagon::STriw_abs_cNotPt_nv_V4: 815 case Hexagon::STriw_abs_cdnNotPt_nv_V4: 816 case Hexagon::STriw_imm_abs_nv_V4: 817 case Hexagon::STriw_imm_abs_cPt_nv_V4: 818 case Hexagon::STriw_imm_abs_cdnPt_nv_V4: 819 case Hexagon::STriw_imm_abs_cNotPt_nv_V4: 820 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4: 821 return true; 822 } 823} 824 825bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const { 826 switch (MI->getOpcode()) 827 { 828 default: return false; 829 // Load Byte 830 case Hexagon::POST_LDrib: 831 case Hexagon::POST_LDrib_cPt: 832 case Hexagon::POST_LDrib_cNotPt: 833 case Hexagon::POST_LDrib_cdnPt_V4: 834 case Hexagon::POST_LDrib_cdnNotPt_V4: 835 836 // Load unsigned byte 837 case Hexagon::POST_LDriub: 838 case Hexagon::POST_LDriub_cPt: 839 case Hexagon::POST_LDriub_cNotPt: 840 case Hexagon::POST_LDriub_cdnPt_V4: 841 case Hexagon::POST_LDriub_cdnNotPt_V4: 842 843 // Load halfword 844 case Hexagon::POST_LDrih: 845 case Hexagon::POST_LDrih_cPt: 846 case Hexagon::POST_LDrih_cNotPt: 847 case Hexagon::POST_LDrih_cdnPt_V4: 848 case Hexagon::POST_LDrih_cdnNotPt_V4: 849 850 // Load unsigned halfword 851 case Hexagon::POST_LDriuh: 852 case Hexagon::POST_LDriuh_cPt: 853 case Hexagon::POST_LDriuh_cNotPt: 854 case Hexagon::POST_LDriuh_cdnPt_V4: 855 case Hexagon::POST_LDriuh_cdnNotPt_V4: 856 857 // Load word 858 case Hexagon::POST_LDriw: 859 case Hexagon::POST_LDriw_cPt: 860 case Hexagon::POST_LDriw_cNotPt: 861 case Hexagon::POST_LDriw_cdnPt_V4: 862 case Hexagon::POST_LDriw_cdnNotPt_V4: 863 864 // Load double word 865 case Hexagon::POST_LDrid: 866 case Hexagon::POST_LDrid_cPt: 867 case Hexagon::POST_LDrid_cNotPt: 868 case Hexagon::POST_LDrid_cdnPt_V4: 869 case Hexagon::POST_LDrid_cdnNotPt_V4: 870 871 // Store byte 872 case Hexagon::POST_STbri: 873 case Hexagon::POST_STbri_cPt: 874 case Hexagon::POST_STbri_cNotPt: 875 case Hexagon::POST_STbri_cdnPt_V4: 876 case Hexagon::POST_STbri_cdnNotPt_V4: 877 878 // Store halfword 879 case Hexagon::POST_SThri: 880 case Hexagon::POST_SThri_cPt: 881 case Hexagon::POST_SThri_cNotPt: 882 case Hexagon::POST_SThri_cdnPt_V4: 883 case Hexagon::POST_SThri_cdnNotPt_V4: 884 885 // Store word 886 case Hexagon::POST_STwri: 887 case Hexagon::POST_STwri_cPt: 888 case Hexagon::POST_STwri_cNotPt: 889 case Hexagon::POST_STwri_cdnPt_V4: 890 case Hexagon::POST_STwri_cdnNotPt_V4: 891 892 // Store double word 893 case Hexagon::POST_STdri: 894 case Hexagon::POST_STdri_cPt: 895 case Hexagon::POST_STdri_cNotPt: 896 case Hexagon::POST_STdri_cdnPt_V4: 897 case Hexagon::POST_STdri_cdnNotPt_V4: 898 return true; 899 } 900} 901 902bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const { 903 if (isNewValueJump(MI)) 904 return true; 905 906 if (isNewValueStore(MI)) 907 return true; 908 909 return false; 910} 911 912bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const { 913 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4; 914} 915 916bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { 917 bool isPred = MI->getDesc().isPredicable(); 918 919 if (!isPred) 920 return false; 921 922 const int Opc = MI->getOpcode(); 923 924 switch(Opc) { 925 case Hexagon::TFRI: 926 return isInt<12>(MI->getOperand(1).getImm()); 927 928 case Hexagon::STrid: 929 case Hexagon::STrid_indexed: 930 return isShiftedUInt<6,3>(MI->getOperand(1).getImm()); 931 932 case Hexagon::STriw: 933 case Hexagon::STriw_indexed: 934 case Hexagon::STriw_nv_V4: 935 return isShiftedUInt<6,2>(MI->getOperand(1).getImm()); 936 937 case Hexagon::STrih: 938 case Hexagon::STrih_indexed: 939 case Hexagon::STrih_nv_V4: 940 return isShiftedUInt<6,1>(MI->getOperand(1).getImm()); 941 942 case Hexagon::STrib: 943 case Hexagon::STrib_indexed: 944 case Hexagon::STrib_nv_V4: 945 return isUInt<6>(MI->getOperand(1).getImm()); 946 947 case Hexagon::LDrid: 948 case Hexagon::LDrid_indexed: 949 return isShiftedUInt<6,3>(MI->getOperand(2).getImm()); 950 951 case Hexagon::LDriw: 952 case Hexagon::LDriw_indexed: 953 return isShiftedUInt<6,2>(MI->getOperand(2).getImm()); 954 955 case Hexagon::LDrih: 956 case Hexagon::LDriuh: 957 case Hexagon::LDrih_indexed: 958 case Hexagon::LDriuh_indexed: 959 return isShiftedUInt<6,1>(MI->getOperand(2).getImm()); 960 961 case Hexagon::LDrib: 962 case Hexagon::LDriub: 963 case Hexagon::LDrib_indexed: 964 case Hexagon::LDriub_indexed: 965 return isUInt<6>(MI->getOperand(2).getImm()); 966 967 case Hexagon::POST_LDrid: 968 return isShiftedInt<4,3>(MI->getOperand(3).getImm()); 969 970 case Hexagon::POST_LDriw: 971 return isShiftedInt<4,2>(MI->getOperand(3).getImm()); 972 973 case Hexagon::POST_LDrih: 974 case Hexagon::POST_LDriuh: 975 return isShiftedInt<4,1>(MI->getOperand(3).getImm()); 976 977 case Hexagon::POST_LDrib: 978 case Hexagon::POST_LDriub: 979 return isInt<4>(MI->getOperand(3).getImm()); 980 981 case Hexagon::STrib_imm_V4: 982 case Hexagon::STrih_imm_V4: 983 case Hexagon::STriw_imm_V4: 984 return (isUInt<6>(MI->getOperand(1).getImm()) && 985 isInt<6>(MI->getOperand(2).getImm())); 986 987 case Hexagon::ADD_ri: 988 return isInt<8>(MI->getOperand(2).getImm()); 989 990 case Hexagon::ASLH: 991 case Hexagon::ASRH: 992 case Hexagon::SXTB: 993 case Hexagon::SXTH: 994 case Hexagon::ZXTB: 995 case Hexagon::ZXTH: 996 return Subtarget.hasV4TOps(); 997 998 case Hexagon::JMPR: 999 return false; 1000 } 1001 1002 return true; 1003} 1004 1005// This function performs the following inversiones: 1006// 1007// cPt ---> cNotPt 1008// cNotPt ---> cPt 1009// 1010// however, these inversiones are NOT included: 1011// 1012// cdnPt -X-> cdnNotPt 1013// cdnNotPt -X-> cdnPt 1014// cPt_nv -X-> cNotPt_nv (new value stores) 1015// cNotPt_nv -X-> cPt_nv (new value stores) 1016// 1017// because only the following transformations are allowed: 1018// 1019// cNotPt ---> cdnNotPt 1020// cPt ---> cdnPt 1021// cNotPt ---> cNotPt_nv 1022// cPt ---> cPt_nv 1023unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { 1024 switch(Opc) { 1025 default: llvm_unreachable("Unexpected predicated instruction"); 1026 case Hexagon::TFR_cPt: 1027 return Hexagon::TFR_cNotPt; 1028 case Hexagon::TFR_cNotPt: 1029 return Hexagon::TFR_cPt; 1030 1031 case Hexagon::TFRI_cPt: 1032 return Hexagon::TFRI_cNotPt; 1033 case Hexagon::TFRI_cNotPt: 1034 return Hexagon::TFRI_cPt; 1035 1036 case Hexagon::JMP_c: 1037 return Hexagon::JMP_cNot; 1038 case Hexagon::JMP_cNot: 1039 return Hexagon::JMP_c; 1040 1041 case Hexagon::ADD_ri_cPt: 1042 return Hexagon::ADD_ri_cNotPt; 1043 case Hexagon::ADD_ri_cNotPt: 1044 return Hexagon::ADD_ri_cPt; 1045 1046 case Hexagon::ADD_rr_cPt: 1047 return Hexagon::ADD_rr_cNotPt; 1048 case Hexagon::ADD_rr_cNotPt: 1049 return Hexagon::ADD_rr_cPt; 1050 1051 case Hexagon::XOR_rr_cPt: 1052 return Hexagon::XOR_rr_cNotPt; 1053 case Hexagon::XOR_rr_cNotPt: 1054 return Hexagon::XOR_rr_cPt; 1055 1056 case Hexagon::AND_rr_cPt: 1057 return Hexagon::AND_rr_cNotPt; 1058 case Hexagon::AND_rr_cNotPt: 1059 return Hexagon::AND_rr_cPt; 1060 1061 case Hexagon::OR_rr_cPt: 1062 return Hexagon::OR_rr_cNotPt; 1063 case Hexagon::OR_rr_cNotPt: 1064 return Hexagon::OR_rr_cPt; 1065 1066 case Hexagon::SUB_rr_cPt: 1067 return Hexagon::SUB_rr_cNotPt; 1068 case Hexagon::SUB_rr_cNotPt: 1069 return Hexagon::SUB_rr_cPt; 1070 1071 case Hexagon::COMBINE_rr_cPt: 1072 return Hexagon::COMBINE_rr_cNotPt; 1073 case Hexagon::COMBINE_rr_cNotPt: 1074 return Hexagon::COMBINE_rr_cPt; 1075 1076 case Hexagon::ASLH_cPt_V4: 1077 return Hexagon::ASLH_cNotPt_V4; 1078 case Hexagon::ASLH_cNotPt_V4: 1079 return Hexagon::ASLH_cPt_V4; 1080 1081 case Hexagon::ASRH_cPt_V4: 1082 return Hexagon::ASRH_cNotPt_V4; 1083 case Hexagon::ASRH_cNotPt_V4: 1084 return Hexagon::ASRH_cPt_V4; 1085 1086 case Hexagon::SXTB_cPt_V4: 1087 return Hexagon::SXTB_cNotPt_V4; 1088 case Hexagon::SXTB_cNotPt_V4: 1089 return Hexagon::SXTB_cPt_V4; 1090 1091 case Hexagon::SXTH_cPt_V4: 1092 return Hexagon::SXTH_cNotPt_V4; 1093 case Hexagon::SXTH_cNotPt_V4: 1094 return Hexagon::SXTH_cPt_V4; 1095 1096 case Hexagon::ZXTB_cPt_V4: 1097 return Hexagon::ZXTB_cNotPt_V4; 1098 case Hexagon::ZXTB_cNotPt_V4: 1099 return Hexagon::ZXTB_cPt_V4; 1100 1101 case Hexagon::ZXTH_cPt_V4: 1102 return Hexagon::ZXTH_cNotPt_V4; 1103 case Hexagon::ZXTH_cNotPt_V4: 1104 return Hexagon::ZXTH_cPt_V4; 1105 1106 1107 case Hexagon::JMPR_cPt: 1108 return Hexagon::JMPR_cNotPt; 1109 case Hexagon::JMPR_cNotPt: 1110 return Hexagon::JMPR_cPt; 1111 1112 // V4 indexed+scaled load. 1113 case Hexagon::LDrid_indexed_shl_cPt_V4: 1114 return Hexagon::LDrid_indexed_shl_cNotPt_V4; 1115 case Hexagon::LDrid_indexed_shl_cNotPt_V4: 1116 return Hexagon::LDrid_indexed_shl_cPt_V4; 1117 1118 case Hexagon::LDrib_indexed_shl_cPt_V4: 1119 return Hexagon::LDrib_indexed_shl_cNotPt_V4; 1120 case Hexagon::LDrib_indexed_shl_cNotPt_V4: 1121 return Hexagon::LDrib_indexed_shl_cPt_V4; 1122 1123 case Hexagon::LDriub_indexed_shl_cPt_V4: 1124 return Hexagon::LDriub_indexed_shl_cNotPt_V4; 1125 case Hexagon::LDriub_indexed_shl_cNotPt_V4: 1126 return Hexagon::LDriub_indexed_shl_cPt_V4; 1127 1128 case Hexagon::LDrih_indexed_shl_cPt_V4: 1129 return Hexagon::LDrih_indexed_shl_cNotPt_V4; 1130 case Hexagon::LDrih_indexed_shl_cNotPt_V4: 1131 return Hexagon::LDrih_indexed_shl_cPt_V4; 1132 1133 case Hexagon::LDriuh_indexed_shl_cPt_V4: 1134 return Hexagon::LDriuh_indexed_shl_cNotPt_V4; 1135 case Hexagon::LDriuh_indexed_shl_cNotPt_V4: 1136 return Hexagon::LDriuh_indexed_shl_cPt_V4; 1137 1138 case Hexagon::LDriw_indexed_shl_cPt_V4: 1139 return Hexagon::LDriw_indexed_shl_cNotPt_V4; 1140 case Hexagon::LDriw_indexed_shl_cNotPt_V4: 1141 return Hexagon::LDriw_indexed_shl_cPt_V4; 1142 1143 // Byte. 1144 case Hexagon::POST_STbri_cPt: 1145 return Hexagon::POST_STbri_cNotPt; 1146 case Hexagon::POST_STbri_cNotPt: 1147 return Hexagon::POST_STbri_cPt; 1148 1149 case Hexagon::STrib_cPt: 1150 return Hexagon::STrib_cNotPt; 1151 case Hexagon::STrib_cNotPt: 1152 return Hexagon::STrib_cPt; 1153 1154 case Hexagon::STrib_indexed_cPt: 1155 return Hexagon::STrib_indexed_cNotPt; 1156 case Hexagon::STrib_indexed_cNotPt: 1157 return Hexagon::STrib_indexed_cPt; 1158 1159 case Hexagon::STrib_imm_cPt_V4: 1160 return Hexagon::STrib_imm_cNotPt_V4; 1161 case Hexagon::STrib_imm_cNotPt_V4: 1162 return Hexagon::STrib_imm_cPt_V4; 1163 1164 case Hexagon::STrib_indexed_shl_cPt_V4: 1165 return Hexagon::STrib_indexed_shl_cNotPt_V4; 1166 case Hexagon::STrib_indexed_shl_cNotPt_V4: 1167 return Hexagon::STrib_indexed_shl_cPt_V4; 1168 1169 // Halfword. 1170 case Hexagon::POST_SThri_cPt: 1171 return Hexagon::POST_SThri_cNotPt; 1172 case Hexagon::POST_SThri_cNotPt: 1173 return Hexagon::POST_SThri_cPt; 1174 1175 case Hexagon::STrih_cPt: 1176 return Hexagon::STrih_cNotPt; 1177 case Hexagon::STrih_cNotPt: 1178 return Hexagon::STrih_cPt; 1179 1180 case Hexagon::STrih_indexed_cPt: 1181 return Hexagon::STrih_indexed_cNotPt; 1182 case Hexagon::STrih_indexed_cNotPt: 1183 return Hexagon::STrih_indexed_cPt; 1184 1185 case Hexagon::STrih_imm_cPt_V4: 1186 return Hexagon::STrih_imm_cNotPt_V4; 1187 case Hexagon::STrih_imm_cNotPt_V4: 1188 return Hexagon::STrih_imm_cPt_V4; 1189 1190 case Hexagon::STrih_indexed_shl_cPt_V4: 1191 return Hexagon::STrih_indexed_shl_cNotPt_V4; 1192 case Hexagon::STrih_indexed_shl_cNotPt_V4: 1193 return Hexagon::STrih_indexed_shl_cPt_V4; 1194 1195 // Word. 1196 case Hexagon::POST_STwri_cPt: 1197 return Hexagon::POST_STwri_cNotPt; 1198 case Hexagon::POST_STwri_cNotPt: 1199 return Hexagon::POST_STwri_cPt; 1200 1201 case Hexagon::STriw_cPt: 1202 return Hexagon::STriw_cNotPt; 1203 case Hexagon::STriw_cNotPt: 1204 return Hexagon::STriw_cPt; 1205 1206 case Hexagon::STriw_indexed_cPt: 1207 return Hexagon::STriw_indexed_cNotPt; 1208 case Hexagon::STriw_indexed_cNotPt: 1209 return Hexagon::STriw_indexed_cPt; 1210 1211 case Hexagon::STriw_indexed_shl_cPt_V4: 1212 return Hexagon::STriw_indexed_shl_cNotPt_V4; 1213 case Hexagon::STriw_indexed_shl_cNotPt_V4: 1214 return Hexagon::STriw_indexed_shl_cPt_V4; 1215 1216 case Hexagon::STriw_imm_cPt_V4: 1217 return Hexagon::STriw_imm_cNotPt_V4; 1218 case Hexagon::STriw_imm_cNotPt_V4: 1219 return Hexagon::STriw_imm_cPt_V4; 1220 1221 // Double word. 1222 case Hexagon::POST_STdri_cPt: 1223 return Hexagon::POST_STdri_cNotPt; 1224 case Hexagon::POST_STdri_cNotPt: 1225 return Hexagon::POST_STdri_cPt; 1226 1227 case Hexagon::STrid_cPt: 1228 return Hexagon::STrid_cNotPt; 1229 case Hexagon::STrid_cNotPt: 1230 return Hexagon::STrid_cPt; 1231 1232 case Hexagon::STrid_indexed_cPt: 1233 return Hexagon::STrid_indexed_cNotPt; 1234 case Hexagon::STrid_indexed_cNotPt: 1235 return Hexagon::STrid_indexed_cPt; 1236 1237 case Hexagon::STrid_indexed_shl_cPt_V4: 1238 return Hexagon::STrid_indexed_shl_cNotPt_V4; 1239 case Hexagon::STrid_indexed_shl_cNotPt_V4: 1240 return Hexagon::STrid_indexed_shl_cPt_V4; 1241 1242 // V4 Store to global address. 1243 case Hexagon::STd_GP_cPt_V4: 1244 return Hexagon::STd_GP_cNotPt_V4; 1245 case Hexagon::STd_GP_cNotPt_V4: 1246 return Hexagon::STd_GP_cPt_V4; 1247 1248 case Hexagon::STb_GP_cPt_V4: 1249 return Hexagon::STb_GP_cNotPt_V4; 1250 case Hexagon::STb_GP_cNotPt_V4: 1251 return Hexagon::STb_GP_cPt_V4; 1252 1253 case Hexagon::STh_GP_cPt_V4: 1254 return Hexagon::STh_GP_cNotPt_V4; 1255 case Hexagon::STh_GP_cNotPt_V4: 1256 return Hexagon::STh_GP_cPt_V4; 1257 1258 case Hexagon::STw_GP_cPt_V4: 1259 return Hexagon::STw_GP_cNotPt_V4; 1260 case Hexagon::STw_GP_cNotPt_V4: 1261 return Hexagon::STw_GP_cPt_V4; 1262 1263 // Load. 1264 case Hexagon::LDrid_cPt: 1265 return Hexagon::LDrid_cNotPt; 1266 case Hexagon::LDrid_cNotPt: 1267 return Hexagon::LDrid_cPt; 1268 1269 case Hexagon::LDriw_cPt: 1270 return Hexagon::LDriw_cNotPt; 1271 case Hexagon::LDriw_cNotPt: 1272 return Hexagon::LDriw_cPt; 1273 1274 case Hexagon::LDrih_cPt: 1275 return Hexagon::LDrih_cNotPt; 1276 case Hexagon::LDrih_cNotPt: 1277 return Hexagon::LDrih_cPt; 1278 1279 case Hexagon::LDriuh_cPt: 1280 return Hexagon::LDriuh_cNotPt; 1281 case Hexagon::LDriuh_cNotPt: 1282 return Hexagon::LDriuh_cPt; 1283 1284 case Hexagon::LDrib_cPt: 1285 return Hexagon::LDrib_cNotPt; 1286 case Hexagon::LDrib_cNotPt: 1287 return Hexagon::LDrib_cPt; 1288 1289 case Hexagon::LDriub_cPt: 1290 return Hexagon::LDriub_cNotPt; 1291 case Hexagon::LDriub_cNotPt: 1292 return Hexagon::LDriub_cPt; 1293 1294 // Load Indexed. 1295 case Hexagon::LDrid_indexed_cPt: 1296 return Hexagon::LDrid_indexed_cNotPt; 1297 case Hexagon::LDrid_indexed_cNotPt: 1298 return Hexagon::LDrid_indexed_cPt; 1299 1300 case Hexagon::LDriw_indexed_cPt: 1301 return Hexagon::LDriw_indexed_cNotPt; 1302 case Hexagon::LDriw_indexed_cNotPt: 1303 return Hexagon::LDriw_indexed_cPt; 1304 1305 case Hexagon::LDrih_indexed_cPt: 1306 return Hexagon::LDrih_indexed_cNotPt; 1307 case Hexagon::LDrih_indexed_cNotPt: 1308 return Hexagon::LDrih_indexed_cPt; 1309 1310 case Hexagon::LDriuh_indexed_cPt: 1311 return Hexagon::LDriuh_indexed_cNotPt; 1312 case Hexagon::LDriuh_indexed_cNotPt: 1313 return Hexagon::LDriuh_indexed_cPt; 1314 1315 case Hexagon::LDrib_indexed_cPt: 1316 return Hexagon::LDrib_indexed_cNotPt; 1317 case Hexagon::LDrib_indexed_cNotPt: 1318 return Hexagon::LDrib_indexed_cPt; 1319 1320 case Hexagon::LDriub_indexed_cPt: 1321 return Hexagon::LDriub_indexed_cNotPt; 1322 case Hexagon::LDriub_indexed_cNotPt: 1323 return Hexagon::LDriub_indexed_cPt; 1324 1325 // Post Inc Load. 1326 case Hexagon::POST_LDrid_cPt: 1327 return Hexagon::POST_LDrid_cNotPt; 1328 case Hexagon::POST_LDriw_cNotPt: 1329 return Hexagon::POST_LDriw_cPt; 1330 1331 case Hexagon::POST_LDrih_cPt: 1332 return Hexagon::POST_LDrih_cNotPt; 1333 case Hexagon::POST_LDrih_cNotPt: 1334 return Hexagon::POST_LDrih_cPt; 1335 1336 case Hexagon::POST_LDriuh_cPt: 1337 return Hexagon::POST_LDriuh_cNotPt; 1338 case Hexagon::POST_LDriuh_cNotPt: 1339 return Hexagon::POST_LDriuh_cPt; 1340 1341 case Hexagon::POST_LDrib_cPt: 1342 return Hexagon::POST_LDrib_cNotPt; 1343 case Hexagon::POST_LDrib_cNotPt: 1344 return Hexagon::POST_LDrib_cPt; 1345 1346 case Hexagon::POST_LDriub_cPt: 1347 return Hexagon::POST_LDriub_cNotPt; 1348 case Hexagon::POST_LDriub_cNotPt: 1349 return Hexagon::POST_LDriub_cPt; 1350 1351 // Dealloc_return. 1352 case Hexagon::DEALLOC_RET_cPt_V4: 1353 return Hexagon::DEALLOC_RET_cNotPt_V4; 1354 case Hexagon::DEALLOC_RET_cNotPt_V4: 1355 return Hexagon::DEALLOC_RET_cPt_V4; 1356 1357 // New Value Jump. 1358 // JMPEQ_ri - with -1. 1359 case Hexagon::JMP_EQriPtneg_nv_V4: 1360 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1361 case Hexagon::JMP_EQriNotPtneg_nv_V4: 1362 return Hexagon::JMP_EQriPtneg_nv_V4; 1363 1364 case Hexagon::JMP_EQriPntneg_nv_V4: 1365 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1366 case Hexagon::JMP_EQriNotPntneg_nv_V4: 1367 return Hexagon::JMP_EQriPntneg_nv_V4; 1368 1369 // JMPEQ_ri. 1370 case Hexagon::JMP_EQriPt_nv_V4: 1371 return Hexagon::JMP_EQriNotPt_nv_V4; 1372 case Hexagon::JMP_EQriNotPt_nv_V4: 1373 return Hexagon::JMP_EQriPt_nv_V4; 1374 1375 case Hexagon::JMP_EQriPnt_nv_V4: 1376 return Hexagon::JMP_EQriNotPnt_nv_V4; 1377 case Hexagon::JMP_EQriNotPnt_nv_V4: 1378 return Hexagon::JMP_EQriPnt_nv_V4; 1379 1380 // JMPEQ_rr. 1381 case Hexagon::JMP_EQrrPt_nv_V4: 1382 return Hexagon::JMP_EQrrNotPt_nv_V4; 1383 case Hexagon::JMP_EQrrNotPt_nv_V4: 1384 return Hexagon::JMP_EQrrPt_nv_V4; 1385 1386 case Hexagon::JMP_EQrrPnt_nv_V4: 1387 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1388 case Hexagon::JMP_EQrrNotPnt_nv_V4: 1389 return Hexagon::JMP_EQrrPnt_nv_V4; 1390 1391 // JMPGT_ri - with -1. 1392 case Hexagon::JMP_GTriPtneg_nv_V4: 1393 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1394 case Hexagon::JMP_GTriNotPtneg_nv_V4: 1395 return Hexagon::JMP_GTriPtneg_nv_V4; 1396 1397 case Hexagon::JMP_GTriPntneg_nv_V4: 1398 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1399 case Hexagon::JMP_GTriNotPntneg_nv_V4: 1400 return Hexagon::JMP_GTriPntneg_nv_V4; 1401 1402 // JMPGT_ri. 1403 case Hexagon::JMP_GTriPt_nv_V4: 1404 return Hexagon::JMP_GTriNotPt_nv_V4; 1405 case Hexagon::JMP_GTriNotPt_nv_V4: 1406 return Hexagon::JMP_GTriPt_nv_V4; 1407 1408 case Hexagon::JMP_GTriPnt_nv_V4: 1409 return Hexagon::JMP_GTriNotPnt_nv_V4; 1410 case Hexagon::JMP_GTriNotPnt_nv_V4: 1411 return Hexagon::JMP_GTriPnt_nv_V4; 1412 1413 // JMPGT_rr. 1414 case Hexagon::JMP_GTrrPt_nv_V4: 1415 return Hexagon::JMP_GTrrNotPt_nv_V4; 1416 case Hexagon::JMP_GTrrNotPt_nv_V4: 1417 return Hexagon::JMP_GTrrPt_nv_V4; 1418 1419 case Hexagon::JMP_GTrrPnt_nv_V4: 1420 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1421 case Hexagon::JMP_GTrrNotPnt_nv_V4: 1422 return Hexagon::JMP_GTrrPnt_nv_V4; 1423 1424 // JMPGT_rrdn. 1425 case Hexagon::JMP_GTrrdnPt_nv_V4: 1426 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1427 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 1428 return Hexagon::JMP_GTrrdnPt_nv_V4; 1429 1430 case Hexagon::JMP_GTrrdnPnt_nv_V4: 1431 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1432 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 1433 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1434 1435 // JMPGTU_ri. 1436 case Hexagon::JMP_GTUriPt_nv_V4: 1437 return Hexagon::JMP_GTUriNotPt_nv_V4; 1438 case Hexagon::JMP_GTUriNotPt_nv_V4: 1439 return Hexagon::JMP_GTUriPt_nv_V4; 1440 1441 case Hexagon::JMP_GTUriPnt_nv_V4: 1442 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1443 case Hexagon::JMP_GTUriNotPnt_nv_V4: 1444 return Hexagon::JMP_GTUriPnt_nv_V4; 1445 1446 // JMPGTU_rr. 1447 case Hexagon::JMP_GTUrrPt_nv_V4: 1448 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1449 case Hexagon::JMP_GTUrrNotPt_nv_V4: 1450 return Hexagon::JMP_GTUrrPt_nv_V4; 1451 1452 case Hexagon::JMP_GTUrrPnt_nv_V4: 1453 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1454 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 1455 return Hexagon::JMP_GTUrrPnt_nv_V4; 1456 1457 // JMPGTU_rrdn. 1458 case Hexagon::JMP_GTUrrdnPt_nv_V4: 1459 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1460 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 1461 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1462 1463 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 1464 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1465 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 1466 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1467 } 1468} 1469 1470 1471int HexagonInstrInfo:: 1472getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { 1473 enum Hexagon::PredSense inPredSense; 1474 inPredSense = invertPredicate ? Hexagon::PredSense_false : 1475 Hexagon::PredSense_true; 1476 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense); 1477 if (CondOpcode >= 0) // Valid Conditional opcode/instruction 1478 return CondOpcode; 1479 1480 // This switch case will be removed once all the instructions have been 1481 // modified to use relation maps. 1482 switch(Opc) { 1483 case Hexagon::TFR: 1484 return !invertPredicate ? Hexagon::TFR_cPt : 1485 Hexagon::TFR_cNotPt; 1486 case Hexagon::TFRI_f: 1487 return !invertPredicate ? Hexagon::TFRI_cPt_f : 1488 Hexagon::TFRI_cNotPt_f; 1489 case Hexagon::TFRI: 1490 return !invertPredicate ? Hexagon::TFRI_cPt : 1491 Hexagon::TFRI_cNotPt; 1492 case Hexagon::JMP: 1493 return !invertPredicate ? Hexagon::JMP_c : 1494 Hexagon::JMP_cNot; 1495 case Hexagon::JMP_EQrrPt_nv_V4: 1496 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 : 1497 Hexagon::JMP_EQrrNotPt_nv_V4; 1498 case Hexagon::JMP_EQriPt_nv_V4: 1499 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 : 1500 Hexagon::JMP_EQriNotPt_nv_V4; 1501 case Hexagon::COMBINE_rr: 1502 return !invertPredicate ? Hexagon::COMBINE_rr_cPt : 1503 Hexagon::COMBINE_rr_cNotPt; 1504 case Hexagon::ASLH: 1505 return !invertPredicate ? Hexagon::ASLH_cPt_V4 : 1506 Hexagon::ASLH_cNotPt_V4; 1507 case Hexagon::ASRH: 1508 return !invertPredicate ? Hexagon::ASRH_cPt_V4 : 1509 Hexagon::ASRH_cNotPt_V4; 1510 case Hexagon::SXTB: 1511 return !invertPredicate ? Hexagon::SXTB_cPt_V4 : 1512 Hexagon::SXTB_cNotPt_V4; 1513 case Hexagon::SXTH: 1514 return !invertPredicate ? Hexagon::SXTH_cPt_V4 : 1515 Hexagon::SXTH_cNotPt_V4; 1516 case Hexagon::ZXTB: 1517 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 : 1518 Hexagon::ZXTB_cNotPt_V4; 1519 case Hexagon::ZXTH: 1520 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 : 1521 Hexagon::ZXTH_cNotPt_V4; 1522 1523 case Hexagon::JMPR: 1524 return !invertPredicate ? Hexagon::JMPR_cPt : 1525 Hexagon::JMPR_cNotPt; 1526 1527 // V4 indexed+scaled load. 1528 case Hexagon::LDrid_indexed_shl_V4: 1529 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 : 1530 Hexagon::LDrid_indexed_shl_cNotPt_V4; 1531 case Hexagon::LDrib_indexed_shl_V4: 1532 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 : 1533 Hexagon::LDrib_indexed_shl_cNotPt_V4; 1534 case Hexagon::LDriub_indexed_shl_V4: 1535 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 : 1536 Hexagon::LDriub_indexed_shl_cNotPt_V4; 1537 case Hexagon::LDrih_indexed_shl_V4: 1538 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 : 1539 Hexagon::LDrih_indexed_shl_cNotPt_V4; 1540 case Hexagon::LDriuh_indexed_shl_V4: 1541 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 : 1542 Hexagon::LDriuh_indexed_shl_cNotPt_V4; 1543 case Hexagon::LDriw_indexed_shl_V4: 1544 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 : 1545 Hexagon::LDriw_indexed_shl_cNotPt_V4; 1546 1547 // V4 Load from global address 1548 case Hexagon::LDd_GP_V4: 1549 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 : 1550 Hexagon::LDd_GP_cNotPt_V4; 1551 case Hexagon::LDb_GP_V4: 1552 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 : 1553 Hexagon::LDb_GP_cNotPt_V4; 1554 case Hexagon::LDub_GP_V4: 1555 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 : 1556 Hexagon::LDub_GP_cNotPt_V4; 1557 case Hexagon::LDh_GP_V4: 1558 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 : 1559 Hexagon::LDh_GP_cNotPt_V4; 1560 case Hexagon::LDuh_GP_V4: 1561 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 : 1562 Hexagon::LDuh_GP_cNotPt_V4; 1563 case Hexagon::LDw_GP_V4: 1564 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 : 1565 Hexagon::LDw_GP_cNotPt_V4; 1566 1567 // Byte. 1568 case Hexagon::POST_STbri: 1569 return !invertPredicate ? Hexagon::POST_STbri_cPt : 1570 Hexagon::POST_STbri_cNotPt; 1571 case Hexagon::STrib: 1572 return !invertPredicate ? Hexagon::STrib_cPt : 1573 Hexagon::STrib_cNotPt; 1574 case Hexagon::STrib_indexed: 1575 return !invertPredicate ? Hexagon::STrib_indexed_cPt : 1576 Hexagon::STrib_indexed_cNotPt; 1577 case Hexagon::STrib_imm_V4: 1578 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 : 1579 Hexagon::STrib_imm_cNotPt_V4; 1580 case Hexagon::STrib_indexed_shl_V4: 1581 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 : 1582 Hexagon::STrib_indexed_shl_cNotPt_V4; 1583 // Halfword. 1584 case Hexagon::POST_SThri: 1585 return !invertPredicate ? Hexagon::POST_SThri_cPt : 1586 Hexagon::POST_SThri_cNotPt; 1587 case Hexagon::STrih: 1588 return !invertPredicate ? Hexagon::STrih_cPt : 1589 Hexagon::STrih_cNotPt; 1590 case Hexagon::STrih_indexed: 1591 return !invertPredicate ? Hexagon::STrih_indexed_cPt : 1592 Hexagon::STrih_indexed_cNotPt; 1593 case Hexagon::STrih_imm_V4: 1594 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 : 1595 Hexagon::STrih_imm_cNotPt_V4; 1596 case Hexagon::STrih_indexed_shl_V4: 1597 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 : 1598 Hexagon::STrih_indexed_shl_cNotPt_V4; 1599 // Word. 1600 case Hexagon::POST_STwri: 1601 return !invertPredicate ? Hexagon::POST_STwri_cPt : 1602 Hexagon::POST_STwri_cNotPt; 1603 case Hexagon::STriw: 1604 return !invertPredicate ? Hexagon::STriw_cPt : 1605 Hexagon::STriw_cNotPt; 1606 case Hexagon::STriw_indexed: 1607 return !invertPredicate ? Hexagon::STriw_indexed_cPt : 1608 Hexagon::STriw_indexed_cNotPt; 1609 case Hexagon::STriw_indexed_shl_V4: 1610 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 : 1611 Hexagon::STriw_indexed_shl_cNotPt_V4; 1612 case Hexagon::STriw_imm_V4: 1613 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 : 1614 Hexagon::STriw_imm_cNotPt_V4; 1615 // Double word. 1616 case Hexagon::POST_STdri: 1617 return !invertPredicate ? Hexagon::POST_STdri_cPt : 1618 Hexagon::POST_STdri_cNotPt; 1619 case Hexagon::STrid: 1620 return !invertPredicate ? Hexagon::STrid_cPt : 1621 Hexagon::STrid_cNotPt; 1622 case Hexagon::STrid_indexed: 1623 return !invertPredicate ? Hexagon::STrid_indexed_cPt : 1624 Hexagon::STrid_indexed_cNotPt; 1625 case Hexagon::STrid_indexed_shl_V4: 1626 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 : 1627 Hexagon::STrid_indexed_shl_cNotPt_V4; 1628 1629 // V4 Store to global address 1630 case Hexagon::STd_GP_V4: 1631 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 : 1632 Hexagon::STd_GP_cNotPt_V4; 1633 case Hexagon::STb_GP_V4: 1634 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 : 1635 Hexagon::STb_GP_cNotPt_V4; 1636 case Hexagon::STh_GP_V4: 1637 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 : 1638 Hexagon::STh_GP_cNotPt_V4; 1639 case Hexagon::STw_GP_V4: 1640 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 : 1641 Hexagon::STw_GP_cNotPt_V4; 1642 1643 // Load. 1644 case Hexagon::LDrid: 1645 return !invertPredicate ? Hexagon::LDrid_cPt : 1646 Hexagon::LDrid_cNotPt; 1647 case Hexagon::LDriw: 1648 return !invertPredicate ? Hexagon::LDriw_cPt : 1649 Hexagon::LDriw_cNotPt; 1650 case Hexagon::LDrih: 1651 return !invertPredicate ? Hexagon::LDrih_cPt : 1652 Hexagon::LDrih_cNotPt; 1653 case Hexagon::LDriuh: 1654 return !invertPredicate ? Hexagon::LDriuh_cPt : 1655 Hexagon::LDriuh_cNotPt; 1656 case Hexagon::LDrib: 1657 return !invertPredicate ? Hexagon::LDrib_cPt : 1658 Hexagon::LDrib_cNotPt; 1659 case Hexagon::LDriub: 1660 return !invertPredicate ? Hexagon::LDriub_cPt : 1661 Hexagon::LDriub_cNotPt; 1662 // Load Indexed. 1663 case Hexagon::LDrid_indexed: 1664 return !invertPredicate ? Hexagon::LDrid_indexed_cPt : 1665 Hexagon::LDrid_indexed_cNotPt; 1666 case Hexagon::LDriw_indexed: 1667 return !invertPredicate ? Hexagon::LDriw_indexed_cPt : 1668 Hexagon::LDriw_indexed_cNotPt; 1669 case Hexagon::LDrih_indexed: 1670 return !invertPredicate ? Hexagon::LDrih_indexed_cPt : 1671 Hexagon::LDrih_indexed_cNotPt; 1672 case Hexagon::LDriuh_indexed: 1673 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt : 1674 Hexagon::LDriuh_indexed_cNotPt; 1675 case Hexagon::LDrib_indexed: 1676 return !invertPredicate ? Hexagon::LDrib_indexed_cPt : 1677 Hexagon::LDrib_indexed_cNotPt; 1678 case Hexagon::LDriub_indexed: 1679 return !invertPredicate ? Hexagon::LDriub_indexed_cPt : 1680 Hexagon::LDriub_indexed_cNotPt; 1681 // Post Increment Load. 1682 case Hexagon::POST_LDrid: 1683 return !invertPredicate ? Hexagon::POST_LDrid_cPt : 1684 Hexagon::POST_LDrid_cNotPt; 1685 case Hexagon::POST_LDriw: 1686 return !invertPredicate ? Hexagon::POST_LDriw_cPt : 1687 Hexagon::POST_LDriw_cNotPt; 1688 case Hexagon::POST_LDrih: 1689 return !invertPredicate ? Hexagon::POST_LDrih_cPt : 1690 Hexagon::POST_LDrih_cNotPt; 1691 case Hexagon::POST_LDriuh: 1692 return !invertPredicate ? Hexagon::POST_LDriuh_cPt : 1693 Hexagon::POST_LDriuh_cNotPt; 1694 case Hexagon::POST_LDrib: 1695 return !invertPredicate ? Hexagon::POST_LDrib_cPt : 1696 Hexagon::POST_LDrib_cNotPt; 1697 case Hexagon::POST_LDriub: 1698 return !invertPredicate ? Hexagon::POST_LDriub_cPt : 1699 Hexagon::POST_LDriub_cNotPt; 1700 // DEALLOC_RETURN. 1701 case Hexagon::DEALLOC_RET_V4: 1702 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 : 1703 Hexagon::DEALLOC_RET_cNotPt_V4; 1704 } 1705 llvm_unreachable("Unexpected predicable instruction"); 1706} 1707 1708 1709bool HexagonInstrInfo:: 1710PredicateInstruction(MachineInstr *MI, 1711 const SmallVectorImpl<MachineOperand> &Cond) const { 1712 int Opc = MI->getOpcode(); 1713 assert (isPredicable(MI) && "Expected predicable instruction"); 1714 bool invertJump = (!Cond.empty() && Cond[0].isImm() && 1715 (Cond[0].getImm() == 0)); 1716 1717 // This will change MI's opcode to its predicate version. 1718 // However, its operand list is still the old one, i.e. the 1719 // non-predicate one. 1720 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump))); 1721 1722 int oper = -1; 1723 unsigned int GAIdx = 0; 1724 1725 // Indicates whether the current MI has a GlobalAddress operand 1726 bool hasGAOpnd = false; 1727 std::vector<MachineOperand> tmpOpnds; 1728 1729 // Indicates whether we need to shift operands to right. 1730 bool needShift = true; 1731 1732 // The predicate is ALWAYS the FIRST input operand !!! 1733 if (MI->getNumOperands() == 0) { 1734 // The non-predicate version of MI does not take any operands, 1735 // i.e. no outs and no ins. In this condition, the predicate 1736 // operand will be directly placed at Operands[0]. No operand 1737 // shift is needed. 1738 // Example: BARRIER 1739 needShift = false; 1740 oper = -1; 1741 } 1742 else if ( MI->getOperand(MI->getNumOperands()-1).isReg() 1743 && MI->getOperand(MI->getNumOperands()-1).isDef() 1744 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) { 1745 // The non-predicate version of MI does not have any input operands. 1746 // In this condition, we extend the length of Operands[] by one and 1747 // copy the original last operand to the newly allocated slot. 1748 // At this moment, it is just a place holder. Later, we will put 1749 // predicate operand directly into it. No operand shift is needed. 1750 // Example: r0=BARRIER (this is a faked insn used here for illustration) 1751 MI->addOperand(MI->getOperand(MI->getNumOperands()-1)); 1752 needShift = false; 1753 oper = MI->getNumOperands() - 2; 1754 } 1755 else { 1756 // We need to right shift all input operands by one. Duplicate the 1757 // last operand into the newly allocated slot. 1758 MI->addOperand(MI->getOperand(MI->getNumOperands()-1)); 1759 } 1760 1761 if (needShift) 1762 { 1763 // Operands[ MI->getNumOperands() - 2 ] has been copied into 1764 // Operands[ MI->getNumOperands() - 1 ], so we start from 1765 // Operands[ MI->getNumOperands() - 3 ]. 1766 // oper is a signed int. 1767 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1. 1768 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) 1769 { 1770 MachineOperand &MO = MI->getOperand(oper); 1771 1772 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7] 1773 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1> 1774 // /\~ 1775 // /||\~ 1776 // || 1777 // Predicate Operand here 1778 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) { 1779 break; 1780 } 1781 if (MO.isReg()) { 1782 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(), 1783 MO.isImplicit(), MO.isKill(), 1784 MO.isDead(), MO.isUndef(), 1785 MO.isDebug()); 1786 } 1787 else if (MO.isImm()) { 1788 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm()); 1789 } 1790 else if (MO.isGlobal()) { 1791 // MI can not have more than one GlobalAddress operand. 1792 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd"); 1793 1794 // There is no member function called "ChangeToGlobalAddress" in the 1795 // MachineOperand class (not like "ChangeToRegister" and 1796 // "ChangeToImmediate"). So we have to remove them from Operands[] list 1797 // first, and then add them back after we have inserted the predicate 1798 // operand. tmpOpnds[] is to remember these operands before we remove 1799 // them. 1800 tmpOpnds.push_back(MO); 1801 1802 // Operands[oper] is a GlobalAddress operand; 1803 // Operands[oper+1] has been copied into Operands[oper+2]; 1804 hasGAOpnd = true; 1805 GAIdx = oper; 1806 continue; 1807 } 1808 else { 1809 assert(false && "Unexpected operand type"); 1810 } 1811 } 1812 } 1813 1814 int regPos = invertJump ? 1 : 0; 1815 MachineOperand PredMO = Cond[regPos]; 1816 1817 // [oper] now points to the last explicit Def. Predicate operand must be 1818 // located at [oper+1]. See diagram above. 1819 // This assumes that the predicate is always the first operand, 1820 // i.e. Operands[0+numResults], in the set of inputs 1821 // It is better to have an assert here to check this. But I don't know how 1822 // to write this assert because findFirstPredOperandIdx() would return -1 1823 if (oper < -1) oper = -1; 1824 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(), 1825 PredMO.isImplicit(), PredMO.isKill(), 1826 PredMO.isDead(), PredMO.isUndef(), 1827 PredMO.isDebug()); 1828 1829 if (hasGAOpnd) 1830 { 1831 unsigned int i; 1832 1833 // Operands[GAIdx] is the original GlobalAddress operand, which is 1834 // already copied into tmpOpnds[0]. 1835 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1] 1836 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2], 1837 // so we start from [GAIdx+2] 1838 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i) 1839 tmpOpnds.push_back(MI->getOperand(i)); 1840 1841 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ] 1842 // It is very important that we always remove from the end of Operands[] 1843 // MI->getNumOperands() is at least 2 if program goes to here. 1844 for (i = MI->getNumOperands() - 1; i > GAIdx; --i) 1845 MI->RemoveOperand(i); 1846 1847 for (i = 0; i < tmpOpnds.size(); ++i) 1848 MI->addOperand(tmpOpnds[i]); 1849 } 1850 1851 return true; 1852} 1853 1854 1855bool 1856HexagonInstrInfo:: 1857isProfitableToIfCvt(MachineBasicBlock &MBB, 1858 unsigned NumCycles, 1859 unsigned ExtraPredCycles, 1860 const BranchProbability &Probability) const { 1861 return true; 1862} 1863 1864 1865bool 1866HexagonInstrInfo:: 1867isProfitableToIfCvt(MachineBasicBlock &TMBB, 1868 unsigned NumTCycles, 1869 unsigned ExtraTCycles, 1870 MachineBasicBlock &FMBB, 1871 unsigned NumFCycles, 1872 unsigned ExtraFCycles, 1873 const BranchProbability &Probability) const { 1874 return true; 1875} 1876 1877 1878bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { 1879 const uint64_t F = MI->getDesc().TSFlags; 1880 1881 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask); 1882} 1883 1884bool 1885HexagonInstrInfo::DefinesPredicate(MachineInstr *MI, 1886 std::vector<MachineOperand> &Pred) const { 1887 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) { 1888 MachineOperand MO = MI->getOperand(oper); 1889 if (MO.isReg() && MO.isDef()) { 1890 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg()); 1891 if (RC == &Hexagon::PredRegsRegClass) { 1892 Pred.push_back(MO); 1893 return true; 1894 } 1895 } 1896 } 1897 return false; 1898} 1899 1900 1901bool 1902HexagonInstrInfo:: 1903SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 1904 const SmallVectorImpl<MachineOperand> &Pred2) const { 1905 // TODO: Fix this 1906 return false; 1907} 1908 1909 1910// 1911// We indicate that we want to reverse the branch by 1912// inserting a 0 at the beginning of the Cond vector. 1913// 1914bool HexagonInstrInfo:: 1915ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 1916 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 1917 Cond.erase(Cond.begin()); 1918 } else { 1919 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0)); 1920 } 1921 return false; 1922} 1923 1924 1925bool HexagonInstrInfo:: 1926isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs, 1927 const BranchProbability &Probability) const { 1928 return (NumInstrs <= 4); 1929} 1930 1931bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { 1932 switch (MI->getOpcode()) { 1933 default: return false; 1934 case Hexagon::DEALLOC_RET_V4 : 1935 case Hexagon::DEALLOC_RET_cPt_V4 : 1936 case Hexagon::DEALLOC_RET_cNotPt_V4 : 1937 case Hexagon::DEALLOC_RET_cdnPnt_V4 : 1938 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 : 1939 case Hexagon::DEALLOC_RET_cdnPt_V4 : 1940 case Hexagon::DEALLOC_RET_cNotdnPt_V4 : 1941 return true; 1942 } 1943} 1944 1945 1946bool HexagonInstrInfo:: 1947isValidOffset(const int Opcode, const int Offset) const { 1948 // This function is to check whether the "Offset" is in the correct range of 1949 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is 1950 // inserted to calculate the final address. Due to this reason, the function 1951 // assumes that the "Offset" has correct alignment. 1952 // We used to assert if the offset was not properly aligned, however, 1953 // there are cases where a misaligned pointer recast can cause this 1954 // problem, and we need to allow for it. The front end warns of such 1955 // misaligns with respect to load size. 1956 1957 switch(Opcode) { 1958 1959 case Hexagon::LDriw: 1960 case Hexagon::LDriw_indexed: 1961 case Hexagon::LDriw_f: 1962 case Hexagon::STriw_indexed: 1963 case Hexagon::STriw: 1964 case Hexagon::STriw_f: 1965 return (Offset >= Hexagon_MEMW_OFFSET_MIN) && 1966 (Offset <= Hexagon_MEMW_OFFSET_MAX); 1967 1968 case Hexagon::LDrid: 1969 case Hexagon::LDrid_indexed: 1970 case Hexagon::LDrid_f: 1971 case Hexagon::STrid: 1972 case Hexagon::STrid_indexed: 1973 case Hexagon::STrid_f: 1974 return (Offset >= Hexagon_MEMD_OFFSET_MIN) && 1975 (Offset <= Hexagon_MEMD_OFFSET_MAX); 1976 1977 case Hexagon::LDrih: 1978 case Hexagon::LDriuh: 1979 case Hexagon::STrih: 1980 return (Offset >= Hexagon_MEMH_OFFSET_MIN) && 1981 (Offset <= Hexagon_MEMH_OFFSET_MAX); 1982 1983 case Hexagon::LDrib: 1984 case Hexagon::STrib: 1985 case Hexagon::LDriub: 1986 return (Offset >= Hexagon_MEMB_OFFSET_MIN) && 1987 (Offset <= Hexagon_MEMB_OFFSET_MAX); 1988 1989 case Hexagon::ADD_ri: 1990 case Hexagon::TFR_FI: 1991 return (Offset >= Hexagon_ADDI_OFFSET_MIN) && 1992 (Offset <= Hexagon_ADDI_OFFSET_MAX); 1993 1994 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 1995 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 1996 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 1997 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 1998 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 1999 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2000 case Hexagon::MEMw_ADDi_MEM_V4 : 2001 case Hexagon::MEMw_SUBi_MEM_V4 : 2002 case Hexagon::MEMw_ADDr_MEM_V4 : 2003 case Hexagon::MEMw_SUBr_MEM_V4 : 2004 case Hexagon::MEMw_ANDr_MEM_V4 : 2005 case Hexagon::MEMw_ORr_MEM_V4 : 2006 return (0 <= Offset && Offset <= 255); 2007 2008 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2009 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2010 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2011 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2012 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2013 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2014 case Hexagon::MEMh_ADDi_MEM_V4 : 2015 case Hexagon::MEMh_SUBi_MEM_V4 : 2016 case Hexagon::MEMh_ADDr_MEM_V4 : 2017 case Hexagon::MEMh_SUBr_MEM_V4 : 2018 case Hexagon::MEMh_ANDr_MEM_V4 : 2019 case Hexagon::MEMh_ORr_MEM_V4 : 2020 return (0 <= Offset && Offset <= 127); 2021 2022 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2023 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2024 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2025 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2026 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2027 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2028 case Hexagon::MEMb_ADDi_MEM_V4 : 2029 case Hexagon::MEMb_SUBi_MEM_V4 : 2030 case Hexagon::MEMb_ADDr_MEM_V4 : 2031 case Hexagon::MEMb_SUBr_MEM_V4 : 2032 case Hexagon::MEMb_ANDr_MEM_V4 : 2033 case Hexagon::MEMb_ORr_MEM_V4 : 2034 return (0 <= Offset && Offset <= 63); 2035 2036 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of 2037 // any size. Later pass knows how to handle it. 2038 case Hexagon::STriw_pred: 2039 case Hexagon::LDriw_pred: 2040 return true; 2041 2042 case Hexagon::LOOP0_i: 2043 return isUInt<10>(Offset); 2044 2045 // INLINEASM is very special. 2046 case Hexagon::INLINEASM: 2047 return true; 2048 } 2049 2050 llvm_unreachable("No offset range is defined for this opcode. " 2051 "Please define it in the above switch statement!"); 2052} 2053 2054 2055// 2056// Check if the Offset is a valid auto-inc imm by Load/Store Type. 2057// 2058bool HexagonInstrInfo:: 2059isValidAutoIncImm(const EVT VT, const int Offset) const { 2060 2061 if (VT == MVT::i64) { 2062 return (Offset >= Hexagon_MEMD_AUTOINC_MIN && 2063 Offset <= Hexagon_MEMD_AUTOINC_MAX && 2064 (Offset & 0x7) == 0); 2065 } 2066 if (VT == MVT::i32) { 2067 return (Offset >= Hexagon_MEMW_AUTOINC_MIN && 2068 Offset <= Hexagon_MEMW_AUTOINC_MAX && 2069 (Offset & 0x3) == 0); 2070 } 2071 if (VT == MVT::i16) { 2072 return (Offset >= Hexagon_MEMH_AUTOINC_MIN && 2073 Offset <= Hexagon_MEMH_AUTOINC_MAX && 2074 (Offset & 0x1) == 0); 2075 } 2076 if (VT == MVT::i8) { 2077 return (Offset >= Hexagon_MEMB_AUTOINC_MIN && 2078 Offset <= Hexagon_MEMB_AUTOINC_MAX); 2079 } 2080 llvm_unreachable("Not an auto-inc opc!"); 2081} 2082 2083 2084bool HexagonInstrInfo:: 2085isMemOp(const MachineInstr *MI) const { 2086 switch (MI->getOpcode()) 2087 { 2088 default: return false; 2089 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2090 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2091 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2092 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2093 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2094 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2095 case Hexagon::MEMw_ADDi_MEM_V4 : 2096 case Hexagon::MEMw_SUBi_MEM_V4 : 2097 case Hexagon::MEMw_ADDr_MEM_V4 : 2098 case Hexagon::MEMw_SUBr_MEM_V4 : 2099 case Hexagon::MEMw_ANDr_MEM_V4 : 2100 case Hexagon::MEMw_ORr_MEM_V4 : 2101 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2102 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2103 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2104 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2105 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2106 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2107 case Hexagon::MEMh_ADDi_MEM_V4 : 2108 case Hexagon::MEMh_SUBi_MEM_V4 : 2109 case Hexagon::MEMh_ADDr_MEM_V4 : 2110 case Hexagon::MEMh_SUBr_MEM_V4 : 2111 case Hexagon::MEMh_ANDr_MEM_V4 : 2112 case Hexagon::MEMh_ORr_MEM_V4 : 2113 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2114 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2115 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2116 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2117 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2118 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2119 case Hexagon::MEMb_ADDi_MEM_V4 : 2120 case Hexagon::MEMb_SUBi_MEM_V4 : 2121 case Hexagon::MEMb_ADDr_MEM_V4 : 2122 case Hexagon::MEMb_SUBr_MEM_V4 : 2123 case Hexagon::MEMb_ANDr_MEM_V4 : 2124 case Hexagon::MEMb_ORr_MEM_V4 : 2125 return true; 2126 } 2127} 2128 2129 2130bool HexagonInstrInfo:: 2131isSpillPredRegOp(const MachineInstr *MI) const { 2132 switch (MI->getOpcode()) { 2133 default: return false; 2134 case Hexagon::STriw_pred : 2135 case Hexagon::LDriw_pred : 2136 return true; 2137 } 2138} 2139 2140bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const { 2141 switch (MI->getOpcode()) { 2142 default: return false; 2143 case Hexagon::CMPEQrr: 2144 case Hexagon::CMPEQri: 2145 case Hexagon::CMPLTrr: 2146 case Hexagon::CMPGTrr: 2147 case Hexagon::CMPGTri: 2148 case Hexagon::CMPLTUrr: 2149 case Hexagon::CMPGTUrr: 2150 case Hexagon::CMPGTUri: 2151 case Hexagon::CMPGEri: 2152 case Hexagon::CMPGEUri: 2153 return true; 2154 } 2155} 2156 2157bool HexagonInstrInfo:: 2158isConditionalTransfer (const MachineInstr *MI) const { 2159 switch (MI->getOpcode()) { 2160 default: return false; 2161 case Hexagon::TFR_cPt: 2162 case Hexagon::TFR_cNotPt: 2163 case Hexagon::TFRI_cPt: 2164 case Hexagon::TFRI_cNotPt: 2165 case Hexagon::TFR_cdnPt: 2166 case Hexagon::TFR_cdnNotPt: 2167 case Hexagon::TFRI_cdnPt: 2168 case Hexagon::TFRI_cdnNotPt: 2169 return true; 2170 } 2171} 2172 2173bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { 2174 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2175 switch (MI->getOpcode()) 2176 { 2177 default: return false; 2178 case Hexagon::ADD_ri_cPt: 2179 case Hexagon::ADD_ri_cNotPt: 2180 case Hexagon::ADD_rr_cPt: 2181 case Hexagon::ADD_rr_cNotPt: 2182 case Hexagon::XOR_rr_cPt: 2183 case Hexagon::XOR_rr_cNotPt: 2184 case Hexagon::AND_rr_cPt: 2185 case Hexagon::AND_rr_cNotPt: 2186 case Hexagon::OR_rr_cPt: 2187 case Hexagon::OR_rr_cNotPt: 2188 case Hexagon::SUB_rr_cPt: 2189 case Hexagon::SUB_rr_cNotPt: 2190 case Hexagon::COMBINE_rr_cPt: 2191 case Hexagon::COMBINE_rr_cNotPt: 2192 return true; 2193 case Hexagon::ASLH_cPt_V4: 2194 case Hexagon::ASLH_cNotPt_V4: 2195 case Hexagon::ASRH_cPt_V4: 2196 case Hexagon::ASRH_cNotPt_V4: 2197 case Hexagon::SXTB_cPt_V4: 2198 case Hexagon::SXTB_cNotPt_V4: 2199 case Hexagon::SXTH_cPt_V4: 2200 case Hexagon::SXTH_cNotPt_V4: 2201 case Hexagon::ZXTB_cPt_V4: 2202 case Hexagon::ZXTB_cNotPt_V4: 2203 case Hexagon::ZXTH_cPt_V4: 2204 case Hexagon::ZXTH_cNotPt_V4: 2205 return QRI.Subtarget.hasV4TOps(); 2206 } 2207} 2208 2209bool HexagonInstrInfo:: 2210isConditionalLoad (const MachineInstr* MI) const { 2211 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2212 switch (MI->getOpcode()) 2213 { 2214 default: return false; 2215 case Hexagon::LDrid_cPt : 2216 case Hexagon::LDrid_cNotPt : 2217 case Hexagon::LDrid_indexed_cPt : 2218 case Hexagon::LDrid_indexed_cNotPt : 2219 case Hexagon::LDriw_cPt : 2220 case Hexagon::LDriw_cNotPt : 2221 case Hexagon::LDriw_indexed_cPt : 2222 case Hexagon::LDriw_indexed_cNotPt : 2223 case Hexagon::LDrih_cPt : 2224 case Hexagon::LDrih_cNotPt : 2225 case Hexagon::LDrih_indexed_cPt : 2226 case Hexagon::LDrih_indexed_cNotPt : 2227 case Hexagon::LDrib_cPt : 2228 case Hexagon::LDrib_cNotPt : 2229 case Hexagon::LDrib_indexed_cPt : 2230 case Hexagon::LDrib_indexed_cNotPt : 2231 case Hexagon::LDriuh_cPt : 2232 case Hexagon::LDriuh_cNotPt : 2233 case Hexagon::LDriuh_indexed_cPt : 2234 case Hexagon::LDriuh_indexed_cNotPt : 2235 case Hexagon::LDriub_cPt : 2236 case Hexagon::LDriub_cNotPt : 2237 case Hexagon::LDriub_indexed_cPt : 2238 case Hexagon::LDriub_indexed_cNotPt : 2239 return true; 2240 case Hexagon::POST_LDrid_cPt : 2241 case Hexagon::POST_LDrid_cNotPt : 2242 case Hexagon::POST_LDriw_cPt : 2243 case Hexagon::POST_LDriw_cNotPt : 2244 case Hexagon::POST_LDrih_cPt : 2245 case Hexagon::POST_LDrih_cNotPt : 2246 case Hexagon::POST_LDrib_cPt : 2247 case Hexagon::POST_LDrib_cNotPt : 2248 case Hexagon::POST_LDriuh_cPt : 2249 case Hexagon::POST_LDriuh_cNotPt : 2250 case Hexagon::POST_LDriub_cPt : 2251 case Hexagon::POST_LDriub_cNotPt : 2252 return QRI.Subtarget.hasV4TOps(); 2253 case Hexagon::LDrid_indexed_shl_cPt_V4 : 2254 case Hexagon::LDrid_indexed_shl_cNotPt_V4 : 2255 case Hexagon::LDrib_indexed_shl_cPt_V4 : 2256 case Hexagon::LDrib_indexed_shl_cNotPt_V4 : 2257 case Hexagon::LDriub_indexed_shl_cPt_V4 : 2258 case Hexagon::LDriub_indexed_shl_cNotPt_V4 : 2259 case Hexagon::LDrih_indexed_shl_cPt_V4 : 2260 case Hexagon::LDrih_indexed_shl_cNotPt_V4 : 2261 case Hexagon::LDriuh_indexed_shl_cPt_V4 : 2262 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 : 2263 case Hexagon::LDriw_indexed_shl_cPt_V4 : 2264 case Hexagon::LDriw_indexed_shl_cNotPt_V4 : 2265 return QRI.Subtarget.hasV4TOps(); 2266 } 2267} 2268 2269// Returns true if an instruction is a conditional store. 2270// 2271// Note: It doesn't include conditional new-value stores as they can't be 2272// converted to .new predicate. 2273// 2274// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ] 2275// ^ ^ 2276// / \ (not OK. it will cause new-value store to be 2277// / X conditional on p0.new while R2 producer is 2278// / \ on p0) 2279// / \. 2280// p.new store p.old NV store 2281// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new] 2282// ^ ^ 2283// \ / 2284// \ / 2285// \ / 2286// p.old store 2287// [if (p0)memw(R0+#0)=R2] 2288// 2289// The above diagram shows the steps involoved in the conversion of a predicated 2290// store instruction to its .new predicated new-value form. 2291// 2292// The following set of instructions further explains the scenario where 2293// conditional new-value store becomes invalid when promoted to .new predicate 2294// form. 2295// 2296// { 1) if (p0) r0 = add(r1, r2) 2297// 2) p0 = cmp.eq(r3, #0) } 2298// 2299// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with 2300// the first two instructions because in instr 1, r0 is conditional on old value 2301// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which 2302// is not valid for new-value stores. 2303bool HexagonInstrInfo:: 2304isConditionalStore (const MachineInstr* MI) const { 2305 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2306 switch (MI->getOpcode()) 2307 { 2308 default: return false; 2309 case Hexagon::STrib_imm_cPt_V4 : 2310 case Hexagon::STrib_imm_cNotPt_V4 : 2311 case Hexagon::STrib_indexed_shl_cPt_V4 : 2312 case Hexagon::STrib_indexed_shl_cNotPt_V4 : 2313 case Hexagon::STrib_cPt : 2314 case Hexagon::STrib_cNotPt : 2315 case Hexagon::POST_STbri_cPt : 2316 case Hexagon::POST_STbri_cNotPt : 2317 case Hexagon::STrid_indexed_cPt : 2318 case Hexagon::STrid_indexed_cNotPt : 2319 case Hexagon::STrid_indexed_shl_cPt_V4 : 2320 case Hexagon::POST_STdri_cPt : 2321 case Hexagon::POST_STdri_cNotPt : 2322 case Hexagon::STrih_cPt : 2323 case Hexagon::STrih_cNotPt : 2324 case Hexagon::STrih_indexed_cPt : 2325 case Hexagon::STrih_indexed_cNotPt : 2326 case Hexagon::STrih_imm_cPt_V4 : 2327 case Hexagon::STrih_imm_cNotPt_V4 : 2328 case Hexagon::STrih_indexed_shl_cPt_V4 : 2329 case Hexagon::STrih_indexed_shl_cNotPt_V4 : 2330 case Hexagon::POST_SThri_cPt : 2331 case Hexagon::POST_SThri_cNotPt : 2332 case Hexagon::STriw_cPt : 2333 case Hexagon::STriw_cNotPt : 2334 case Hexagon::STriw_indexed_cPt : 2335 case Hexagon::STriw_indexed_cNotPt : 2336 case Hexagon::STriw_imm_cPt_V4 : 2337 case Hexagon::STriw_imm_cNotPt_V4 : 2338 case Hexagon::STriw_indexed_shl_cPt_V4 : 2339 case Hexagon::STriw_indexed_shl_cNotPt_V4 : 2340 case Hexagon::POST_STwri_cPt : 2341 case Hexagon::POST_STwri_cNotPt : 2342 return QRI.Subtarget.hasV4TOps(); 2343 2344 // V4 global address store before promoting to dot new. 2345 case Hexagon::STd_GP_cPt_V4 : 2346 case Hexagon::STd_GP_cNotPt_V4 : 2347 case Hexagon::STb_GP_cPt_V4 : 2348 case Hexagon::STb_GP_cNotPt_V4 : 2349 case Hexagon::STh_GP_cPt_V4 : 2350 case Hexagon::STh_GP_cNotPt_V4 : 2351 case Hexagon::STw_GP_cPt_V4 : 2352 case Hexagon::STw_GP_cNotPt_V4 : 2353 return QRI.Subtarget.hasV4TOps(); 2354 2355 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded 2356 // from the "Conditional Store" list. Because a predicated new value store 2357 // would NOT be promoted to a double dot new store. See diagram below: 2358 // This function returns yes for those stores that are predicated but not 2359 // yet promoted to predicate dot new instructions. 2360 // 2361 // +---------------------+ 2362 // /-----| if (p0) memw(..)=r0 |---------\~ 2363 // || +---------------------+ || 2364 // promote || /\ /\ || promote 2365 // || /||\ /||\ || 2366 // \||/ demote || \||/ 2367 // \/ || || \/ 2368 // +-------------------------+ || +-------------------------+ 2369 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new | 2370 // +-------------------------+ || +-------------------------+ 2371 // || || || 2372 // || demote \||/ 2373 // promote || \/ NOT possible 2374 // || || /\~ 2375 // \||/ || /||\~ 2376 // \/ || || 2377 // +-----------------------------+ 2378 // | if (p0.new) memw(..)=r0.new | 2379 // +-----------------------------+ 2380 // Double Dot New Store 2381 // 2382 } 2383} 2384 2385unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const { 2386 const uint64_t F = MI->getDesc().TSFlags; 2387 2388 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask); 2389} 2390 2391/// immediateExtend - Changes the instruction in place to one using an immediate 2392/// extender. 2393void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const { 2394 assert((isExtendable(MI)||isConstExtended(MI)) && 2395 "Instruction must be extendable"); 2396 // Find which operand is extendable. 2397 short ExtOpNum = getCExtOpNum(MI); 2398 MachineOperand &MO = MI->getOperand(ExtOpNum); 2399 // This needs to be something we understand. 2400 assert((MO.isMBB() || MO.isImm()) && 2401 "Branch with unknown extendable field type"); 2402 // Mark given operand as extended. 2403 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended); 2404} 2405 2406DFAPacketizer *HexagonInstrInfo:: 2407CreateTargetScheduleState(const TargetMachine *TM, 2408 const ScheduleDAG *DAG) const { 2409 const InstrItineraryData *II = TM->getInstrItineraryData(); 2410 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II); 2411} 2412 2413bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 2414 const MachineBasicBlock *MBB, 2415 const MachineFunction &MF) const { 2416 // Debug info is never a scheduling boundary. It's necessary to be explicit 2417 // due to the special treatment of IT instructions below, otherwise a 2418 // dbg_value followed by an IT will result in the IT instruction being 2419 // considered a scheduling hazard, which is wrong. It should be the actual 2420 // instruction preceding the dbg_value instruction(s), just like it is 2421 // when debug info is not present. 2422 if (MI->isDebugValue()) 2423 return false; 2424 2425 // Terminators and labels can't be scheduled around. 2426 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm()) 2427 return true; 2428 2429 return false; 2430} 2431 2432bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const { 2433 2434 // Constant extenders are allowed only for V4 and above. 2435 if (!Subtarget.hasV4TOps()) 2436 return false; 2437 2438 const uint64_t F = MI->getDesc().TSFlags; 2439 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask; 2440 if (isExtended) // Instruction must be extended. 2441 return true; 2442 2443 unsigned isExtendable = (F >> HexagonII::ExtendablePos) 2444 & HexagonII::ExtendableMask; 2445 if (!isExtendable) 2446 return false; 2447 2448 short ExtOpNum = getCExtOpNum(MI); 2449 const MachineOperand &MO = MI->getOperand(ExtOpNum); 2450 // Use MO operand flags to determine if MO 2451 // has the HMOTF_ConstExtended flag set. 2452 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended) 2453 return true; 2454 // If this is a Machine BB address we are talking about, and it is 2455 // not marked as extended, say so. 2456 if (MO.isMBB()) 2457 return false; 2458 2459 // We could be using an instruction with an extendable immediate and shoehorn 2460 // a global address into it. If it is a global address it will be constant 2461 // extended. We do this for COMBINE. 2462 // We currently only handle isGlobal() because it is the only kind of 2463 // object we are going to end up with here for now. 2464 // In the future we probably should add isSymbol(), etc. 2465 if (MO.isGlobal() || MO.isSymbol()) 2466 return true; 2467 2468 // If the extendable operand is not 'Immediate' type, the instruction should 2469 // have 'isExtended' flag set. 2470 assert(MO.isImm() && "Extendable operand must be Immediate type"); 2471 2472 int MinValue = getMinValue(MI); 2473 int MaxValue = getMaxValue(MI); 2474 int ImmValue = MO.getImm(); 2475 2476 return (ImmValue < MinValue || ImmValue > MaxValue); 2477} 2478 2479// Returns true if a particular operand is extendable for an instruction. 2480bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI, 2481 unsigned short OperandNum) const { 2482 // Constant extenders are allowed only for V4 and above. 2483 if (!Subtarget.hasV4TOps()) 2484 return false; 2485 2486 const uint64_t F = MI->getDesc().TSFlags; 2487 2488 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) 2489 == OperandNum; 2490} 2491 2492// Returns Operand Index for the constant extended instruction. 2493unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const { 2494 const uint64_t F = MI->getDesc().TSFlags; 2495 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask); 2496} 2497 2498// Returns the min value that doesn't need to be extended. 2499int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const { 2500 const uint64_t F = MI->getDesc().TSFlags; 2501 unsigned isSigned = (F >> HexagonII::ExtentSignedPos) 2502 & HexagonII::ExtentSignedMask; 2503 unsigned bits = (F >> HexagonII::ExtentBitsPos) 2504 & HexagonII::ExtentBitsMask; 2505 2506 if (isSigned) // if value is signed 2507 return -1 << (bits - 1); 2508 else 2509 return 0; 2510} 2511 2512// Returns the max value that doesn't need to be extended. 2513int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const { 2514 const uint64_t F = MI->getDesc().TSFlags; 2515 unsigned isSigned = (F >> HexagonII::ExtentSignedPos) 2516 & HexagonII::ExtentSignedMask; 2517 unsigned bits = (F >> HexagonII::ExtentBitsPos) 2518 & HexagonII::ExtentBitsMask; 2519 2520 if (isSigned) // if value is signed 2521 return ~(-1 << (bits - 1)); 2522 else 2523 return ~(-1 << bits); 2524} 2525 2526// Returns true if an instruction can be converted into a non-extended 2527// equivalent instruction. 2528bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const { 2529 2530 short NonExtOpcode; 2531 // Check if the instruction has a register form that uses register in place 2532 // of the extended operand, if so return that as the non-extended form. 2533 if (Hexagon::getRegForm(MI->getOpcode()) >= 0) 2534 return true; 2535 2536 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) { 2537 // Check addressing mode and retreive non-ext equivalent instruction. 2538 2539 switch (getAddrMode(MI)) { 2540 case HexagonII::Absolute : 2541 // Load/store with absolute addressing mode can be converted into 2542 // base+offset mode. 2543 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode()); 2544 break; 2545 case HexagonII::BaseImmOffset : 2546 // Load/store with base+offset addressing mode can be converted into 2547 // base+register offset addressing mode. However left shift operand should 2548 // be set to 0. 2549 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode()); 2550 break; 2551 default: 2552 return false; 2553 } 2554 if (NonExtOpcode < 0) 2555 return false; 2556 return true; 2557 } 2558 return false; 2559} 2560 2561// Returns opcode of the non-extended equivalent instruction. 2562short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const { 2563 2564 // Check if the instruction has a register form that uses register in place 2565 // of the extended operand, if so return that as the non-extended form. 2566 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode()); 2567 if (NonExtOpcode >= 0) 2568 return NonExtOpcode; 2569 2570 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) { 2571 // Check addressing mode and retreive non-ext equivalent instruction. 2572 switch (getAddrMode(MI)) { 2573 case HexagonII::Absolute : 2574 return Hexagon::getBasedWithImmOffset(MI->getOpcode()); 2575 case HexagonII::BaseImmOffset : 2576 return Hexagon::getBaseWithRegOffset(MI->getOpcode()); 2577 default: 2578 return -1; 2579 } 2580 } 2581 return -1; 2582} 2583