HexagonInstrInfo.cpp revision 7517bbc91ae1c60d3c7df8b11642c7a5bb3d5a71 
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonInstrInfo.h"
15#include "HexagonRegisterInfo.h"
16#include "HexagonSubtarget.h"
17#include "Hexagon.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/MathExtras.h"
27#define GET_INSTRINFO_CTOR
28#include "HexagonGenInstrInfo.inc"
29#include "HexagonGenDFAPacketizer.inc"
30
31using namespace llvm;
32
33///
34/// Constants for Hexagon instructions.
35///
36const int Hexagon_MEMW_OFFSET_MAX = 4095;
37const int Hexagon_MEMW_OFFSET_MIN = -4096;
38const int Hexagon_MEMD_OFFSET_MAX = 8191;
39const int Hexagon_MEMD_OFFSET_MIN = -8192;
40const int Hexagon_MEMH_OFFSET_MAX = 2047;
41const int Hexagon_MEMH_OFFSET_MIN = -2048;
42const int Hexagon_MEMB_OFFSET_MAX = 1023;
43const int Hexagon_MEMB_OFFSET_MIN = -1024;
44const int Hexagon_ADDI_OFFSET_MAX = 32767;
45const int Hexagon_ADDI_OFFSET_MIN = -32768;
46const int Hexagon_MEMD_AUTOINC_MAX = 56;
47const int Hexagon_MEMD_AUTOINC_MIN = -64;
48const int Hexagon_MEMW_AUTOINC_MAX = 28;
49const int Hexagon_MEMW_AUTOINC_MIN = -32;
50const int Hexagon_MEMH_AUTOINC_MAX = 14;
51const int Hexagon_MEMH_AUTOINC_MIN = -16;
52const int Hexagon_MEMB_AUTOINC_MAX = 7;
53const int Hexagon_MEMB_AUTOINC_MIN = -8;
54
55
56HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
57  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
58    RI(ST, *this), Subtarget(ST) {
59}
60
61
62/// isLoadFromStackSlot - If the specified machine instruction is a direct
63/// load from a stack slot, return the virtual or physical register number of
64/// the destination along with the FrameIndex of the loaded stack slot.  If
65/// not, return 0.  This predicate must return 0 if the instruction has
66/// any side effects other than loading from the stack slot.
67unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
68                                             int &FrameIndex) const {
69
70
71  switch (MI->getOpcode()) {
72  default: break;
73  case Hexagon::LDriw:
74  case Hexagon::LDrid:
75  case Hexagon::LDrih:
76  case Hexagon::LDrib:
77  case Hexagon::LDriub:
78    if (MI->getOperand(2).isFI() &&
79        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
80      FrameIndex = MI->getOperand(2).getIndex();
81      return MI->getOperand(0).getReg();
82    }
83    break;
84  }
85  return 0;
86}
87
88
89/// isStoreToStackSlot - If the specified machine instruction is a direct
90/// store to a stack slot, return the virtual or physical register number of
91/// the source reg along with the FrameIndex of the loaded stack slot.  If
92/// not, return 0.  This predicate must return 0 if the instruction has
93/// any side effects other than storing to the stack slot.
94unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
95                                            int &FrameIndex) const {
96  switch (MI->getOpcode()) {
97  default: break;
98  case Hexagon::STriw:
99  case Hexagon::STrid:
100  case Hexagon::STrih:
101  case Hexagon::STrib:
102    if (MI->getOperand(2).isFI() &&
103        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
104      FrameIndex = MI->getOperand(2).getIndex();
105      return MI->getOperand(0).getReg();
106    }
107    break;
108  }
109  return 0;
110}
111
112
113unsigned
114HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
115                             MachineBasicBlock *FBB,
116                             const SmallVectorImpl<MachineOperand> &Cond,
117                             DebugLoc DL) const{
118
119    int BOpc   = Hexagon::JMP;
120    int BccOpc = Hexagon::JMP_c;
121
122    assert(TBB && "InsertBranch must not be told to insert a fallthrough");
123
124    int regPos = 0;
125    // Check if ReverseBranchCondition has asked to reverse this branch
126    // If we want to reverse the branch an odd number of times, we want
127    // JMP_cNot.
128    if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
129      BccOpc = Hexagon::JMP_cNot;
130      regPos = 1;
131    }
132
133    if (FBB == 0) {
134      if (Cond.empty()) {
135        // Due to a bug in TailMerging/CFG Optimization, we need to add a
136        // special case handling of a predicated jump followed by an
137        // unconditional jump. If not, Tail Merging and CFG Optimization go
138        // into an infinite loop.
139        MachineBasicBlock *NewTBB, *NewFBB;
140        SmallVector<MachineOperand, 4> Cond;
141        MachineInstr *Term = MBB.getFirstTerminator();
142        if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
143                                                 false)) {
144          MachineBasicBlock *NextBB =
145            llvm::next(MachineFunction::iterator(&MBB));
146          if (NewTBB == NextBB) {
147            ReverseBranchCondition(Cond);
148            RemoveBranch(MBB);
149            return InsertBranch(MBB, TBB, 0, Cond, DL);
150          }
151        }
152        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
153      } else {
154        BuildMI(&MBB, DL,
155                get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
156      }
157      return 1;
158    }
159
160    BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
161    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
162
163    return 2;
164}
165
166
167bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
168                                     MachineBasicBlock *&TBB,
169                                 MachineBasicBlock *&FBB,
170                                 SmallVectorImpl<MachineOperand> &Cond,
171                                 bool AllowModify) const {
172  FBB = NULL;
173
174  // If the block has no terminators, it just falls into the block after it.
175  MachineBasicBlock::iterator I = MBB.end();
176  if (I == MBB.begin())
177    return false;
178
179  // A basic block may looks like this:
180  //
181  //  [   insn
182  //     EH_LABEL
183  //      insn
184  //      insn
185  //      insn
186  //     EH_LABEL
187  //      insn     ]
188  //
189  // It has two succs but does not have a terminator
190  // Don't know how to handle it.
191  do {
192    --I;
193    if (I->isEHLabel())
194      return true;
195  } while (I != MBB.begin());
196
197  I = MBB.end();
198  --I;
199
200  while (I->isDebugValue()) {
201    if (I == MBB.begin())
202      return false;
203    --I;
204  }
205  if (!isUnpredicatedTerminator(I))
206    return false;
207
208  // Get the last instruction in the block.
209  MachineInstr *LastInst = I;
210
211  // If there is only one terminator instruction, process it.
212  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
213    if (LastInst->getOpcode() == Hexagon::JMP) {
214      TBB = LastInst->getOperand(0).getMBB();
215      return false;
216    }
217    if (LastInst->getOpcode() == Hexagon::JMP_c) {
218      // Block ends with fall-through true condbranch.
219      TBB = LastInst->getOperand(1).getMBB();
220      Cond.push_back(LastInst->getOperand(0));
221      return false;
222    }
223    if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
224      // Block ends with fall-through false condbranch.
225      TBB = LastInst->getOperand(1).getMBB();
226      Cond.push_back(MachineOperand::CreateImm(0));
227      Cond.push_back(LastInst->getOperand(0));
228      return false;
229    }
230    // Otherwise, don't know what this is.
231    return true;
232  }
233
234  // Get the instruction before it if it's a terminator.
235  MachineInstr *SecondLastInst = I;
236
237  // If there are three terminators, we don't know what sort of block this is.
238  if (SecondLastInst && I != MBB.begin() &&
239      isUnpredicatedTerminator(--I))
240    return true;
241
242  // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
243  if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
244      (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
245      LastInst->getOpcode() == Hexagon::JMP) {
246    TBB =  SecondLastInst->getOperand(1).getMBB();
247    Cond.push_back(SecondLastInst->getOperand(0));
248    FBB = LastInst->getOperand(0).getMBB();
249    return false;
250  }
251
252  // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
253  if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
254      LastInst->getOpcode() == Hexagon::JMP) {
255    TBB =  SecondLastInst->getOperand(1).getMBB();
256    Cond.push_back(MachineOperand::CreateImm(0));
257    Cond.push_back(SecondLastInst->getOperand(0));
258    FBB = LastInst->getOperand(0).getMBB();
259    return false;
260  }
261
262  // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
263  // executed, so remove it.
264  if (SecondLastInst->getOpcode() == Hexagon::JMP &&
265      LastInst->getOpcode() == Hexagon::JMP) {
266    TBB = SecondLastInst->getOperand(0).getMBB();
267    I = LastInst;
268    if (AllowModify)
269      I->eraseFromParent();
270    return false;
271  }
272
273  // Otherwise, can't handle this.
274  return true;
275}
276
277
278unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
279  int BOpc   = Hexagon::JMP;
280  int BccOpc = Hexagon::JMP_c;
281  int BccOpcNot = Hexagon::JMP_cNot;
282
283  MachineBasicBlock::iterator I = MBB.end();
284  if (I == MBB.begin()) return 0;
285  --I;
286  if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
287      I->getOpcode() != BccOpcNot)
288    return 0;
289
290  // Remove the branch.
291  I->eraseFromParent();
292
293  I = MBB.end();
294
295  if (I == MBB.begin()) return 1;
296  --I;
297  if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
298    return 1;
299
300  // Remove the branch.
301  I->eraseFromParent();
302  return 2;
303}
304
305
306void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
307                                 MachineBasicBlock::iterator I, DebugLoc DL,
308                                 unsigned DestReg, unsigned SrcReg,
309                                 bool KillSrc) const {
310  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
311    BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
312    return;
313  }
314  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
315    BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
316    return;
317  }
318  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
319    // Map Pd = Ps to Pd = or(Ps, Ps).
320    BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
321            DestReg).addReg(SrcReg).addReg(SrcReg);
322    return;
323  }
324  if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
325    // We can have an overlap between single and double reg: r1:0 = r0.
326    if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
327        // r1:0 = r0
328        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
329                Hexagon::subreg_hireg))).addImm(0);
330    } else {
331        // r1:0 = r1 or no overlap.
332        BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
333                Hexagon::subreg_loreg))).addReg(SrcReg);
334        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
335                Hexagon::subreg_hireg))).addImm(0);
336    }
337    return;
338  }
339  if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
340    BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
341    return;
342  }
343
344  llvm_unreachable("Unimplemented");
345}
346
347
348void HexagonInstrInfo::
349storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
350                    unsigned SrcReg, bool isKill, int FI,
351                    const TargetRegisterClass *RC,
352                    const TargetRegisterInfo *TRI) const {
353
354  DebugLoc DL = MBB.findDebugLoc(I);
355  MachineFunction &MF = *MBB.getParent();
356  MachineFrameInfo &MFI = *MF.getFrameInfo();
357  unsigned Align = MFI.getObjectAlignment(FI);
358
359  MachineMemOperand *MMO =
360      MF.getMachineMemOperand(
361                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
362                      MachineMemOperand::MOStore,
363                      MFI.getObjectSize(FI),
364                      Align);
365
366  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
367    BuildMI(MBB, I, DL, get(Hexagon::STriw))
368          .addFrameIndex(FI).addImm(0)
369          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
370  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
371    BuildMI(MBB, I, DL, get(Hexagon::STrid))
372          .addFrameIndex(FI).addImm(0)
373          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
374  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
375    BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
376          .addFrameIndex(FI).addImm(0)
377          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
378  } else {
379    llvm_unreachable("Unimplemented");
380  }
381}
382
383
384void HexagonInstrInfo::storeRegToAddr(
385                                 MachineFunction &MF, unsigned SrcReg,
386                                 bool isKill,
387                                 SmallVectorImpl<MachineOperand> &Addr,
388                                 const TargetRegisterClass *RC,
389                                 SmallVectorImpl<MachineInstr*> &NewMIs) const
390{
391  llvm_unreachable("Unimplemented");
392}
393
394
395void HexagonInstrInfo::
396loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
397                     unsigned DestReg, int FI,
398                     const TargetRegisterClass *RC,
399                     const TargetRegisterInfo *TRI) const {
400  DebugLoc DL = MBB.findDebugLoc(I);
401  MachineFunction &MF = *MBB.getParent();
402  MachineFrameInfo &MFI = *MF.getFrameInfo();
403  unsigned Align = MFI.getObjectAlignment(FI);
404
405  MachineMemOperand *MMO =
406      MF.getMachineMemOperand(
407                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
408                      MachineMemOperand::MOLoad,
409                      MFI.getObjectSize(FI),
410                      Align);
411  if (RC == &Hexagon::IntRegsRegClass) {
412    BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
413          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
414  } else if (RC == &Hexagon::DoubleRegsRegClass) {
415    BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
416          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
417  } else if (RC == &Hexagon::PredRegsRegClass) {
418    BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
419          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
420  } else {
421    llvm_unreachable("Can't store this register to stack slot");
422  }
423}
424
425
426void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
427                                        SmallVectorImpl<MachineOperand> &Addr,
428                                        const TargetRegisterClass *RC,
429                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
430  llvm_unreachable("Unimplemented");
431}
432
433
434MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
435                                                    MachineInstr* MI,
436                                          const SmallVectorImpl<unsigned> &Ops,
437                                                    int FI) const {
438  // Hexagon_TODO: Implement.
439  return(0);
440}
441
442
443unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
444
445  MachineRegisterInfo &RegInfo = MF->getRegInfo();
446  const TargetRegisterClass *TRC;
447  if (VT == MVT::i1) {
448    TRC = &Hexagon::PredRegsRegClass;
449  } else if (VT == MVT::i32 || VT == MVT::f32) {
450    TRC = &Hexagon::IntRegsRegClass;
451  } else if (VT == MVT::i64 || VT == MVT::f64) {
452    TRC = &Hexagon::DoubleRegsRegClass;
453  } else {
454    llvm_unreachable("Cannot handle this register class");
455  }
456
457  unsigned NewReg = RegInfo.createVirtualRegister(TRC);
458  return NewReg;
459}
460
461bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
462  switch(MI->getOpcode()) {
463    default: return false;
464    // JMP_EQri
465    case Hexagon::JMP_EQriPt_nv_V4:
466    case Hexagon::JMP_EQriPnt_nv_V4:
467    case Hexagon::JMP_EQriNotPt_nv_V4:
468    case Hexagon::JMP_EQriNotPnt_nv_V4:
469
470    // JMP_EQri - with -1
471    case Hexagon::JMP_EQriPtneg_nv_V4:
472    case Hexagon::JMP_EQriPntneg_nv_V4:
473    case Hexagon::JMP_EQriNotPtneg_nv_V4:
474    case Hexagon::JMP_EQriNotPntneg_nv_V4:
475
476    // JMP_EQrr
477    case Hexagon::JMP_EQrrPt_nv_V4:
478    case Hexagon::JMP_EQrrPnt_nv_V4:
479    case Hexagon::JMP_EQrrNotPt_nv_V4:
480    case Hexagon::JMP_EQrrNotPnt_nv_V4:
481
482    // JMP_GTri
483    case Hexagon::JMP_GTriPt_nv_V4:
484    case Hexagon::JMP_GTriPnt_nv_V4:
485    case Hexagon::JMP_GTriNotPt_nv_V4:
486    case Hexagon::JMP_GTriNotPnt_nv_V4:
487
488    // JMP_GTri - with -1
489    case Hexagon::JMP_GTriPtneg_nv_V4:
490    case Hexagon::JMP_GTriPntneg_nv_V4:
491    case Hexagon::JMP_GTriNotPtneg_nv_V4:
492    case Hexagon::JMP_GTriNotPntneg_nv_V4:
493
494    // JMP_GTrr
495    case Hexagon::JMP_GTrrPt_nv_V4:
496    case Hexagon::JMP_GTrrPnt_nv_V4:
497    case Hexagon::JMP_GTrrNotPt_nv_V4:
498    case Hexagon::JMP_GTrrNotPnt_nv_V4:
499
500    // JMP_GTrrdn
501    case Hexagon::JMP_GTrrdnPt_nv_V4:
502    case Hexagon::JMP_GTrrdnPnt_nv_V4:
503    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
504    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
505
506    // JMP_GTUri
507    case Hexagon::JMP_GTUriPt_nv_V4:
508    case Hexagon::JMP_GTUriPnt_nv_V4:
509    case Hexagon::JMP_GTUriNotPt_nv_V4:
510    case Hexagon::JMP_GTUriNotPnt_nv_V4:
511
512    // JMP_GTUrr
513    case Hexagon::JMP_GTUrrPt_nv_V4:
514    case Hexagon::JMP_GTUrrPnt_nv_V4:
515    case Hexagon::JMP_GTUrrNotPt_nv_V4:
516    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
517
518    // JMP_GTUrrdn
519    case Hexagon::JMP_GTUrrdnPt_nv_V4:
520    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
521    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
522    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
523
524    // TFR_FI
525    case Hexagon::TFR_FI:
526      return true;
527  }
528}
529
530bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
531  switch(MI->getOpcode()) {
532    default: return false;
533    // JMP_EQri
534    case Hexagon::JMP_EQriPt_ie_nv_V4:
535    case Hexagon::JMP_EQriPnt_ie_nv_V4:
536    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
537    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
538
539    // JMP_EQri - with -1
540    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
541    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
542    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
543    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
544
545    // JMP_EQrr
546    case Hexagon::JMP_EQrrPt_ie_nv_V4:
547    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
548    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
549    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
550
551    // JMP_GTri
552    case Hexagon::JMP_GTriPt_ie_nv_V4:
553    case Hexagon::JMP_GTriPnt_ie_nv_V4:
554    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
555    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
556
557    // JMP_GTri - with -1
558    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
559    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
560    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
561    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
562
563    // JMP_GTrr
564    case Hexagon::JMP_GTrrPt_ie_nv_V4:
565    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
566    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
567    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
568
569    // JMP_GTrrdn
570    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
571    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
572    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
573    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
574
575    // JMP_GTUri
576    case Hexagon::JMP_GTUriPt_ie_nv_V4:
577    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
578    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
579    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
580
581    // JMP_GTUrr
582    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
583    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
584    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
585    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
586
587    // JMP_GTUrrdn
588    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
589    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
590    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
591    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
592
593    // V4 absolute set addressing.
594    case Hexagon::LDrid_abs_setimm_V4:
595    case Hexagon::LDriw_abs_setimm_V4:
596    case Hexagon::LDrih_abs_setimm_V4:
597    case Hexagon::LDrib_abs_setimm_V4:
598    case Hexagon::LDriuh_abs_setimm_V4:
599    case Hexagon::LDriub_abs_setimm_V4:
600
601    case Hexagon::STrid_abs_setimm_V4:
602    case Hexagon::STrib_abs_setimm_V4:
603    case Hexagon::STrih_abs_setimm_V4:
604    case Hexagon::STriw_abs_setimm_V4:
605
606    // V4 global address load.
607    case Hexagon::LDrid_GP_cPt_V4 :
608    case Hexagon::LDrid_GP_cNotPt_V4 :
609    case Hexagon::LDrid_GP_cdnPt_V4 :
610    case Hexagon::LDrid_GP_cdnNotPt_V4 :
611    case Hexagon::LDrib_GP_cPt_V4 :
612    case Hexagon::LDrib_GP_cNotPt_V4 :
613    case Hexagon::LDrib_GP_cdnPt_V4 :
614    case Hexagon::LDrib_GP_cdnNotPt_V4 :
615    case Hexagon::LDriub_GP_cPt_V4 :
616    case Hexagon::LDriub_GP_cNotPt_V4 :
617    case Hexagon::LDriub_GP_cdnPt_V4 :
618    case Hexagon::LDriub_GP_cdnNotPt_V4 :
619    case Hexagon::LDrih_GP_cPt_V4 :
620    case Hexagon::LDrih_GP_cNotPt_V4 :
621    case Hexagon::LDrih_GP_cdnPt_V4 :
622    case Hexagon::LDrih_GP_cdnNotPt_V4 :
623    case Hexagon::LDriuh_GP_cPt_V4 :
624    case Hexagon::LDriuh_GP_cNotPt_V4 :
625    case Hexagon::LDriuh_GP_cdnPt_V4 :
626    case Hexagon::LDriuh_GP_cdnNotPt_V4 :
627    case Hexagon::LDriw_GP_cPt_V4 :
628    case Hexagon::LDriw_GP_cNotPt_V4 :
629    case Hexagon::LDriw_GP_cdnPt_V4 :
630    case Hexagon::LDriw_GP_cdnNotPt_V4 :
631    case Hexagon::LDd_GP_cPt_V4 :
632    case Hexagon::LDd_GP_cNotPt_V4 :
633    case Hexagon::LDd_GP_cdnPt_V4 :
634    case Hexagon::LDd_GP_cdnNotPt_V4 :
635    case Hexagon::LDb_GP_cPt_V4 :
636    case Hexagon::LDb_GP_cNotPt_V4 :
637    case Hexagon::LDb_GP_cdnPt_V4 :
638    case Hexagon::LDb_GP_cdnNotPt_V4 :
639    case Hexagon::LDub_GP_cPt_V4 :
640    case Hexagon::LDub_GP_cNotPt_V4 :
641    case Hexagon::LDub_GP_cdnPt_V4 :
642    case Hexagon::LDub_GP_cdnNotPt_V4 :
643    case Hexagon::LDh_GP_cPt_V4 :
644    case Hexagon::LDh_GP_cNotPt_V4 :
645    case Hexagon::LDh_GP_cdnPt_V4 :
646    case Hexagon::LDh_GP_cdnNotPt_V4 :
647    case Hexagon::LDuh_GP_cPt_V4 :
648    case Hexagon::LDuh_GP_cNotPt_V4 :
649    case Hexagon::LDuh_GP_cdnPt_V4 :
650    case Hexagon::LDuh_GP_cdnNotPt_V4 :
651    case Hexagon::LDw_GP_cPt_V4 :
652    case Hexagon::LDw_GP_cNotPt_V4 :
653    case Hexagon::LDw_GP_cdnPt_V4 :
654    case Hexagon::LDw_GP_cdnNotPt_V4 :
655
656    // V4 global address store.
657    case Hexagon::STrid_GP_cPt_V4 :
658    case Hexagon::STrid_GP_cNotPt_V4 :
659    case Hexagon::STrid_GP_cdnPt_V4 :
660    case Hexagon::STrid_GP_cdnNotPt_V4 :
661    case Hexagon::STrib_GP_cPt_V4 :
662    case Hexagon::STrib_GP_cNotPt_V4 :
663    case Hexagon::STrib_GP_cdnPt_V4 :
664    case Hexagon::STrib_GP_cdnNotPt_V4 :
665    case Hexagon::STrih_GP_cPt_V4 :
666    case Hexagon::STrih_GP_cNotPt_V4 :
667    case Hexagon::STrih_GP_cdnPt_V4 :
668    case Hexagon::STrih_GP_cdnNotPt_V4 :
669    case Hexagon::STriw_GP_cPt_V4 :
670    case Hexagon::STriw_GP_cNotPt_V4 :
671    case Hexagon::STriw_GP_cdnPt_V4 :
672    case Hexagon::STriw_GP_cdnNotPt_V4 :
673    case Hexagon::STd_GP_cPt_V4 :
674    case Hexagon::STd_GP_cNotPt_V4 :
675    case Hexagon::STd_GP_cdnPt_V4 :
676    case Hexagon::STd_GP_cdnNotPt_V4 :
677    case Hexagon::STb_GP_cPt_V4 :
678    case Hexagon::STb_GP_cNotPt_V4 :
679    case Hexagon::STb_GP_cdnPt_V4 :
680    case Hexagon::STb_GP_cdnNotPt_V4 :
681    case Hexagon::STh_GP_cPt_V4 :
682    case Hexagon::STh_GP_cNotPt_V4 :
683    case Hexagon::STh_GP_cdnPt_V4 :
684    case Hexagon::STh_GP_cdnNotPt_V4 :
685    case Hexagon::STw_GP_cPt_V4 :
686    case Hexagon::STw_GP_cNotPt_V4 :
687    case Hexagon::STw_GP_cdnPt_V4 :
688    case Hexagon::STw_GP_cdnNotPt_V4 :
689
690    // V4 predicated global address new value store.
691    case Hexagon::STrib_GP_cPt_nv_V4 :
692    case Hexagon::STrib_GP_cNotPt_nv_V4 :
693    case Hexagon::STrib_GP_cdnPt_nv_V4 :
694    case Hexagon::STrib_GP_cdnNotPt_nv_V4 :
695    case Hexagon::STrih_GP_cPt_nv_V4 :
696    case Hexagon::STrih_GP_cNotPt_nv_V4 :
697    case Hexagon::STrih_GP_cdnPt_nv_V4 :
698    case Hexagon::STrih_GP_cdnNotPt_nv_V4 :
699    case Hexagon::STriw_GP_cPt_nv_V4 :
700    case Hexagon::STriw_GP_cNotPt_nv_V4 :
701    case Hexagon::STriw_GP_cdnPt_nv_V4 :
702    case Hexagon::STriw_GP_cdnNotPt_nv_V4 :
703    case Hexagon::STb_GP_cPt_nv_V4 :
704    case Hexagon::STb_GP_cNotPt_nv_V4 :
705    case Hexagon::STb_GP_cdnPt_nv_V4 :
706    case Hexagon::STb_GP_cdnNotPt_nv_V4 :
707    case Hexagon::STh_GP_cPt_nv_V4 :
708    case Hexagon::STh_GP_cNotPt_nv_V4 :
709    case Hexagon::STh_GP_cdnPt_nv_V4 :
710    case Hexagon::STh_GP_cdnNotPt_nv_V4 :
711    case Hexagon::STw_GP_cPt_nv_V4 :
712    case Hexagon::STw_GP_cNotPt_nv_V4 :
713    case Hexagon::STw_GP_cdnPt_nv_V4 :
714    case Hexagon::STw_GP_cdnNotPt_nv_V4 :
715
716    // TFR_FI
717    case Hexagon::TFR_FI_immext_V4:
718
719    // TFRI_F
720    case Hexagon::TFRI_f:
721    case Hexagon::TFRI_cPt_f:
722    case Hexagon::TFRI_cNotPt_f:
723    case Hexagon::CONST64_Float_Real:
724      return true;
725  }
726}
727
728bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
729  switch (MI->getOpcode()) {
730    default: return false;
731    // JMP_EQri
732    case Hexagon::JMP_EQriPt_nv_V4:
733    case Hexagon::JMP_EQriPnt_nv_V4:
734    case Hexagon::JMP_EQriNotPt_nv_V4:
735    case Hexagon::JMP_EQriNotPnt_nv_V4:
736    case Hexagon::JMP_EQriPt_ie_nv_V4:
737    case Hexagon::JMP_EQriPnt_ie_nv_V4:
738    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
739    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
740
741    // JMP_EQri - with -1
742    case Hexagon::JMP_EQriPtneg_nv_V4:
743    case Hexagon::JMP_EQriPntneg_nv_V4:
744    case Hexagon::JMP_EQriNotPtneg_nv_V4:
745    case Hexagon::JMP_EQriNotPntneg_nv_V4:
746    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
747    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
748    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
749    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
750
751    // JMP_EQrr
752    case Hexagon::JMP_EQrrPt_nv_V4:
753    case Hexagon::JMP_EQrrPnt_nv_V4:
754    case Hexagon::JMP_EQrrNotPt_nv_V4:
755    case Hexagon::JMP_EQrrNotPnt_nv_V4:
756    case Hexagon::JMP_EQrrPt_ie_nv_V4:
757    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
758    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
759    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
760
761    // JMP_GTri
762    case Hexagon::JMP_GTriPt_nv_V4:
763    case Hexagon::JMP_GTriPnt_nv_V4:
764    case Hexagon::JMP_GTriNotPt_nv_V4:
765    case Hexagon::JMP_GTriNotPnt_nv_V4:
766    case Hexagon::JMP_GTriPt_ie_nv_V4:
767    case Hexagon::JMP_GTriPnt_ie_nv_V4:
768    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
769    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
770
771    // JMP_GTri - with -1
772    case Hexagon::JMP_GTriPtneg_nv_V4:
773    case Hexagon::JMP_GTriPntneg_nv_V4:
774    case Hexagon::JMP_GTriNotPtneg_nv_V4:
775    case Hexagon::JMP_GTriNotPntneg_nv_V4:
776    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
777    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
778    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
779    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
780
781    // JMP_GTrr
782    case Hexagon::JMP_GTrrPt_nv_V4:
783    case Hexagon::JMP_GTrrPnt_nv_V4:
784    case Hexagon::JMP_GTrrNotPt_nv_V4:
785    case Hexagon::JMP_GTrrNotPnt_nv_V4:
786    case Hexagon::JMP_GTrrPt_ie_nv_V4:
787    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
788    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
789    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
790
791    // JMP_GTrrdn
792    case Hexagon::JMP_GTrrdnPt_nv_V4:
793    case Hexagon::JMP_GTrrdnPnt_nv_V4:
794    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
795    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
796    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
797    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
798    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
799    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
800
801    // JMP_GTUri
802    case Hexagon::JMP_GTUriPt_nv_V4:
803    case Hexagon::JMP_GTUriPnt_nv_V4:
804    case Hexagon::JMP_GTUriNotPt_nv_V4:
805    case Hexagon::JMP_GTUriNotPnt_nv_V4:
806    case Hexagon::JMP_GTUriPt_ie_nv_V4:
807    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
808    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
809    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
810
811    // JMP_GTUrr
812    case Hexagon::JMP_GTUrrPt_nv_V4:
813    case Hexagon::JMP_GTUrrPnt_nv_V4:
814    case Hexagon::JMP_GTUrrNotPt_nv_V4:
815    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
816    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
817    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
818    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
819    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
820
821    // JMP_GTUrrdn
822    case Hexagon::JMP_GTUrrdnPt_nv_V4:
823    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
824    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
825    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
826    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
827    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
828    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
829    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
830      return true;
831  }
832}
833
834unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
835  switch(MI->getOpcode()) {
836    default: llvm_unreachable("Unknown type of instruction.");
837    // JMP_EQri
838    case Hexagon::JMP_EQriPt_nv_V4:
839      return Hexagon::JMP_EQriPt_ie_nv_V4;
840    case Hexagon::JMP_EQriNotPt_nv_V4:
841      return Hexagon::JMP_EQriNotPt_ie_nv_V4;
842    case Hexagon::JMP_EQriPnt_nv_V4:
843      return Hexagon::JMP_EQriPnt_ie_nv_V4;
844    case Hexagon::JMP_EQriNotPnt_nv_V4:
845      return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
846
847    // JMP_EQri -- with -1
848    case Hexagon::JMP_EQriPtneg_nv_V4:
849      return Hexagon::JMP_EQriPtneg_ie_nv_V4;
850    case Hexagon::JMP_EQriNotPtneg_nv_V4:
851      return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
852    case Hexagon::JMP_EQriPntneg_nv_V4:
853      return Hexagon::JMP_EQriPntneg_ie_nv_V4;
854    case Hexagon::JMP_EQriNotPntneg_nv_V4:
855      return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
856
857    // JMP_EQrr
858    case Hexagon::JMP_EQrrPt_nv_V4:
859      return Hexagon::JMP_EQrrPt_ie_nv_V4;
860    case Hexagon::JMP_EQrrNotPt_nv_V4:
861      return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
862    case Hexagon::JMP_EQrrPnt_nv_V4:
863      return Hexagon::JMP_EQrrPnt_ie_nv_V4;
864    case Hexagon::JMP_EQrrNotPnt_nv_V4:
865      return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
866
867    // JMP_GTri
868    case Hexagon::JMP_GTriPt_nv_V4:
869      return Hexagon::JMP_GTriPt_ie_nv_V4;
870    case Hexagon::JMP_GTriNotPt_nv_V4:
871      return Hexagon::JMP_GTriNotPt_ie_nv_V4;
872    case Hexagon::JMP_GTriPnt_nv_V4:
873      return Hexagon::JMP_GTriPnt_ie_nv_V4;
874    case Hexagon::JMP_GTriNotPnt_nv_V4:
875      return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
876
877    // JMP_GTri -- with -1
878    case Hexagon::JMP_GTriPtneg_nv_V4:
879      return Hexagon::JMP_GTriPtneg_ie_nv_V4;
880    case Hexagon::JMP_GTriNotPtneg_nv_V4:
881      return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
882    case Hexagon::JMP_GTriPntneg_nv_V4:
883      return Hexagon::JMP_GTriPntneg_ie_nv_V4;
884    case Hexagon::JMP_GTriNotPntneg_nv_V4:
885      return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
886
887    // JMP_GTrr
888    case Hexagon::JMP_GTrrPt_nv_V4:
889      return Hexagon::JMP_GTrrPt_ie_nv_V4;
890    case Hexagon::JMP_GTrrNotPt_nv_V4:
891      return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
892    case Hexagon::JMP_GTrrPnt_nv_V4:
893      return Hexagon::JMP_GTrrPnt_ie_nv_V4;
894    case Hexagon::JMP_GTrrNotPnt_nv_V4:
895      return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
896
897    // JMP_GTrrdn
898    case Hexagon::JMP_GTrrdnPt_nv_V4:
899      return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
900    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
901      return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
902    case Hexagon::JMP_GTrrdnPnt_nv_V4:
903      return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
904    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
905      return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
906
907    // JMP_GTUri
908    case Hexagon::JMP_GTUriPt_nv_V4:
909      return Hexagon::JMP_GTUriPt_ie_nv_V4;
910    case Hexagon::JMP_GTUriNotPt_nv_V4:
911      return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
912    case Hexagon::JMP_GTUriPnt_nv_V4:
913      return Hexagon::JMP_GTUriPnt_ie_nv_V4;
914    case Hexagon::JMP_GTUriNotPnt_nv_V4:
915      return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
916
917    // JMP_GTUrr
918    case Hexagon::JMP_GTUrrPt_nv_V4:
919      return Hexagon::JMP_GTUrrPt_ie_nv_V4;
920    case Hexagon::JMP_GTUrrNotPt_nv_V4:
921      return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
922    case Hexagon::JMP_GTUrrPnt_nv_V4:
923      return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
924    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
925      return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
926
927    // JMP_GTUrrdn
928    case Hexagon::JMP_GTUrrdnPt_nv_V4:
929      return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
930    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
931      return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
932    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
933      return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
934    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
935      return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
936
937    case Hexagon::TFR_FI:
938        return Hexagon::TFR_FI_immext_V4;
939
940    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
941    case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
942    case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
943    case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
944    case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
945    case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
946    case Hexagon::MEMw_ORr_indexed_MEM_V4 :
947    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
948    case Hexagon::MEMw_ADDi_MEM_V4 :
949    case Hexagon::MEMw_SUBi_MEM_V4 :
950    case Hexagon::MEMw_ADDr_MEM_V4 :
951    case Hexagon::MEMw_SUBr_MEM_V4 :
952    case Hexagon::MEMw_ANDr_MEM_V4 :
953    case Hexagon::MEMw_ORr_MEM_V4 :
954    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
955    case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
956    case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
957    case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
958    case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
959    case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
960    case Hexagon::MEMh_ORr_indexed_MEM_V4 :
961    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
962    case Hexagon::MEMh_ADDi_MEM_V4 :
963    case Hexagon::MEMh_SUBi_MEM_V4 :
964    case Hexagon::MEMh_ADDr_MEM_V4 :
965    case Hexagon::MEMh_SUBr_MEM_V4 :
966    case Hexagon::MEMh_ANDr_MEM_V4 :
967    case Hexagon::MEMh_ORr_MEM_V4 :
968    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
969    case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
970    case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
971    case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
972    case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
973    case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
974    case Hexagon::MEMb_ORr_indexed_MEM_V4 :
975    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
976    case Hexagon::MEMb_ADDi_MEM_V4 :
977    case Hexagon::MEMb_SUBi_MEM_V4 :
978    case Hexagon::MEMb_ADDr_MEM_V4 :
979    case Hexagon::MEMb_SUBr_MEM_V4 :
980    case Hexagon::MEMb_ANDr_MEM_V4 :
981    case Hexagon::MEMb_ORr_MEM_V4 :
982      llvm_unreachable("Needs implementing.");
983  }
984}
985
986unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {
987  switch(MI->getOpcode()) {
988    default: llvm_unreachable("Unknown type of jump instruction.");
989    // JMP_EQri
990    case Hexagon::JMP_EQriPt_ie_nv_V4:
991      return Hexagon::JMP_EQriPt_nv_V4;
992    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
993      return Hexagon::JMP_EQriNotPt_nv_V4;
994    case Hexagon::JMP_EQriPnt_ie_nv_V4:
995      return Hexagon::JMP_EQriPnt_nv_V4;
996    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
997      return Hexagon::JMP_EQriNotPnt_nv_V4;
998
999    // JMP_EQri -- with -1
1000    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
1001      return Hexagon::JMP_EQriPtneg_nv_V4;
1002    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
1003      return Hexagon::JMP_EQriNotPtneg_nv_V4;
1004    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
1005      return Hexagon::JMP_EQriPntneg_nv_V4;
1006    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
1007      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1008
1009    // JMP_EQrr
1010    case Hexagon::JMP_EQrrPt_ie_nv_V4:
1011      return Hexagon::JMP_EQrrPt_nv_V4;
1012    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
1013      return Hexagon::JMP_EQrrNotPt_nv_V4;
1014    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
1015      return Hexagon::JMP_EQrrPnt_nv_V4;
1016    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
1017      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1018
1019    // JMP_GTri
1020    case Hexagon::JMP_GTriPt_ie_nv_V4:
1021      return Hexagon::JMP_GTriPt_nv_V4;
1022    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
1023      return Hexagon::JMP_GTriNotPt_nv_V4;
1024    case Hexagon::JMP_GTriPnt_ie_nv_V4:
1025      return Hexagon::JMP_GTriPnt_nv_V4;
1026    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
1027      return Hexagon::JMP_GTriNotPnt_nv_V4;
1028
1029    // JMP_GTri -- with -1
1030    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
1031      return Hexagon::JMP_GTriPtneg_nv_V4;
1032    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
1033      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1034    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
1035      return Hexagon::JMP_GTriPntneg_nv_V4;
1036    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
1037      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1038
1039    // JMP_GTrr
1040    case Hexagon::JMP_GTrrPt_ie_nv_V4:
1041      return Hexagon::JMP_GTrrPt_nv_V4;
1042    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
1043      return Hexagon::JMP_GTrrNotPt_nv_V4;
1044    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
1045      return Hexagon::JMP_GTrrPnt_nv_V4;
1046    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
1047      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1048
1049    // JMP_GTrrdn
1050    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
1051      return Hexagon::JMP_GTrrdnPt_nv_V4;
1052    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
1053      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1054    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
1055      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1056    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
1057      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1058
1059    // JMP_GTUri
1060    case Hexagon::JMP_GTUriPt_ie_nv_V4:
1061      return Hexagon::JMP_GTUriPt_nv_V4;
1062    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
1063      return Hexagon::JMP_GTUriNotPt_nv_V4;
1064    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
1065      return Hexagon::JMP_GTUriPnt_nv_V4;
1066    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
1067      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1068
1069    // JMP_GTUrr
1070    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
1071      return Hexagon::JMP_GTUrrPt_nv_V4;
1072    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
1073      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1074    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
1075      return Hexagon::JMP_GTUrrPnt_nv_V4;
1076    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
1077      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1078
1079    // JMP_GTUrrdn
1080    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
1081      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1082    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
1083      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1084    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
1085      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1086    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
1087      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1088  }
1089}
1090
1091
1092bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
1093  switch (MI->getOpcode()) {
1094    default: return false;
1095    // Store Byte
1096    case Hexagon::STrib_nv_V4:
1097    case Hexagon::STrib_indexed_nv_V4:
1098    case Hexagon::STrib_indexed_shl_nv_V4:
1099    case Hexagon::STrib_shl_nv_V4:
1100    case Hexagon::STrib_GP_nv_V4:
1101    case Hexagon::STb_GP_nv_V4:
1102    case Hexagon::POST_STbri_nv_V4:
1103    case Hexagon::STrib_cPt_nv_V4:
1104    case Hexagon::STrib_cdnPt_nv_V4:
1105    case Hexagon::STrib_cNotPt_nv_V4:
1106    case Hexagon::STrib_cdnNotPt_nv_V4:
1107    case Hexagon::STrib_indexed_cPt_nv_V4:
1108    case Hexagon::STrib_indexed_cdnPt_nv_V4:
1109    case Hexagon::STrib_indexed_cNotPt_nv_V4:
1110    case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
1111    case Hexagon::STrib_indexed_shl_cPt_nv_V4:
1112    case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1113    case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
1114    case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1115    case Hexagon::POST_STbri_cPt_nv_V4:
1116    case Hexagon::POST_STbri_cdnPt_nv_V4:
1117    case Hexagon::POST_STbri_cNotPt_nv_V4:
1118    case Hexagon::POST_STbri_cdnNotPt_nv_V4:
1119    case Hexagon::STb_GP_cPt_nv_V4:
1120    case Hexagon::STb_GP_cNotPt_nv_V4:
1121    case Hexagon::STb_GP_cdnPt_nv_V4:
1122    case Hexagon::STb_GP_cdnNotPt_nv_V4:
1123    case Hexagon::STrib_GP_cPt_nv_V4:
1124    case Hexagon::STrib_GP_cNotPt_nv_V4:
1125    case Hexagon::STrib_GP_cdnPt_nv_V4:
1126    case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1127    case Hexagon::STrib_abs_nv_V4:
1128    case Hexagon::STrib_abs_cPt_nv_V4:
1129    case Hexagon::STrib_abs_cdnPt_nv_V4:
1130    case Hexagon::STrib_abs_cNotPt_nv_V4:
1131    case Hexagon::STrib_abs_cdnNotPt_nv_V4:
1132    case Hexagon::STrib_imm_abs_nv_V4:
1133    case Hexagon::STrib_imm_abs_cPt_nv_V4:
1134    case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
1135    case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
1136    case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
1137
1138    // Store Halfword
1139    case Hexagon::STrih_nv_V4:
1140    case Hexagon::STrih_indexed_nv_V4:
1141    case Hexagon::STrih_indexed_shl_nv_V4:
1142    case Hexagon::STrih_shl_nv_V4:
1143    case Hexagon::STrih_GP_nv_V4:
1144    case Hexagon::STh_GP_nv_V4:
1145    case Hexagon::POST_SThri_nv_V4:
1146    case Hexagon::STrih_cPt_nv_V4:
1147    case Hexagon::STrih_cdnPt_nv_V4:
1148    case Hexagon::STrih_cNotPt_nv_V4:
1149    case Hexagon::STrih_cdnNotPt_nv_V4:
1150    case Hexagon::STrih_indexed_cPt_nv_V4:
1151    case Hexagon::STrih_indexed_cdnPt_nv_V4:
1152    case Hexagon::STrih_indexed_cNotPt_nv_V4:
1153    case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1154    case Hexagon::STrih_indexed_shl_cPt_nv_V4:
1155    case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
1156    case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
1157    case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
1158    case Hexagon::POST_SThri_cPt_nv_V4:
1159    case Hexagon::POST_SThri_cdnPt_nv_V4:
1160    case Hexagon::POST_SThri_cNotPt_nv_V4:
1161    case Hexagon::POST_SThri_cdnNotPt_nv_V4:
1162    case Hexagon::STh_GP_cPt_nv_V4:
1163    case Hexagon::STh_GP_cNotPt_nv_V4:
1164    case Hexagon::STh_GP_cdnPt_nv_V4:
1165    case Hexagon::STh_GP_cdnNotPt_nv_V4:
1166    case Hexagon::STrih_GP_cPt_nv_V4:
1167    case Hexagon::STrih_GP_cNotPt_nv_V4:
1168    case Hexagon::STrih_GP_cdnPt_nv_V4:
1169    case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1170    case Hexagon::STrih_abs_nv_V4:
1171    case Hexagon::STrih_abs_cPt_nv_V4:
1172    case Hexagon::STrih_abs_cdnPt_nv_V4:
1173    case Hexagon::STrih_abs_cNotPt_nv_V4:
1174    case Hexagon::STrih_abs_cdnNotPt_nv_V4:
1175    case Hexagon::STrih_imm_abs_nv_V4:
1176    case Hexagon::STrih_imm_abs_cPt_nv_V4:
1177    case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
1178    case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
1179    case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
1180
1181    // Store Word
1182    case Hexagon::STriw_nv_V4:
1183    case Hexagon::STriw_indexed_nv_V4:
1184    case Hexagon::STriw_indexed_shl_nv_V4:
1185    case Hexagon::STriw_shl_nv_V4:
1186    case Hexagon::STriw_GP_nv_V4:
1187    case Hexagon::STw_GP_nv_V4:
1188    case Hexagon::POST_STwri_nv_V4:
1189    case Hexagon::STriw_cPt_nv_V4:
1190    case Hexagon::STriw_cdnPt_nv_V4:
1191    case Hexagon::STriw_cNotPt_nv_V4:
1192    case Hexagon::STriw_cdnNotPt_nv_V4:
1193    case Hexagon::STriw_indexed_cPt_nv_V4:
1194    case Hexagon::STriw_indexed_cdnPt_nv_V4:
1195    case Hexagon::STriw_indexed_cNotPt_nv_V4:
1196    case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
1197    case Hexagon::STriw_indexed_shl_cPt_nv_V4:
1198    case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
1199    case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
1200    case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
1201    case Hexagon::POST_STwri_cPt_nv_V4:
1202    case Hexagon::POST_STwri_cdnPt_nv_V4:
1203    case Hexagon::POST_STwri_cNotPt_nv_V4:
1204    case Hexagon::POST_STwri_cdnNotPt_nv_V4:
1205    case Hexagon::STw_GP_cPt_nv_V4:
1206    case Hexagon::STw_GP_cNotPt_nv_V4:
1207    case Hexagon::STw_GP_cdnPt_nv_V4:
1208    case Hexagon::STw_GP_cdnNotPt_nv_V4:
1209    case Hexagon::STriw_GP_cPt_nv_V4:
1210    case Hexagon::STriw_GP_cNotPt_nv_V4:
1211    case Hexagon::STriw_GP_cdnPt_nv_V4:
1212    case Hexagon::STriw_GP_cdnNotPt_nv_V4:
1213    case Hexagon::STriw_abs_nv_V4:
1214    case Hexagon::STriw_abs_cPt_nv_V4:
1215    case Hexagon::STriw_abs_cdnPt_nv_V4:
1216    case Hexagon::STriw_abs_cNotPt_nv_V4:
1217    case Hexagon::STriw_abs_cdnNotPt_nv_V4:
1218    case Hexagon::STriw_imm_abs_nv_V4:
1219    case Hexagon::STriw_imm_abs_cPt_nv_V4:
1220    case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
1221    case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
1222    case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
1223      return true;
1224  }
1225}
1226
1227bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1228  switch (MI->getOpcode())
1229  {
1230    default: return false;
1231    // Load Byte
1232    case Hexagon::POST_LDrib:
1233    case Hexagon::POST_LDrib_cPt:
1234    case Hexagon::POST_LDrib_cNotPt:
1235    case Hexagon::POST_LDrib_cdnPt_V4:
1236    case Hexagon::POST_LDrib_cdnNotPt_V4:
1237
1238    // Load unsigned byte
1239    case Hexagon::POST_LDriub:
1240    case Hexagon::POST_LDriub_cPt:
1241    case Hexagon::POST_LDriub_cNotPt:
1242    case Hexagon::POST_LDriub_cdnPt_V4:
1243    case Hexagon::POST_LDriub_cdnNotPt_V4:
1244
1245    // Load halfword
1246    case Hexagon::POST_LDrih:
1247    case Hexagon::POST_LDrih_cPt:
1248    case Hexagon::POST_LDrih_cNotPt:
1249    case Hexagon::POST_LDrih_cdnPt_V4:
1250    case Hexagon::POST_LDrih_cdnNotPt_V4:
1251
1252    // Load unsigned halfword
1253    case Hexagon::POST_LDriuh:
1254    case Hexagon::POST_LDriuh_cPt:
1255    case Hexagon::POST_LDriuh_cNotPt:
1256    case Hexagon::POST_LDriuh_cdnPt_V4:
1257    case Hexagon::POST_LDriuh_cdnNotPt_V4:
1258
1259    // Load word
1260    case Hexagon::POST_LDriw:
1261    case Hexagon::POST_LDriw_cPt:
1262    case Hexagon::POST_LDriw_cNotPt:
1263    case Hexagon::POST_LDriw_cdnPt_V4:
1264    case Hexagon::POST_LDriw_cdnNotPt_V4:
1265
1266    // Load double word
1267    case Hexagon::POST_LDrid:
1268    case Hexagon::POST_LDrid_cPt:
1269    case Hexagon::POST_LDrid_cNotPt:
1270    case Hexagon::POST_LDrid_cdnPt_V4:
1271    case Hexagon::POST_LDrid_cdnNotPt_V4:
1272
1273    // Store byte
1274    case Hexagon::POST_STbri:
1275    case Hexagon::POST_STbri_cPt:
1276    case Hexagon::POST_STbri_cNotPt:
1277    case Hexagon::POST_STbri_cdnPt_V4:
1278    case Hexagon::POST_STbri_cdnNotPt_V4:
1279
1280    // Store halfword
1281    case Hexagon::POST_SThri:
1282    case Hexagon::POST_SThri_cPt:
1283    case Hexagon::POST_SThri_cNotPt:
1284    case Hexagon::POST_SThri_cdnPt_V4:
1285    case Hexagon::POST_SThri_cdnNotPt_V4:
1286
1287    // Store word
1288    case Hexagon::POST_STwri:
1289    case Hexagon::POST_STwri_cPt:
1290    case Hexagon::POST_STwri_cNotPt:
1291    case Hexagon::POST_STwri_cdnPt_V4:
1292    case Hexagon::POST_STwri_cdnNotPt_V4:
1293
1294    // Store double word
1295    case Hexagon::POST_STdri:
1296    case Hexagon::POST_STdri_cPt:
1297    case Hexagon::POST_STdri_cNotPt:
1298    case Hexagon::POST_STdri_cdnPt_V4:
1299    case Hexagon::POST_STdri_cdnNotPt_V4:
1300      return true;
1301  }
1302}
1303
1304bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
1305  return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
1306}
1307
1308bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1309  bool isPred = MI->getDesc().isPredicable();
1310
1311  if (!isPred)
1312    return false;
1313
1314  const int Opc = MI->getOpcode();
1315
1316  switch(Opc) {
1317  case Hexagon::TFRI:
1318    return isInt<12>(MI->getOperand(1).getImm());
1319
1320  case Hexagon::STrid:
1321  case Hexagon::STrid_indexed:
1322    return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1323
1324  case Hexagon::STriw:
1325  case Hexagon::STriw_indexed:
1326  case Hexagon::STriw_nv_V4:
1327    return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1328
1329  case Hexagon::STrih:
1330  case Hexagon::STrih_indexed:
1331  case Hexagon::STrih_nv_V4:
1332    return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1333
1334  case Hexagon::STrib:
1335  case Hexagon::STrib_indexed:
1336  case Hexagon::STrib_nv_V4:
1337    return isUInt<6>(MI->getOperand(1).getImm());
1338
1339  case Hexagon::LDrid:
1340  case Hexagon::LDrid_indexed:
1341    return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1342
1343  case Hexagon::LDriw:
1344  case Hexagon::LDriw_indexed:
1345    return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1346
1347  case Hexagon::LDrih:
1348  case Hexagon::LDriuh:
1349  case Hexagon::LDrih_indexed:
1350  case Hexagon::LDriuh_indexed:
1351    return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1352
1353  case Hexagon::LDrib:
1354  case Hexagon::LDriub:
1355  case Hexagon::LDrib_indexed:
1356  case Hexagon::LDriub_indexed:
1357    return isUInt<6>(MI->getOperand(2).getImm());
1358
1359  case Hexagon::POST_LDrid:
1360    return isShiftedInt<4,3>(MI->getOperand(3).getImm());
1361
1362  case Hexagon::POST_LDriw:
1363    return isShiftedInt<4,2>(MI->getOperand(3).getImm());
1364
1365  case Hexagon::POST_LDrih:
1366  case Hexagon::POST_LDriuh:
1367    return isShiftedInt<4,1>(MI->getOperand(3).getImm());
1368
1369  case Hexagon::POST_LDrib:
1370  case Hexagon::POST_LDriub:
1371    return isInt<4>(MI->getOperand(3).getImm());
1372
1373  case Hexagon::STrib_imm_V4:
1374  case Hexagon::STrih_imm_V4:
1375  case Hexagon::STriw_imm_V4:
1376    return (isUInt<6>(MI->getOperand(1).getImm()) &&
1377            isInt<6>(MI->getOperand(2).getImm()));
1378
1379  case Hexagon::ADD_ri:
1380    return isInt<8>(MI->getOperand(2).getImm());
1381
1382  case Hexagon::ASLH:
1383  case Hexagon::ASRH:
1384  case Hexagon::SXTB:
1385  case Hexagon::SXTH:
1386  case Hexagon::ZXTB:
1387  case Hexagon::ZXTH:
1388    return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1389
1390  case Hexagon::JMPR:
1391    return false;
1392  }
1393
1394  return true;
1395}
1396
1397unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1398  switch(Opc) {
1399    default: llvm_unreachable("Unexpected predicated instruction");
1400    case Hexagon::TFR_cPt:
1401      return Hexagon::TFR_cNotPt;
1402    case Hexagon::TFR_cNotPt:
1403      return Hexagon::TFR_cPt;
1404
1405    case Hexagon::TFRI_cPt:
1406      return Hexagon::TFRI_cNotPt;
1407    case Hexagon::TFRI_cNotPt:
1408      return Hexagon::TFRI_cPt;
1409
1410    case Hexagon::JMP_c:
1411      return Hexagon::JMP_cNot;
1412    case Hexagon::JMP_cNot:
1413      return Hexagon::JMP_c;
1414
1415    case Hexagon::ADD_ri_cPt:
1416      return Hexagon::ADD_ri_cNotPt;
1417    case Hexagon::ADD_ri_cNotPt:
1418      return Hexagon::ADD_ri_cPt;
1419
1420    case Hexagon::ADD_rr_cPt:
1421      return Hexagon::ADD_rr_cNotPt;
1422    case Hexagon::ADD_rr_cNotPt:
1423      return Hexagon::ADD_rr_cPt;
1424
1425    case Hexagon::XOR_rr_cPt:
1426      return Hexagon::XOR_rr_cNotPt;
1427    case Hexagon::XOR_rr_cNotPt:
1428      return Hexagon::XOR_rr_cPt;
1429
1430    case Hexagon::AND_rr_cPt:
1431      return Hexagon::AND_rr_cNotPt;
1432    case Hexagon::AND_rr_cNotPt:
1433      return Hexagon::AND_rr_cPt;
1434
1435    case Hexagon::OR_rr_cPt:
1436      return Hexagon::OR_rr_cNotPt;
1437    case Hexagon::OR_rr_cNotPt:
1438      return Hexagon::OR_rr_cPt;
1439
1440    case Hexagon::SUB_rr_cPt:
1441      return Hexagon::SUB_rr_cNotPt;
1442    case Hexagon::SUB_rr_cNotPt:
1443      return Hexagon::SUB_rr_cPt;
1444
1445    case Hexagon::COMBINE_rr_cPt:
1446      return Hexagon::COMBINE_rr_cNotPt;
1447    case Hexagon::COMBINE_rr_cNotPt:
1448      return Hexagon::COMBINE_rr_cPt;
1449
1450    case Hexagon::ASLH_cPt_V4:
1451      return Hexagon::ASLH_cNotPt_V4;
1452    case Hexagon::ASLH_cNotPt_V4:
1453      return Hexagon::ASLH_cPt_V4;
1454
1455    case Hexagon::ASRH_cPt_V4:
1456      return Hexagon::ASRH_cNotPt_V4;
1457    case Hexagon::ASRH_cNotPt_V4:
1458      return Hexagon::ASRH_cPt_V4;
1459
1460    case Hexagon::SXTB_cPt_V4:
1461      return Hexagon::SXTB_cNotPt_V4;
1462    case Hexagon::SXTB_cNotPt_V4:
1463      return Hexagon::SXTB_cPt_V4;
1464
1465    case Hexagon::SXTH_cPt_V4:
1466      return Hexagon::SXTH_cNotPt_V4;
1467    case Hexagon::SXTH_cNotPt_V4:
1468      return Hexagon::SXTH_cPt_V4;
1469
1470    case Hexagon::ZXTB_cPt_V4:
1471      return Hexagon::ZXTB_cNotPt_V4;
1472    case Hexagon::ZXTB_cNotPt_V4:
1473      return Hexagon::ZXTB_cPt_V4;
1474
1475    case Hexagon::ZXTH_cPt_V4:
1476      return Hexagon::ZXTH_cNotPt_V4;
1477    case Hexagon::ZXTH_cNotPt_V4:
1478      return Hexagon::ZXTH_cPt_V4;
1479
1480
1481    case Hexagon::JMPR_cPt:
1482      return Hexagon::JMPR_cNotPt;
1483    case Hexagon::JMPR_cNotPt:
1484      return Hexagon::JMPR_cPt;
1485
1486  // V4 indexed+scaled load.
1487    case Hexagon::LDrid_indexed_cPt_V4:
1488      return Hexagon::LDrid_indexed_cNotPt_V4;
1489    case Hexagon::LDrid_indexed_cNotPt_V4:
1490      return Hexagon::LDrid_indexed_cPt_V4;
1491
1492    case Hexagon::LDrid_indexed_shl_cPt_V4:
1493      return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1494    case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1495      return Hexagon::LDrid_indexed_shl_cPt_V4;
1496
1497    case Hexagon::LDrib_indexed_cPt_V4:
1498      return Hexagon::LDrib_indexed_cNotPt_V4;
1499    case Hexagon::LDrib_indexed_cNotPt_V4:
1500      return Hexagon::LDrib_indexed_cPt_V4;
1501
1502    case Hexagon::LDriub_indexed_cPt_V4:
1503      return Hexagon::LDriub_indexed_cNotPt_V4;
1504    case Hexagon::LDriub_indexed_cNotPt_V4:
1505      return Hexagon::LDriub_indexed_cPt_V4;
1506
1507    case Hexagon::LDrib_indexed_shl_cPt_V4:
1508      return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1509    case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1510      return Hexagon::LDrib_indexed_shl_cPt_V4;
1511
1512    case Hexagon::LDriub_indexed_shl_cPt_V4:
1513      return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1514    case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1515      return Hexagon::LDriub_indexed_shl_cPt_V4;
1516
1517    case Hexagon::LDrih_indexed_cPt_V4:
1518      return Hexagon::LDrih_indexed_cNotPt_V4;
1519    case Hexagon::LDrih_indexed_cNotPt_V4:
1520      return Hexagon::LDrih_indexed_cPt_V4;
1521
1522    case Hexagon::LDriuh_indexed_cPt_V4:
1523      return Hexagon::LDriuh_indexed_cNotPt_V4;
1524    case Hexagon::LDriuh_indexed_cNotPt_V4:
1525      return Hexagon::LDriuh_indexed_cPt_V4;
1526
1527    case Hexagon::LDrih_indexed_shl_cPt_V4:
1528      return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1529    case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1530      return Hexagon::LDrih_indexed_shl_cPt_V4;
1531
1532    case Hexagon::LDriuh_indexed_shl_cPt_V4:
1533      return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1534    case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1535      return Hexagon::LDriuh_indexed_shl_cPt_V4;
1536
1537    case Hexagon::LDriw_indexed_cPt_V4:
1538      return Hexagon::LDriw_indexed_cNotPt_V4;
1539    case Hexagon::LDriw_indexed_cNotPt_V4:
1540      return Hexagon::LDriw_indexed_cPt_V4;
1541
1542    case Hexagon::LDriw_indexed_shl_cPt_V4:
1543      return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1544    case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1545      return Hexagon::LDriw_indexed_shl_cPt_V4;
1546
1547    // Byte.
1548    case Hexagon::POST_STbri_cPt:
1549      return Hexagon::POST_STbri_cNotPt;
1550    case Hexagon::POST_STbri_cNotPt:
1551      return Hexagon::POST_STbri_cPt;
1552
1553    case Hexagon::STrib_cPt:
1554      return Hexagon::STrib_cNotPt;
1555    case Hexagon::STrib_cNotPt:
1556      return Hexagon::STrib_cPt;
1557
1558    case Hexagon::STrib_indexed_cPt:
1559      return Hexagon::STrib_indexed_cNotPt;
1560    case Hexagon::STrib_indexed_cNotPt:
1561      return Hexagon::STrib_indexed_cPt;
1562
1563    case Hexagon::STrib_imm_cPt_V4:
1564      return Hexagon::STrib_imm_cNotPt_V4;
1565    case Hexagon::STrib_imm_cNotPt_V4:
1566      return Hexagon::STrib_imm_cPt_V4;
1567
1568    case Hexagon::STrib_indexed_shl_cPt_V4:
1569      return Hexagon::STrib_indexed_shl_cNotPt_V4;
1570    case Hexagon::STrib_indexed_shl_cNotPt_V4:
1571      return Hexagon::STrib_indexed_shl_cPt_V4;
1572
1573  // Halfword.
1574    case Hexagon::POST_SThri_cPt:
1575      return Hexagon::POST_SThri_cNotPt;
1576    case Hexagon::POST_SThri_cNotPt:
1577      return Hexagon::POST_SThri_cPt;
1578
1579    case Hexagon::STrih_cPt:
1580      return Hexagon::STrih_cNotPt;
1581    case Hexagon::STrih_cNotPt:
1582      return Hexagon::STrih_cPt;
1583
1584    case Hexagon::STrih_indexed_cPt:
1585      return Hexagon::STrih_indexed_cNotPt;
1586    case Hexagon::STrih_indexed_cNotPt:
1587      return Hexagon::STrih_indexed_cPt;
1588
1589    case Hexagon::STrih_imm_cPt_V4:
1590      return Hexagon::STrih_imm_cNotPt_V4;
1591    case Hexagon::STrih_imm_cNotPt_V4:
1592      return Hexagon::STrih_imm_cPt_V4;
1593
1594    case Hexagon::STrih_indexed_shl_cPt_V4:
1595      return Hexagon::STrih_indexed_shl_cNotPt_V4;
1596    case Hexagon::STrih_indexed_shl_cNotPt_V4:
1597      return Hexagon::STrih_indexed_shl_cPt_V4;
1598
1599  // Word.
1600    case Hexagon::POST_STwri_cPt:
1601      return Hexagon::POST_STwri_cNotPt;
1602    case Hexagon::POST_STwri_cNotPt:
1603      return Hexagon::POST_STwri_cPt;
1604
1605    case Hexagon::STriw_cPt:
1606      return Hexagon::STriw_cNotPt;
1607    case Hexagon::STriw_cNotPt:
1608      return Hexagon::STriw_cPt;
1609
1610    case Hexagon::STriw_indexed_cPt:
1611      return Hexagon::STriw_indexed_cNotPt;
1612    case Hexagon::STriw_indexed_cNotPt:
1613      return Hexagon::STriw_indexed_cPt;
1614
1615    case Hexagon::STriw_indexed_shl_cPt_V4:
1616      return Hexagon::STriw_indexed_shl_cNotPt_V4;
1617    case Hexagon::STriw_indexed_shl_cNotPt_V4:
1618      return Hexagon::STriw_indexed_shl_cPt_V4;
1619
1620    case Hexagon::STriw_imm_cPt_V4:
1621      return Hexagon::STriw_imm_cNotPt_V4;
1622    case Hexagon::STriw_imm_cNotPt_V4:
1623      return Hexagon::STriw_imm_cPt_V4;
1624
1625  // Double word.
1626    case Hexagon::POST_STdri_cPt:
1627      return Hexagon::POST_STdri_cNotPt;
1628    case Hexagon::POST_STdri_cNotPt:
1629      return Hexagon::POST_STdri_cPt;
1630
1631    case Hexagon::STrid_cPt:
1632      return Hexagon::STrid_cNotPt;
1633    case Hexagon::STrid_cNotPt:
1634      return Hexagon::STrid_cPt;
1635
1636    case Hexagon::STrid_indexed_cPt:
1637      return Hexagon::STrid_indexed_cNotPt;
1638    case Hexagon::STrid_indexed_cNotPt:
1639      return Hexagon::STrid_indexed_cPt;
1640
1641    case Hexagon::STrid_indexed_shl_cPt_V4:
1642      return Hexagon::STrid_indexed_shl_cNotPt_V4;
1643    case Hexagon::STrid_indexed_shl_cNotPt_V4:
1644      return Hexagon::STrid_indexed_shl_cPt_V4;
1645
1646    // V4 Store to global address.
1647    case Hexagon::STd_GP_cPt_V4:
1648      return Hexagon::STd_GP_cNotPt_V4;
1649    case Hexagon::STd_GP_cNotPt_V4:
1650      return Hexagon::STd_GP_cPt_V4;
1651
1652    case Hexagon::STb_GP_cPt_V4:
1653      return Hexagon::STb_GP_cNotPt_V4;
1654    case Hexagon::STb_GP_cNotPt_V4:
1655      return Hexagon::STb_GP_cPt_V4;
1656
1657    case Hexagon::STh_GP_cPt_V4:
1658      return Hexagon::STh_GP_cNotPt_V4;
1659    case Hexagon::STh_GP_cNotPt_V4:
1660      return Hexagon::STh_GP_cPt_V4;
1661
1662    case Hexagon::STw_GP_cPt_V4:
1663      return Hexagon::STw_GP_cNotPt_V4;
1664    case Hexagon::STw_GP_cNotPt_V4:
1665      return Hexagon::STw_GP_cPt_V4;
1666
1667    case Hexagon::STrid_GP_cPt_V4:
1668      return Hexagon::STrid_GP_cNotPt_V4;
1669    case Hexagon::STrid_GP_cNotPt_V4:
1670      return Hexagon::STrid_GP_cPt_V4;
1671
1672    case Hexagon::STrib_GP_cPt_V4:
1673      return Hexagon::STrib_GP_cNotPt_V4;
1674    case Hexagon::STrib_GP_cNotPt_V4:
1675      return Hexagon::STrib_GP_cPt_V4;
1676
1677    case Hexagon::STrih_GP_cPt_V4:
1678      return Hexagon::STrih_GP_cNotPt_V4;
1679    case Hexagon::STrih_GP_cNotPt_V4:
1680      return Hexagon::STrih_GP_cPt_V4;
1681
1682    case Hexagon::STriw_GP_cPt_V4:
1683      return Hexagon::STriw_GP_cNotPt_V4;
1684    case Hexagon::STriw_GP_cNotPt_V4:
1685      return Hexagon::STriw_GP_cPt_V4;
1686
1687  // Load.
1688    case Hexagon::LDrid_cPt:
1689      return Hexagon::LDrid_cNotPt;
1690    case Hexagon::LDrid_cNotPt:
1691      return Hexagon::LDrid_cPt;
1692
1693    case Hexagon::LDriw_cPt:
1694      return Hexagon::LDriw_cNotPt;
1695    case Hexagon::LDriw_cNotPt:
1696      return Hexagon::LDriw_cPt;
1697
1698    case Hexagon::LDrih_cPt:
1699      return Hexagon::LDrih_cNotPt;
1700    case Hexagon::LDrih_cNotPt:
1701      return Hexagon::LDrih_cPt;
1702
1703    case Hexagon::LDriuh_cPt:
1704      return Hexagon::LDriuh_cNotPt;
1705    case Hexagon::LDriuh_cNotPt:
1706      return Hexagon::LDriuh_cPt;
1707
1708    case Hexagon::LDrib_cPt:
1709      return Hexagon::LDrib_cNotPt;
1710    case Hexagon::LDrib_cNotPt:
1711      return Hexagon::LDrib_cPt;
1712
1713    case Hexagon::LDriub_cPt:
1714      return Hexagon::LDriub_cNotPt;
1715    case Hexagon::LDriub_cNotPt:
1716      return Hexagon::LDriub_cPt;
1717
1718 // Load Indexed.
1719    case Hexagon::LDrid_indexed_cPt:
1720      return Hexagon::LDrid_indexed_cNotPt;
1721    case Hexagon::LDrid_indexed_cNotPt:
1722      return Hexagon::LDrid_indexed_cPt;
1723
1724    case Hexagon::LDriw_indexed_cPt:
1725      return Hexagon::LDriw_indexed_cNotPt;
1726    case Hexagon::LDriw_indexed_cNotPt:
1727      return Hexagon::LDriw_indexed_cPt;
1728
1729    case Hexagon::LDrih_indexed_cPt:
1730      return Hexagon::LDrih_indexed_cNotPt;
1731    case Hexagon::LDrih_indexed_cNotPt:
1732      return Hexagon::LDrih_indexed_cPt;
1733
1734    case Hexagon::LDriuh_indexed_cPt:
1735      return Hexagon::LDriuh_indexed_cNotPt;
1736    case Hexagon::LDriuh_indexed_cNotPt:
1737      return Hexagon::LDriuh_indexed_cPt;
1738
1739    case Hexagon::LDrib_indexed_cPt:
1740      return Hexagon::LDrib_indexed_cNotPt;
1741    case Hexagon::LDrib_indexed_cNotPt:
1742      return Hexagon::LDrib_indexed_cPt;
1743
1744    case Hexagon::LDriub_indexed_cPt:
1745      return Hexagon::LDriub_indexed_cNotPt;
1746    case Hexagon::LDriub_indexed_cNotPt:
1747      return Hexagon::LDriub_indexed_cPt;
1748
1749  // Post Inc Load.
1750    case Hexagon::POST_LDrid_cPt:
1751      return Hexagon::POST_LDrid_cNotPt;
1752    case Hexagon::POST_LDriw_cNotPt:
1753      return Hexagon::POST_LDriw_cPt;
1754
1755    case Hexagon::POST_LDrih_cPt:
1756      return Hexagon::POST_LDrih_cNotPt;
1757    case Hexagon::POST_LDrih_cNotPt:
1758      return Hexagon::POST_LDrih_cPt;
1759
1760    case Hexagon::POST_LDriuh_cPt:
1761      return Hexagon::POST_LDriuh_cNotPt;
1762    case Hexagon::POST_LDriuh_cNotPt:
1763      return Hexagon::POST_LDriuh_cPt;
1764
1765    case Hexagon::POST_LDrib_cPt:
1766      return Hexagon::POST_LDrib_cNotPt;
1767    case Hexagon::POST_LDrib_cNotPt:
1768      return Hexagon::POST_LDrib_cPt;
1769
1770    case Hexagon::POST_LDriub_cPt:
1771      return Hexagon::POST_LDriub_cNotPt;
1772    case Hexagon::POST_LDriub_cNotPt:
1773      return Hexagon::POST_LDriub_cPt;
1774
1775  // Dealloc_return.
1776    case Hexagon::DEALLOC_RET_cPt_V4:
1777      return Hexagon::DEALLOC_RET_cNotPt_V4;
1778    case Hexagon::DEALLOC_RET_cNotPt_V4:
1779      return Hexagon::DEALLOC_RET_cPt_V4;
1780
1781   // New Value Jump.
1782   // JMPEQ_ri - with -1.
1783    case Hexagon::JMP_EQriPtneg_nv_V4:
1784      return Hexagon::JMP_EQriNotPtneg_nv_V4;
1785    case Hexagon::JMP_EQriNotPtneg_nv_V4:
1786      return Hexagon::JMP_EQriPtneg_nv_V4;
1787
1788    case Hexagon::JMP_EQriPntneg_nv_V4:
1789      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1790    case Hexagon::JMP_EQriNotPntneg_nv_V4:
1791      return Hexagon::JMP_EQriPntneg_nv_V4;
1792
1793   // JMPEQ_ri.
1794     case Hexagon::JMP_EQriPt_nv_V4:
1795      return Hexagon::JMP_EQriNotPt_nv_V4;
1796    case Hexagon::JMP_EQriNotPt_nv_V4:
1797      return Hexagon::JMP_EQriPt_nv_V4;
1798
1799     case Hexagon::JMP_EQriPnt_nv_V4:
1800      return Hexagon::JMP_EQriNotPnt_nv_V4;
1801    case Hexagon::JMP_EQriNotPnt_nv_V4:
1802      return Hexagon::JMP_EQriPnt_nv_V4;
1803
1804   // JMPEQ_rr.
1805     case Hexagon::JMP_EQrrPt_nv_V4:
1806      return Hexagon::JMP_EQrrNotPt_nv_V4;
1807    case Hexagon::JMP_EQrrNotPt_nv_V4:
1808      return Hexagon::JMP_EQrrPt_nv_V4;
1809
1810     case Hexagon::JMP_EQrrPnt_nv_V4:
1811      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1812    case Hexagon::JMP_EQrrNotPnt_nv_V4:
1813      return Hexagon::JMP_EQrrPnt_nv_V4;
1814
1815   // JMPGT_ri - with -1.
1816    case Hexagon::JMP_GTriPtneg_nv_V4:
1817      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1818    case Hexagon::JMP_GTriNotPtneg_nv_V4:
1819      return Hexagon::JMP_GTriPtneg_nv_V4;
1820
1821    case Hexagon::JMP_GTriPntneg_nv_V4:
1822      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1823    case Hexagon::JMP_GTriNotPntneg_nv_V4:
1824      return Hexagon::JMP_GTriPntneg_nv_V4;
1825
1826   // JMPGT_ri.
1827     case Hexagon::JMP_GTriPt_nv_V4:
1828      return Hexagon::JMP_GTriNotPt_nv_V4;
1829    case Hexagon::JMP_GTriNotPt_nv_V4:
1830      return Hexagon::JMP_GTriPt_nv_V4;
1831
1832     case Hexagon::JMP_GTriPnt_nv_V4:
1833      return Hexagon::JMP_GTriNotPnt_nv_V4;
1834    case Hexagon::JMP_GTriNotPnt_nv_V4:
1835      return Hexagon::JMP_GTriPnt_nv_V4;
1836
1837   // JMPGT_rr.
1838     case Hexagon::JMP_GTrrPt_nv_V4:
1839      return Hexagon::JMP_GTrrNotPt_nv_V4;
1840    case Hexagon::JMP_GTrrNotPt_nv_V4:
1841      return Hexagon::JMP_GTrrPt_nv_V4;
1842
1843     case Hexagon::JMP_GTrrPnt_nv_V4:
1844      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1845    case Hexagon::JMP_GTrrNotPnt_nv_V4:
1846      return Hexagon::JMP_GTrrPnt_nv_V4;
1847
1848   // JMPGT_rrdn.
1849     case Hexagon::JMP_GTrrdnPt_nv_V4:
1850      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1851    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1852      return Hexagon::JMP_GTrrdnPt_nv_V4;
1853
1854     case Hexagon::JMP_GTrrdnPnt_nv_V4:
1855      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1856    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1857      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1858
1859   // JMPGTU_ri.
1860     case Hexagon::JMP_GTUriPt_nv_V4:
1861      return Hexagon::JMP_GTUriNotPt_nv_V4;
1862    case Hexagon::JMP_GTUriNotPt_nv_V4:
1863      return Hexagon::JMP_GTUriPt_nv_V4;
1864
1865     case Hexagon::JMP_GTUriPnt_nv_V4:
1866      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1867    case Hexagon::JMP_GTUriNotPnt_nv_V4:
1868      return Hexagon::JMP_GTUriPnt_nv_V4;
1869
1870   // JMPGTU_rr.
1871     case Hexagon::JMP_GTUrrPt_nv_V4:
1872      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1873    case Hexagon::JMP_GTUrrNotPt_nv_V4:
1874      return Hexagon::JMP_GTUrrPt_nv_V4;
1875
1876     case Hexagon::JMP_GTUrrPnt_nv_V4:
1877      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1878    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1879      return Hexagon::JMP_GTUrrPnt_nv_V4;
1880
1881   // JMPGTU_rrdn.
1882     case Hexagon::JMP_GTUrrdnPt_nv_V4:
1883      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1884    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1885      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1886
1887     case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1888      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1889    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1890      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1891  }
1892}
1893
1894
1895int HexagonInstrInfo::
1896getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1897  switch(Opc) {
1898  case Hexagon::TFR:
1899    return !invertPredicate ? Hexagon::TFR_cPt :
1900                              Hexagon::TFR_cNotPt;
1901  case Hexagon::TFRI_f:
1902    return !invertPredicate ? Hexagon::TFRI_cPt_f :
1903                              Hexagon::TFRI_cNotPt_f;
1904  case Hexagon::TFRI:
1905    return !invertPredicate ? Hexagon::TFRI_cPt :
1906                              Hexagon::TFRI_cNotPt;
1907  case Hexagon::JMP:
1908    return !invertPredicate ? Hexagon::JMP_c :
1909                              Hexagon::JMP_cNot;
1910  case Hexagon::ADD_ri:
1911    return !invertPredicate ? Hexagon::ADD_ri_cPt :
1912                              Hexagon::ADD_ri_cNotPt;
1913  case Hexagon::ADD_rr:
1914    return !invertPredicate ? Hexagon::ADD_rr_cPt :
1915                              Hexagon::ADD_rr_cNotPt;
1916  case Hexagon::XOR_rr:
1917    return !invertPredicate ? Hexagon::XOR_rr_cPt :
1918                              Hexagon::XOR_rr_cNotPt;
1919  case Hexagon::AND_rr:
1920    return !invertPredicate ? Hexagon::AND_rr_cPt :
1921                              Hexagon::AND_rr_cNotPt;
1922  case Hexagon::OR_rr:
1923    return !invertPredicate ? Hexagon::OR_rr_cPt :
1924                              Hexagon::OR_rr_cNotPt;
1925  case Hexagon::SUB_rr:
1926    return !invertPredicate ? Hexagon::SUB_rr_cPt :
1927                              Hexagon::SUB_rr_cNotPt;
1928  case Hexagon::COMBINE_rr:
1929    return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1930                              Hexagon::COMBINE_rr_cNotPt;
1931  case Hexagon::ASLH:
1932    return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1933                              Hexagon::ASLH_cNotPt_V4;
1934  case Hexagon::ASRH:
1935    return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1936                              Hexagon::ASRH_cNotPt_V4;
1937  case Hexagon::SXTB:
1938    return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1939                              Hexagon::SXTB_cNotPt_V4;
1940  case Hexagon::SXTH:
1941    return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1942                              Hexagon::SXTH_cNotPt_V4;
1943  case Hexagon::ZXTB:
1944    return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1945                              Hexagon::ZXTB_cNotPt_V4;
1946  case Hexagon::ZXTH:
1947    return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1948                              Hexagon::ZXTH_cNotPt_V4;
1949
1950  case Hexagon::JMPR:
1951    return !invertPredicate ? Hexagon::JMPR_cPt :
1952                              Hexagon::JMPR_cNotPt;
1953
1954  // V4 indexed+scaled load.
1955  case Hexagon::LDrid_indexed_V4:
1956    return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
1957                              Hexagon::LDrid_indexed_cNotPt_V4;
1958  case Hexagon::LDrid_indexed_shl_V4:
1959    return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1960                              Hexagon::LDrid_indexed_shl_cNotPt_V4;
1961  case Hexagon::LDrib_indexed_V4:
1962    return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
1963                              Hexagon::LDrib_indexed_cNotPt_V4;
1964  case Hexagon::LDriub_indexed_V4:
1965    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1966                              Hexagon::LDriub_indexed_cNotPt_V4;
1967  case Hexagon::LDriub_ae_indexed_V4:
1968    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1969                              Hexagon::LDriub_indexed_cNotPt_V4;
1970  case Hexagon::LDrib_indexed_shl_V4:
1971    return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1972                              Hexagon::LDrib_indexed_shl_cNotPt_V4;
1973  case Hexagon::LDriub_indexed_shl_V4:
1974    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1975                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1976  case Hexagon::LDriub_ae_indexed_shl_V4:
1977    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1978                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1979  case Hexagon::LDrih_indexed_V4:
1980    return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
1981                              Hexagon::LDrih_indexed_cNotPt_V4;
1982  case Hexagon::LDriuh_indexed_V4:
1983    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1984                              Hexagon::LDriuh_indexed_cNotPt_V4;
1985  case Hexagon::LDriuh_ae_indexed_V4:
1986    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1987                              Hexagon::LDriuh_indexed_cNotPt_V4;
1988  case Hexagon::LDrih_indexed_shl_V4:
1989    return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1990                              Hexagon::LDrih_indexed_shl_cNotPt_V4;
1991  case Hexagon::LDriuh_indexed_shl_V4:
1992    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1993                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1994  case Hexagon::LDriuh_ae_indexed_shl_V4:
1995    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1996                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1997  case Hexagon::LDriw_indexed_V4:
1998    return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
1999                              Hexagon::LDriw_indexed_cNotPt_V4;
2000  case Hexagon::LDriw_indexed_shl_V4:
2001    return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
2002                              Hexagon::LDriw_indexed_shl_cNotPt_V4;
2003
2004  // V4 Load from global address
2005  case Hexagon::LDrid_GP_V4:
2006    return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 :
2007                              Hexagon::LDrid_GP_cNotPt_V4;
2008  case Hexagon::LDrib_GP_V4:
2009    return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 :
2010                              Hexagon::LDrib_GP_cNotPt_V4;
2011  case Hexagon::LDriub_GP_V4:
2012    return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 :
2013                              Hexagon::LDriub_GP_cNotPt_V4;
2014  case Hexagon::LDrih_GP_V4:
2015    return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 :
2016                              Hexagon::LDrih_GP_cNotPt_V4;
2017  case Hexagon::LDriuh_GP_V4:
2018    return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 :
2019                              Hexagon::LDriuh_GP_cNotPt_V4;
2020  case Hexagon::LDriw_GP_V4:
2021    return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 :
2022                              Hexagon::LDriw_GP_cNotPt_V4;
2023
2024  case Hexagon::LDd_GP_V4:
2025    return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
2026                              Hexagon::LDd_GP_cNotPt_V4;
2027  case Hexagon::LDb_GP_V4:
2028    return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
2029                              Hexagon::LDb_GP_cNotPt_V4;
2030  case Hexagon::LDub_GP_V4:
2031    return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
2032                              Hexagon::LDub_GP_cNotPt_V4;
2033  case Hexagon::LDh_GP_V4:
2034    return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
2035                              Hexagon::LDh_GP_cNotPt_V4;
2036  case Hexagon::LDuh_GP_V4:
2037    return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
2038                              Hexagon::LDuh_GP_cNotPt_V4;
2039  case Hexagon::LDw_GP_V4:
2040    return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
2041                              Hexagon::LDw_GP_cNotPt_V4;
2042
2043    // Byte.
2044  case Hexagon::POST_STbri:
2045    return !invertPredicate ? Hexagon::POST_STbri_cPt :
2046                              Hexagon::POST_STbri_cNotPt;
2047  case Hexagon::STrib:
2048    return !invertPredicate ? Hexagon::STrib_cPt :
2049                              Hexagon::STrib_cNotPt;
2050  case Hexagon::STrib_indexed:
2051    return !invertPredicate ? Hexagon::STrib_indexed_cPt :
2052                              Hexagon::STrib_indexed_cNotPt;
2053  case Hexagon::STrib_imm_V4:
2054    return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
2055                              Hexagon::STrib_imm_cNotPt_V4;
2056  case Hexagon::STrib_indexed_shl_V4:
2057    return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
2058                              Hexagon::STrib_indexed_shl_cNotPt_V4;
2059  // Halfword.
2060  case Hexagon::POST_SThri:
2061    return !invertPredicate ? Hexagon::POST_SThri_cPt :
2062                              Hexagon::POST_SThri_cNotPt;
2063  case Hexagon::STrih:
2064    return !invertPredicate ? Hexagon::STrih_cPt :
2065                              Hexagon::STrih_cNotPt;
2066  case Hexagon::STrih_indexed:
2067    return !invertPredicate ? Hexagon::STrih_indexed_cPt :
2068                              Hexagon::STrih_indexed_cNotPt;
2069  case Hexagon::STrih_imm_V4:
2070    return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
2071                              Hexagon::STrih_imm_cNotPt_V4;
2072  case Hexagon::STrih_indexed_shl_V4:
2073    return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
2074                              Hexagon::STrih_indexed_shl_cNotPt_V4;
2075  // Word.
2076  case Hexagon::POST_STwri:
2077    return !invertPredicate ? Hexagon::POST_STwri_cPt :
2078                              Hexagon::POST_STwri_cNotPt;
2079  case Hexagon::STriw:
2080    return !invertPredicate ? Hexagon::STriw_cPt :
2081                              Hexagon::STriw_cNotPt;
2082  case Hexagon::STriw_indexed:
2083    return !invertPredicate ? Hexagon::STriw_indexed_cPt :
2084                              Hexagon::STriw_indexed_cNotPt;
2085  case Hexagon::STriw_indexed_shl_V4:
2086    return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
2087                              Hexagon::STriw_indexed_shl_cNotPt_V4;
2088  case Hexagon::STriw_imm_V4:
2089    return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
2090                              Hexagon::STriw_imm_cNotPt_V4;
2091  // Double word.
2092  case Hexagon::POST_STdri:
2093    return !invertPredicate ? Hexagon::POST_STdri_cPt :
2094                              Hexagon::POST_STdri_cNotPt;
2095  case Hexagon::STrid:
2096    return !invertPredicate ? Hexagon::STrid_cPt :
2097                              Hexagon::STrid_cNotPt;
2098  case Hexagon::STrid_indexed:
2099    return !invertPredicate ? Hexagon::STrid_indexed_cPt :
2100                              Hexagon::STrid_indexed_cNotPt;
2101  case Hexagon::STrid_indexed_shl_V4:
2102    return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
2103                              Hexagon::STrid_indexed_shl_cNotPt_V4;
2104
2105  // V4 Store to global address
2106  case Hexagon::STrid_GP_V4:
2107    return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 :
2108                              Hexagon::STrid_GP_cNotPt_V4;
2109  case Hexagon::STrib_GP_V4:
2110    return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 :
2111                              Hexagon::STrib_GP_cNotPt_V4;
2112  case Hexagon::STrih_GP_V4:
2113    return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 :
2114                              Hexagon::STrih_GP_cNotPt_V4;
2115  case Hexagon::STriw_GP_V4:
2116    return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 :
2117                              Hexagon::STriw_GP_cNotPt_V4;
2118
2119  case Hexagon::STd_GP_V4:
2120    return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
2121                              Hexagon::STd_GP_cNotPt_V4;
2122  case Hexagon::STb_GP_V4:
2123    return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
2124                              Hexagon::STb_GP_cNotPt_V4;
2125  case Hexagon::STh_GP_V4:
2126    return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
2127                              Hexagon::STh_GP_cNotPt_V4;
2128  case Hexagon::STw_GP_V4:
2129    return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
2130                              Hexagon::STw_GP_cNotPt_V4;
2131
2132  // Load.
2133  case Hexagon::LDrid:
2134    return !invertPredicate ? Hexagon::LDrid_cPt :
2135                              Hexagon::LDrid_cNotPt;
2136  case Hexagon::LDriw:
2137    return !invertPredicate ? Hexagon::LDriw_cPt :
2138                              Hexagon::LDriw_cNotPt;
2139  case Hexagon::LDrih:
2140    return !invertPredicate ? Hexagon::LDrih_cPt :
2141                              Hexagon::LDrih_cNotPt;
2142  case Hexagon::LDriuh:
2143    return !invertPredicate ? Hexagon::LDriuh_cPt :
2144                              Hexagon::LDriuh_cNotPt;
2145  case Hexagon::LDrib:
2146    return !invertPredicate ? Hexagon::LDrib_cPt :
2147                              Hexagon::LDrib_cNotPt;
2148  case Hexagon::LDriub:
2149    return !invertPredicate ? Hexagon::LDriub_cPt :
2150                              Hexagon::LDriub_cNotPt;
2151 // Load Indexed.
2152  case Hexagon::LDrid_indexed:
2153    return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
2154                              Hexagon::LDrid_indexed_cNotPt;
2155  case Hexagon::LDriw_indexed:
2156    return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
2157                              Hexagon::LDriw_indexed_cNotPt;
2158  case Hexagon::LDrih_indexed:
2159    return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
2160                              Hexagon::LDrih_indexed_cNotPt;
2161  case Hexagon::LDriuh_indexed:
2162    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
2163                              Hexagon::LDriuh_indexed_cNotPt;
2164  case Hexagon::LDrib_indexed:
2165    return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
2166                              Hexagon::LDrib_indexed_cNotPt;
2167  case Hexagon::LDriub_indexed:
2168    return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
2169                              Hexagon::LDriub_indexed_cNotPt;
2170  // Post Increment Load.
2171  case Hexagon::POST_LDrid:
2172    return !invertPredicate ? Hexagon::POST_LDrid_cPt :
2173                              Hexagon::POST_LDrid_cNotPt;
2174  case Hexagon::POST_LDriw:
2175    return !invertPredicate ? Hexagon::POST_LDriw_cPt :
2176                              Hexagon::POST_LDriw_cNotPt;
2177  case Hexagon::POST_LDrih:
2178    return !invertPredicate ? Hexagon::POST_LDrih_cPt :
2179                              Hexagon::POST_LDrih_cNotPt;
2180  case Hexagon::POST_LDriuh:
2181    return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
2182                              Hexagon::POST_LDriuh_cNotPt;
2183  case Hexagon::POST_LDrib:
2184    return !invertPredicate ? Hexagon::POST_LDrib_cPt :
2185                              Hexagon::POST_LDrib_cNotPt;
2186  case Hexagon::POST_LDriub:
2187    return !invertPredicate ? Hexagon::POST_LDriub_cPt :
2188                              Hexagon::POST_LDriub_cNotPt;
2189  // DEALLOC_RETURN.
2190  case Hexagon::DEALLOC_RET_V4:
2191    return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
2192                              Hexagon::DEALLOC_RET_cNotPt_V4;
2193  }
2194  llvm_unreachable("Unexpected predicable instruction");
2195}
2196
2197
2198bool HexagonInstrInfo::
2199PredicateInstruction(MachineInstr *MI,
2200                     const SmallVectorImpl<MachineOperand> &Cond) const {
2201  int Opc = MI->getOpcode();
2202  assert (isPredicable(MI) && "Expected predicable instruction");
2203  bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
2204                     (Cond[0].getImm() == 0));
2205  MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
2206  //
2207  // This assumes that the predicate is always the first operand
2208  // in the set of inputs.
2209  //
2210  MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
2211  int oper;
2212  for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
2213    MachineOperand MO = MI->getOperand(oper);
2214    if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
2215      break;
2216    }
2217
2218    if (MO.isReg()) {
2219      MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
2220                                              MO.isImplicit(), MO.isKill(),
2221                                              MO.isDead(), MO.isUndef(),
2222                                              MO.isDebug());
2223    } else if (MO.isImm()) {
2224      MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
2225    } else {
2226      llvm_unreachable("Unexpected operand type");
2227    }
2228  }
2229
2230  int regPos = invertJump ? 1 : 0;
2231  MachineOperand PredMO = Cond[regPos];
2232  MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
2233                                          PredMO.isImplicit(), PredMO.isKill(),
2234                                          PredMO.isDead(), PredMO.isUndef(),
2235                                          PredMO.isDebug());
2236
2237  return true;
2238}
2239
2240
2241bool
2242HexagonInstrInfo::
2243isProfitableToIfCvt(MachineBasicBlock &MBB,
2244                    unsigned NumCyles,
2245                    unsigned ExtraPredCycles,
2246                    const BranchProbability &Probability) const {
2247  return true;
2248}
2249
2250
2251bool
2252HexagonInstrInfo::
2253isProfitableToIfCvt(MachineBasicBlock &TMBB,
2254                    unsigned NumTCycles,
2255                    unsigned ExtraTCycles,
2256                    MachineBasicBlock &FMBB,
2257                    unsigned NumFCycles,
2258                    unsigned ExtraFCycles,
2259                    const BranchProbability &Probability) const {
2260  return true;
2261}
2262
2263
2264bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
2265  const uint64_t F = MI->getDesc().TSFlags;
2266
2267  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2268}
2269
2270bool
2271HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
2272                                   std::vector<MachineOperand> &Pred) const {
2273  for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
2274    MachineOperand MO = MI->getOperand(oper);
2275    if (MO.isReg() && MO.isDef()) {
2276      const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
2277      if (RC == &Hexagon::PredRegsRegClass) {
2278        Pred.push_back(MO);
2279        return true;
2280      }
2281    }
2282  }
2283  return false;
2284}
2285
2286
2287bool
2288HexagonInstrInfo::
2289SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
2290                  const SmallVectorImpl<MachineOperand> &Pred2) const {
2291  // TODO: Fix this
2292  return false;
2293}
2294
2295
2296//
2297// We indicate that we want to reverse the branch by
2298// inserting a 0 at the beginning of the Cond vector.
2299//
2300bool HexagonInstrInfo::
2301ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2302  if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
2303    Cond.erase(Cond.begin());
2304  } else {
2305    Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
2306  }
2307  return false;
2308}
2309
2310
2311bool HexagonInstrInfo::
2312isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
2313                          const BranchProbability &Probability) const {
2314  return (NumInstrs <= 4);
2315}
2316
2317bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
2318  switch (MI->getOpcode()) {
2319  default: return false;
2320  case Hexagon::DEALLOC_RET_V4 :
2321  case Hexagon::DEALLOC_RET_cPt_V4 :
2322  case Hexagon::DEALLOC_RET_cNotPt_V4 :
2323  case Hexagon::DEALLOC_RET_cdnPnt_V4 :
2324  case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
2325  case Hexagon::DEALLOC_RET_cdnPt_V4 :
2326  case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
2327   return true;
2328  }
2329}
2330
2331
2332bool HexagonInstrInfo::
2333isValidOffset(const int Opcode, const int Offset) const {
2334  // This function is to check whether the "Offset" is in the correct range of
2335  // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
2336  // inserted to calculate the final address. Due to this reason, the function
2337  // assumes that the "Offset" has correct alignment.
2338
2339  switch(Opcode) {
2340
2341  case Hexagon::LDriw:
2342  case Hexagon::LDriw_f:
2343  case Hexagon::STriw:
2344  case Hexagon::STriw_f:
2345    assert((Offset % 4 == 0) && "Offset has incorrect alignment");
2346    return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2347      (Offset <= Hexagon_MEMW_OFFSET_MAX);
2348
2349  case Hexagon::LDrid:
2350  case Hexagon::LDrid_f:
2351  case Hexagon::STrid:
2352  case Hexagon::STrid_f:
2353    assert((Offset % 8 == 0) && "Offset has incorrect alignment");
2354    return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2355      (Offset <= Hexagon_MEMD_OFFSET_MAX);
2356
2357  case Hexagon::LDrih:
2358  case Hexagon::LDriuh:
2359  case Hexagon::STrih:
2360    assert((Offset % 2 == 0) && "Offset has incorrect alignment");
2361    return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2362      (Offset <= Hexagon_MEMH_OFFSET_MAX);
2363
2364  case Hexagon::LDrib:
2365  case Hexagon::STrib:
2366  case Hexagon::LDriub:
2367    return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2368      (Offset <= Hexagon_MEMB_OFFSET_MAX);
2369
2370  case Hexagon::ADD_ri:
2371  case Hexagon::TFR_FI:
2372    return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2373      (Offset <= Hexagon_ADDI_OFFSET_MAX);
2374
2375  case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2376  case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2377  case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2378  case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2379  case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2380  case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2381  case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2382  case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2383  case Hexagon::MEMw_ADDi_MEM_V4 :
2384  case Hexagon::MEMw_SUBi_MEM_V4 :
2385  case Hexagon::MEMw_ADDr_MEM_V4 :
2386  case Hexagon::MEMw_SUBr_MEM_V4 :
2387  case Hexagon::MEMw_ANDr_MEM_V4 :
2388  case Hexagon::MEMw_ORr_MEM_V4 :
2389    assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
2390    return (0 <= Offset && Offset <= 255);
2391
2392  case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2393  case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2394  case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2395  case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2396  case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2397  case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2398  case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2399  case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2400  case Hexagon::MEMh_ADDi_MEM_V4 :
2401  case Hexagon::MEMh_SUBi_MEM_V4 :
2402  case Hexagon::MEMh_ADDr_MEM_V4 :
2403  case Hexagon::MEMh_SUBr_MEM_V4 :
2404  case Hexagon::MEMh_ANDr_MEM_V4 :
2405  case Hexagon::MEMh_ORr_MEM_V4 :
2406    assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
2407    return (0 <= Offset && Offset <= 127);
2408
2409  case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2410  case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2411  case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2412  case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2413  case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2414  case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2415  case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2416  case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2417  case Hexagon::MEMb_ADDi_MEM_V4 :
2418  case Hexagon::MEMb_SUBi_MEM_V4 :
2419  case Hexagon::MEMb_ADDr_MEM_V4 :
2420  case Hexagon::MEMb_SUBr_MEM_V4 :
2421  case Hexagon::MEMb_ANDr_MEM_V4 :
2422  case Hexagon::MEMb_ORr_MEM_V4 :
2423    return (0 <= Offset && Offset <= 63);
2424
2425  // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2426  // any size. Later pass knows how to handle it.
2427  case Hexagon::STriw_pred:
2428  case Hexagon::LDriw_pred:
2429    return true;
2430
2431  // INLINEASM is very special.
2432  case Hexagon::INLINEASM:
2433    return true;
2434  }
2435
2436  llvm_unreachable("No offset range is defined for this opcode. "
2437                   "Please define it in the above switch statement!");
2438}
2439
2440
2441//
2442// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2443//
2444bool HexagonInstrInfo::
2445isValidAutoIncImm(const EVT VT, const int Offset) const {
2446
2447  if (VT == MVT::i64) {
2448      return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2449              Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2450              (Offset & 0x7) == 0);
2451  }
2452  if (VT == MVT::i32) {
2453      return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2454              Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2455              (Offset & 0x3) == 0);
2456  }
2457  if (VT == MVT::i16) {
2458      return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2459              Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2460              (Offset & 0x1) == 0);
2461  }
2462  if (VT == MVT::i8) {
2463      return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2464              Offset <= Hexagon_MEMB_AUTOINC_MAX);
2465  }
2466  llvm_unreachable("Not an auto-inc opc!");
2467}
2468
2469
2470bool HexagonInstrInfo::
2471isMemOp(const MachineInstr *MI) const {
2472  switch (MI->getOpcode())
2473  {
2474    default: return false;
2475    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2476    case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2477    case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2478    case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2479    case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2480    case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2481    case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2482    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2483    case Hexagon::MEMw_ADDi_MEM_V4 :
2484    case Hexagon::MEMw_SUBi_MEM_V4 :
2485    case Hexagon::MEMw_ADDr_MEM_V4 :
2486    case Hexagon::MEMw_SUBr_MEM_V4 :
2487    case Hexagon::MEMw_ANDr_MEM_V4 :
2488    case Hexagon::MEMw_ORr_MEM_V4 :
2489    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2490    case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2491    case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2492    case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2493    case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2494    case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2495    case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2496    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2497    case Hexagon::MEMh_ADDi_MEM_V4 :
2498    case Hexagon::MEMh_SUBi_MEM_V4 :
2499    case Hexagon::MEMh_ADDr_MEM_V4 :
2500    case Hexagon::MEMh_SUBr_MEM_V4 :
2501    case Hexagon::MEMh_ANDr_MEM_V4 :
2502    case Hexagon::MEMh_ORr_MEM_V4 :
2503    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2504    case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2505    case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2506    case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2507    case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2508    case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2509    case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2510    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2511    case Hexagon::MEMb_ADDi_MEM_V4 :
2512    case Hexagon::MEMb_SUBi_MEM_V4 :
2513    case Hexagon::MEMb_ADDr_MEM_V4 :
2514    case Hexagon::MEMb_SUBr_MEM_V4 :
2515    case Hexagon::MEMb_ANDr_MEM_V4 :
2516    case Hexagon::MEMb_ORr_MEM_V4 :
2517      return true;
2518  }
2519}
2520
2521
2522bool HexagonInstrInfo::
2523isSpillPredRegOp(const MachineInstr *MI) const {
2524  switch (MI->getOpcode()) {
2525    default: return false;
2526    case Hexagon::STriw_pred :
2527    case Hexagon::LDriw_pred :
2528      return true;
2529  }
2530  return false;
2531}
2532
2533bool HexagonInstrInfo::
2534isConditionalTransfer (const MachineInstr *MI) const {
2535  switch (MI->getOpcode()) {
2536    default: return false;
2537    case Hexagon::TFR_cPt:
2538    case Hexagon::TFR_cNotPt:
2539    case Hexagon::TFRI_cPt:
2540    case Hexagon::TFRI_cNotPt:
2541    case Hexagon::TFR_cdnPt:
2542    case Hexagon::TFR_cdnNotPt:
2543    case Hexagon::TFRI_cdnPt:
2544    case Hexagon::TFRI_cdnNotPt:
2545      return true;
2546  }
2547}
2548
2549bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2550  const HexagonRegisterInfo& QRI = getRegisterInfo();
2551  switch (MI->getOpcode())
2552  {
2553    default: return false;
2554    case Hexagon::ADD_ri_cPt:
2555    case Hexagon::ADD_ri_cNotPt:
2556    case Hexagon::ADD_rr_cPt:
2557    case Hexagon::ADD_rr_cNotPt:
2558    case Hexagon::XOR_rr_cPt:
2559    case Hexagon::XOR_rr_cNotPt:
2560    case Hexagon::AND_rr_cPt:
2561    case Hexagon::AND_rr_cNotPt:
2562    case Hexagon::OR_rr_cPt:
2563    case Hexagon::OR_rr_cNotPt:
2564    case Hexagon::SUB_rr_cPt:
2565    case Hexagon::SUB_rr_cNotPt:
2566    case Hexagon::COMBINE_rr_cPt:
2567    case Hexagon::COMBINE_rr_cNotPt:
2568      return true;
2569    case Hexagon::ASLH_cPt_V4:
2570    case Hexagon::ASLH_cNotPt_V4:
2571    case Hexagon::ASRH_cPt_V4:
2572    case Hexagon::ASRH_cNotPt_V4:
2573    case Hexagon::SXTB_cPt_V4:
2574    case Hexagon::SXTB_cNotPt_V4:
2575    case Hexagon::SXTH_cPt_V4:
2576    case Hexagon::SXTH_cNotPt_V4:
2577    case Hexagon::ZXTB_cPt_V4:
2578    case Hexagon::ZXTB_cNotPt_V4:
2579    case Hexagon::ZXTH_cPt_V4:
2580    case Hexagon::ZXTH_cNotPt_V4:
2581      return QRI.Subtarget.hasV4TOps();
2582  }
2583}
2584
2585bool HexagonInstrInfo::
2586isConditionalLoad (const MachineInstr* MI) const {
2587  const HexagonRegisterInfo& QRI = getRegisterInfo();
2588  switch (MI->getOpcode())
2589  {
2590    default: return false;
2591    case Hexagon::LDrid_cPt :
2592    case Hexagon::LDrid_cNotPt :
2593    case Hexagon::LDrid_indexed_cPt :
2594    case Hexagon::LDrid_indexed_cNotPt :
2595    case Hexagon::LDriw_cPt :
2596    case Hexagon::LDriw_cNotPt :
2597    case Hexagon::LDriw_indexed_cPt :
2598    case Hexagon::LDriw_indexed_cNotPt :
2599    case Hexagon::LDrih_cPt :
2600    case Hexagon::LDrih_cNotPt :
2601    case Hexagon::LDrih_indexed_cPt :
2602    case Hexagon::LDrih_indexed_cNotPt :
2603    case Hexagon::LDrib_cPt :
2604    case Hexagon::LDrib_cNotPt :
2605    case Hexagon::LDrib_indexed_cPt :
2606    case Hexagon::LDrib_indexed_cNotPt :
2607    case Hexagon::LDriuh_cPt :
2608    case Hexagon::LDriuh_cNotPt :
2609    case Hexagon::LDriuh_indexed_cPt :
2610    case Hexagon::LDriuh_indexed_cNotPt :
2611    case Hexagon::LDriub_cPt :
2612    case Hexagon::LDriub_cNotPt :
2613    case Hexagon::LDriub_indexed_cPt :
2614    case Hexagon::LDriub_indexed_cNotPt :
2615      return true;
2616    case Hexagon::POST_LDrid_cPt :
2617    case Hexagon::POST_LDrid_cNotPt :
2618    case Hexagon::POST_LDriw_cPt :
2619    case Hexagon::POST_LDriw_cNotPt :
2620    case Hexagon::POST_LDrih_cPt :
2621    case Hexagon::POST_LDrih_cNotPt :
2622    case Hexagon::POST_LDrib_cPt :
2623    case Hexagon::POST_LDrib_cNotPt :
2624    case Hexagon::POST_LDriuh_cPt :
2625    case Hexagon::POST_LDriuh_cNotPt :
2626    case Hexagon::POST_LDriub_cPt :
2627    case Hexagon::POST_LDriub_cNotPt :
2628      return QRI.Subtarget.hasV4TOps();
2629    case Hexagon::LDrid_indexed_cPt_V4 :
2630    case Hexagon::LDrid_indexed_cNotPt_V4 :
2631    case Hexagon::LDrid_indexed_shl_cPt_V4 :
2632    case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2633    case Hexagon::LDrib_indexed_cPt_V4 :
2634    case Hexagon::LDrib_indexed_cNotPt_V4 :
2635    case Hexagon::LDrib_indexed_shl_cPt_V4 :
2636    case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2637    case Hexagon::LDriub_indexed_cPt_V4 :
2638    case Hexagon::LDriub_indexed_cNotPt_V4 :
2639    case Hexagon::LDriub_indexed_shl_cPt_V4 :
2640    case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2641    case Hexagon::LDrih_indexed_cPt_V4 :
2642    case Hexagon::LDrih_indexed_cNotPt_V4 :
2643    case Hexagon::LDrih_indexed_shl_cPt_V4 :
2644    case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2645    case Hexagon::LDriuh_indexed_cPt_V4 :
2646    case Hexagon::LDriuh_indexed_cNotPt_V4 :
2647    case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2648    case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2649    case Hexagon::LDriw_indexed_cPt_V4 :
2650    case Hexagon::LDriw_indexed_cNotPt_V4 :
2651    case Hexagon::LDriw_indexed_shl_cPt_V4 :
2652    case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2653      return QRI.Subtarget.hasV4TOps();
2654  }
2655}
2656
2657// Returns true if an instruction is a conditional store.
2658//
2659// Note: It doesn't include conditional new-value stores as they can't be
2660// converted to .new predicate.
2661//
2662//               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2663//                ^           ^
2664//               /             \ (not OK. it will cause new-value store to be
2665//              /               X conditional on p0.new while R2 producer is
2666//             /                 \ on p0)
2667//            /                   \.
2668//     p.new store                 p.old NV store
2669// [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
2670//            ^                  ^
2671//             \                /
2672//              \              /
2673//               \            /
2674//                 p.old store
2675//             [if (p0)memw(R0+#0)=R2]
2676//
2677// The above diagram shows the steps involoved in the conversion of a predicated
2678// store instruction to its .new predicated new-value form.
2679//
2680// The following set of instructions further explains the scenario where
2681// conditional new-value store becomes invalid when promoted to .new predicate
2682// form.
2683//
2684// { 1) if (p0) r0 = add(r1, r2)
2685//   2) p0 = cmp.eq(r3, #0) }
2686//
2687//   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
2688// the first two instructions because in instr 1, r0 is conditional on old value
2689// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2690// is not valid for new-value stores.
2691bool HexagonInstrInfo::
2692isConditionalStore (const MachineInstr* MI) const {
2693  const HexagonRegisterInfo& QRI = getRegisterInfo();
2694  switch (MI->getOpcode())
2695  {
2696    default: return false;
2697    case Hexagon::STrib_imm_cPt_V4 :
2698    case Hexagon::STrib_imm_cNotPt_V4 :
2699    case Hexagon::STrib_indexed_shl_cPt_V4 :
2700    case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2701    case Hexagon::STrib_cPt :
2702    case Hexagon::STrib_cNotPt :
2703    case Hexagon::POST_STbri_cPt :
2704    case Hexagon::POST_STbri_cNotPt :
2705    case Hexagon::STrid_indexed_cPt :
2706    case Hexagon::STrid_indexed_cNotPt :
2707    case Hexagon::STrid_indexed_shl_cPt_V4 :
2708    case Hexagon::POST_STdri_cPt :
2709    case Hexagon::POST_STdri_cNotPt :
2710    case Hexagon::STrih_cPt :
2711    case Hexagon::STrih_cNotPt :
2712    case Hexagon::STrih_indexed_cPt :
2713    case Hexagon::STrih_indexed_cNotPt :
2714    case Hexagon::STrih_imm_cPt_V4 :
2715    case Hexagon::STrih_imm_cNotPt_V4 :
2716    case Hexagon::STrih_indexed_shl_cPt_V4 :
2717    case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2718    case Hexagon::POST_SThri_cPt :
2719    case Hexagon::POST_SThri_cNotPt :
2720    case Hexagon::STriw_cPt :
2721    case Hexagon::STriw_cNotPt :
2722    case Hexagon::STriw_indexed_cPt :
2723    case Hexagon::STriw_indexed_cNotPt :
2724    case Hexagon::STriw_imm_cPt_V4 :
2725    case Hexagon::STriw_imm_cNotPt_V4 :
2726    case Hexagon::STriw_indexed_shl_cPt_V4 :
2727    case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2728    case Hexagon::POST_STwri_cPt :
2729    case Hexagon::POST_STwri_cNotPt :
2730      return QRI.Subtarget.hasV4TOps();
2731
2732    // V4 global address store before promoting to dot new.
2733    case Hexagon::STrid_GP_cPt_V4 :
2734    case Hexagon::STrid_GP_cNotPt_V4 :
2735    case Hexagon::STrib_GP_cPt_V4 :
2736    case Hexagon::STrib_GP_cNotPt_V4 :
2737    case Hexagon::STrih_GP_cPt_V4 :
2738    case Hexagon::STrih_GP_cNotPt_V4 :
2739    case Hexagon::STriw_GP_cPt_V4 :
2740    case Hexagon::STriw_GP_cNotPt_V4 :
2741    case Hexagon::STd_GP_cPt_V4 :
2742    case Hexagon::STd_GP_cNotPt_V4 :
2743    case Hexagon::STb_GP_cPt_V4 :
2744    case Hexagon::STb_GP_cNotPt_V4 :
2745    case Hexagon::STh_GP_cPt_V4 :
2746    case Hexagon::STh_GP_cNotPt_V4 :
2747    case Hexagon::STw_GP_cPt_V4 :
2748    case Hexagon::STw_GP_cNotPt_V4 :
2749      return QRI.Subtarget.hasV4TOps();
2750
2751    // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2752    // from the "Conditional Store" list. Because a predicated new value store
2753    // would NOT be promoted to a double dot new store. See diagram below:
2754    // This function returns yes for those stores that are predicated but not
2755    // yet promoted to predicate dot new instructions.
2756    //
2757    //                          +---------------------+
2758    //                    /-----| if (p0) memw(..)=r0 |---------\~
2759    //                   ||     +---------------------+         ||
2760    //          promote  ||       /\       /\                   ||  promote
2761    //                   ||      /||\     /||\                  ||
2762    //                  \||/    demote     ||                  \||/
2763    //                   \/       ||       ||                   \/
2764    //       +-------------------------+   ||   +-------------------------+
2765    //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
2766    //       +-------------------------+   ||   +-------------------------+
2767    //                        ||           ||         ||
2768    //                        ||         demote      \||/
2769    //                      promote        ||         \/ NOT possible
2770    //                        ||           ||         /\~
2771    //                       \||/          ||        /||\~
2772    //                        \/           ||         ||
2773    //                      +-----------------------------+
2774    //                      | if (p0.new) memw(..)=r0.new |
2775    //                      +-----------------------------+
2776    //                           Double Dot New Store
2777    //
2778  }
2779}
2780
2781
2782
2783DFAPacketizer *HexagonInstrInfo::
2784CreateTargetScheduleState(const TargetMachine *TM,
2785                           const ScheduleDAG *DAG) const {
2786  const InstrItineraryData *II = TM->getInstrItineraryData();
2787  return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2788}
2789
2790bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2791                                            const MachineBasicBlock *MBB,
2792                                            const MachineFunction &MF) const {
2793  // Debug info is never a scheduling boundary. It's necessary to be explicit
2794  // due to the special treatment of IT instructions below, otherwise a
2795  // dbg_value followed by an IT will result in the IT instruction being
2796  // considered a scheduling hazard, which is wrong. It should be the actual
2797  // instruction preceding the dbg_value instruction(s), just like it is
2798  // when debug info is not present.
2799  if (MI->isDebugValue())
2800    return false;
2801
2802  // Terminators and labels can't be scheduled around.
2803  if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2804    return true;
2805
2806  return false;
2807}
2808