1//===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the MSP430 implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "msp430-reg-info" 15 16#include "MSP430RegisterInfo.h" 17#include "MSP430.h" 18#include "MSP430MachineFunctionInfo.h" 19#include "MSP430TargetMachine.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/IR/Function.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Target/TargetOptions.h" 28 29#define GET_REGINFO_TARGET_DESC 30#include "MSP430GenRegisterInfo.inc" 31 32using namespace llvm; 33 34// FIXME: Provide proper call frame setup / destroy opcodes. 35MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm, 36 const TargetInstrInfo &tii) 37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) { 38 StackAlign = TM.getFrameLowering()->getStackAlignment(); 39} 40 41const uint16_t* 42MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 43 const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering(); 44 const Function* F = MF->getFunction(); 45 static const uint16_t CalleeSavedRegs[] = { 46 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, 47 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, 48 0 49 }; 50 static const uint16_t CalleeSavedRegsFP[] = { 51 MSP430::R5W, MSP430::R6W, MSP430::R7W, 52 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, 53 0 54 }; 55 static const uint16_t CalleeSavedRegsIntr[] = { 56 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, 57 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, 58 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W, 59 0 60 }; 61 static const uint16_t CalleeSavedRegsIntrFP[] = { 62 MSP430::R5W, MSP430::R6W, MSP430::R7W, 63 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, 64 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W, 65 0 66 }; 67 68 if (TFI->hasFP(*MF)) 69 return (F->getCallingConv() == CallingConv::MSP430_INTR ? 70 CalleeSavedRegsIntrFP : CalleeSavedRegsFP); 71 else 72 return (F->getCallingConv() == CallingConv::MSP430_INTR ? 73 CalleeSavedRegsIntr : CalleeSavedRegs); 74 75} 76 77BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 78 BitVector Reserved(getNumRegs()); 79 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 80 81 // Mark 4 special registers with subregisters as reserved. 82 Reserved.set(MSP430::PCB); 83 Reserved.set(MSP430::SPB); 84 Reserved.set(MSP430::SRB); 85 Reserved.set(MSP430::CGB); 86 Reserved.set(MSP430::PCW); 87 Reserved.set(MSP430::SPW); 88 Reserved.set(MSP430::SRW); 89 Reserved.set(MSP430::CGW); 90 91 // Mark frame pointer as reserved if needed. 92 if (TFI->hasFP(MF)) 93 Reserved.set(MSP430::FPW); 94 95 return Reserved; 96} 97 98const TargetRegisterClass * 99MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 100 const { 101 return &MSP430::GR16RegClass; 102} 103 104void 105MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 106 int SPAdj, unsigned FIOperandNum, 107 RegScavenger *RS) const { 108 assert(SPAdj == 0 && "Unexpected"); 109 110 MachineInstr &MI = *II; 111 MachineBasicBlock &MBB = *MI.getParent(); 112 MachineFunction &MF = *MBB.getParent(); 113 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 114 DebugLoc dl = MI.getDebugLoc(); 115 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 116 117 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW); 118 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 119 120 // Skip the saved PC 121 Offset += 2; 122 123 if (!TFI->hasFP(MF)) 124 Offset += MF.getFrameInfo()->getStackSize(); 125 else 126 Offset += 2; // Skip the saved FPW 127 128 // Fold imm into offset 129 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 130 131 if (MI.getOpcode() == MSP430::ADD16ri) { 132 // This is actually "load effective address" of the stack slot 133 // instruction. We have only two-address instructions, thus we need to 134 // expand it into mov + add 135 136 MI.setDesc(TII.get(MSP430::MOV16rr)); 137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 138 139 if (Offset == 0) 140 return; 141 142 // We need to materialize the offset via add instruction. 143 unsigned DstReg = MI.getOperand(0).getReg(); 144 if (Offset < 0) 145 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) 146 .addReg(DstReg).addImm(-Offset); 147 else 148 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) 149 .addReg(DstReg).addImm(Offset); 150 151 return; 152 } 153 154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 155 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 156} 157 158unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 159 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 160 161 return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW; 162} 163