1//===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines hazard recognizers for scheduling on PowerPC processors. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef PPCHAZRECS_H 15#define PPCHAZRECS_H 16 17#include "PPCInstrInfo.h" 18#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 19#include "llvm/CodeGen/ScoreboardHazardRecognizer.h" 20#include "llvm/CodeGen/SelectionDAGNodes.h" 21 22namespace llvm { 23 24/// PPCScoreboardHazardRecognizer - This class implements a scoreboard-based 25/// hazard recognizer for generic PPC processors. 26class PPCScoreboardHazardRecognizer : public ScoreboardHazardRecognizer { 27 const ScheduleDAG *DAG; 28public: 29 PPCScoreboardHazardRecognizer(const InstrItineraryData *ItinData, 30 const ScheduleDAG *DAG_) : 31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {} 32 33 virtual HazardType getHazardType(SUnit *SU, int Stalls); 34 virtual void EmitInstruction(SUnit *SU); 35 virtual void AdvanceCycle(); 36 virtual void Reset(); 37}; 38 39/// PPCHazardRecognizer970 - This class defines a finite state automata that 40/// models the dispatch logic on the PowerPC 970 (aka G5) processor. This 41/// promotes good dispatch group formation and implements noop insertion to 42/// avoid structural hazards that cause significant performance penalties (e.g. 43/// setting the CTR register then branching through it within a dispatch group), 44/// or storing then loading from the same address within a dispatch group. 45class PPCHazardRecognizer970 : public ScheduleHazardRecognizer { 46 const TargetInstrInfo &TII; 47 48 unsigned NumIssued; // Number of insts issued, including advanced cycles. 49 50 // Various things that can cause a structural hazard. 51 52 // HasCTRSet - If the CTR register is set in this group, disallow BCTRL. 53 bool HasCTRSet; 54 55 // StoredPtr - Keep track of the address of any store. If we see a load from 56 // the same address (or one that aliases it), disallow the store. We can have 57 // up to four stores in one dispatch group, hence we track up to 4. 58 // 59 // This is null if we haven't seen a store yet. We keep track of both 60 // operands of the store here, since we support [r+r] and [r+i] addressing. 61 const Value *StoreValue[4]; 62 int64_t StoreOffset[4]; 63 uint64_t StoreSize[4]; 64 unsigned NumStores; 65 66public: 67 PPCHazardRecognizer970(const TargetInstrInfo &TII); 68 virtual HazardType getHazardType(SUnit *SU, int Stalls); 69 virtual void EmitInstruction(SUnit *SU); 70 virtual void AdvanceCycle(); 71 virtual void Reset(); 72 73private: 74 /// EndDispatchGroup - Called when we are finishing a new dispatch group. 75 /// 76 void EndDispatchGroup(); 77 78 /// GetInstrType - Classify the specified powerpc opcode according to its 79 /// pipeline. 80 PPCII::PPC970_Unit GetInstrType(unsigned Opcode, 81 bool &isFirst, bool &isSingle,bool &isCracked, 82 bool &isLoad, bool &isStore); 83 84 bool isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset, 85 const Value *LoadValue) const; 86}; 87 88} // end namespace llvm 89 90#endif 91 92