1//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetRegisterInfo 11// class. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "reginfo" 16#include "PPCRegisterInfo.h" 17#include "PPC.h" 18#include "PPCFrameLowering.h" 19#include "PPCInstrBuilder.h" 20#include "PPCMachineFunctionInfo.h" 21#include "PPCSubtarget.h" 22#include "llvm/ADT/BitVector.h" 23#include "llvm/ADT/STLExtras.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineModuleInfo.h" 28#include "llvm/CodeGen/MachineRegisterInfo.h" 29#include "llvm/CodeGen/RegisterScavenging.h" 30#include "llvm/CodeGen/ValueTypes.h" 31#include "llvm/IR/CallingConv.h" 32#include "llvm/IR/Constants.h" 33#include "llvm/IR/Function.h" 34#include "llvm/IR/Type.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/MathExtras.h" 39#include "llvm/Support/raw_ostream.h" 40#include "llvm/Target/TargetFrameLowering.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include <cstdlib> 45 46#define GET_REGINFO_TARGET_DESC 47#include "PPCGenRegisterInfo.inc" 48 49using namespace llvm; 50 51PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 52 const TargetInstrInfo &tii) 53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 54 ST.isPPC64() ? 0 : 1, 55 ST.isPPC64() ? 0 : 1), 56 Subtarget(ST), TII(tii) { 57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 65 66 // 64-bit 67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 72} 73 74/// getPointerRegClass - Return the register class to use to hold pointers. 75/// This is used for addressing modes. 76const TargetRegisterClass * 77PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 78 const { 79 if (Subtarget.isPPC64()) 80 return &PPC::G8RCRegClass; 81 return &PPC::GPRCRegClass; 82} 83 84const uint16_t* 85PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 86 if (Subtarget.isDarwinABI()) 87 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 88 CSR_Darwin32_SaveList; 89 90 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 91} 92 93const uint32_t* 94PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 95 if (Subtarget.isDarwinABI()) 96 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 97 CSR_Darwin32_RegMask; 98 99 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 100} 101 102BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 103 BitVector Reserved(getNumRegs()); 104 const PPCFrameLowering *PPCFI = 105 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 106 107 Reserved.set(PPC::R0); 108 Reserved.set(PPC::R1); 109 Reserved.set(PPC::LR); 110 Reserved.set(PPC::LR8); 111 Reserved.set(PPC::RM); 112 113 // The SVR4 ABI reserves r2 and r13 114 if (Subtarget.isSVR4ABI()) { 115 Reserved.set(PPC::R2); // System-reserved register 116 Reserved.set(PPC::R13); // Small Data Area pointer register 117 } 118 119 // On PPC64, r13 is the thread pointer. Never allocate this register. 120 // Note that this is over conservative, as it also prevents allocation of R31 121 // when the FP is not needed. 122 if (Subtarget.isPPC64()) { 123 Reserved.set(PPC::R13); 124 Reserved.set(PPC::R31); 125 126 Reserved.set(PPC::X0); 127 Reserved.set(PPC::X1); 128 Reserved.set(PPC::X13); 129 Reserved.set(PPC::X31); 130 131 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 132 if (Subtarget.isSVR4ABI()) { 133 Reserved.set(PPC::X2); 134 } 135 } 136 137 if (PPCFI->needsFP(MF)) 138 Reserved.set(PPC::R31); 139 140 return Reserved; 141} 142 143unsigned 144PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 145 MachineFunction &MF) const { 146 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 147 const unsigned DefaultSafety = 1; 148 149 switch (RC->getID()) { 150 default: 151 return 0; 152 case PPC::G8RCRegClassID: 153 case PPC::GPRCRegClassID: { 154 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 155 return 32 - FP - DefaultSafety; 156 } 157 case PPC::F8RCRegClassID: 158 case PPC::F4RCRegClassID: 159 case PPC::VRRCRegClassID: 160 return 32 - DefaultSafety; 161 case PPC::CRRCRegClassID: 162 return 8 - DefaultSafety; 163 } 164} 165 166//===----------------------------------------------------------------------===// 167// Stack Frame Processing methods 168//===----------------------------------------------------------------------===// 169 170/// lowerDynamicAlloc - Generate the code for allocating an object in the 171/// current frame. The sequence of code with be in the general form 172/// 173/// addi R0, SP, \#frameSize ; get the address of the previous frame 174/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 175/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 176/// 177void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 178 int SPAdj, RegScavenger *RS) const { 179 // Get the instruction. 180 MachineInstr &MI = *II; 181 // Get the instruction's basic block. 182 MachineBasicBlock &MBB = *MI.getParent(); 183 // Get the basic block's function. 184 MachineFunction &MF = *MBB.getParent(); 185 // Get the frame info. 186 MachineFrameInfo *MFI = MF.getFrameInfo(); 187 // Determine whether 64-bit pointers are used. 188 bool LP64 = Subtarget.isPPC64(); 189 DebugLoc dl = MI.getDebugLoc(); 190 191 // Get the maximum call stack size. 192 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 193 // Get the total frame size. 194 unsigned FrameSize = MFI->getStackSize(); 195 196 // Get stack alignments. 197 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 198 unsigned MaxAlign = MFI->getMaxAlignment(); 199 if (MaxAlign > TargetAlign) 200 report_fatal_error("Dynamic alloca with large aligns not supported"); 201 202 // Determine the previous frame's address. If FrameSize can't be 203 // represented as 16 bits or we need special alignment, then we load the 204 // previous frame's address from 0(SP). Why not do an addis of the hi? 205 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 206 // Constructing the constant and adding would take 3 instructions. 207 // Fortunately, a frame greater than 32K is rare. 208 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 209 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 210 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 211 212 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 213 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 214 .addReg(PPC::R31) 215 .addImm(FrameSize); 216 } else if (LP64) { 217 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 218 .addImm(0) 219 .addReg(PPC::X1); 220 } else { 221 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 222 .addImm(0) 223 .addReg(PPC::R1); 224 } 225 226 // Grow the stack and update the stack pointer link, then determine the 227 // address of new allocated space. 228 if (LP64) { 229 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 230 .addReg(Reg, RegState::Kill) 231 .addReg(PPC::X1) 232 .addReg(MI.getOperand(1).getReg()); 233 if (!MI.getOperand(1).isKill()) 234 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 235 .addReg(PPC::X1) 236 .addImm(maxCallFrameSize); 237 else 238 // Implicitly kill the register. 239 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 240 .addReg(PPC::X1) 241 .addImm(maxCallFrameSize) 242 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 243 } else { 244 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 245 .addReg(Reg, RegState::Kill) 246 .addReg(PPC::R1) 247 .addReg(MI.getOperand(1).getReg()); 248 249 if (!MI.getOperand(1).isKill()) 250 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 251 .addReg(PPC::R1) 252 .addImm(maxCallFrameSize); 253 else 254 // Implicitly kill the register. 255 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 256 .addReg(PPC::R1) 257 .addImm(maxCallFrameSize) 258 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 259 } 260 261 // Discard the DYNALLOC instruction. 262 MBB.erase(II); 263} 264 265/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 266/// reserving a whole register (R0), we scrounge for one here. This generates 267/// code like this: 268/// 269/// mfcr rA ; Move the conditional register into GPR rA. 270/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 271/// stw rA, FI ; Store rA to the frame. 272/// 273void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 274 unsigned FrameIndex, int SPAdj, 275 RegScavenger *RS) const { 276 // Get the instruction. 277 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 278 // Get the instruction's basic block. 279 MachineBasicBlock &MBB = *MI.getParent(); 280 DebugLoc dl = MI.getDebugLoc(); 281 282 // FIXME: Once LLVM supports creating virtual registers here, or the register 283 // scavenger can return multiple registers, stop using reserved registers 284 // here. 285 (void) SPAdj; 286 (void) RS; 287 288 bool LP64 = Subtarget.isPPC64(); 289 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 290 unsigned SrcReg = MI.getOperand(0).getReg(); 291 292 // We need to store the CR in the low 4-bits of the saved value. First, issue 293 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 294 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 295 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 296 297 // If the saved register wasn't CR0, shift the bits left so that they are in 298 // CR0's slot. 299 if (SrcReg != PPC::CR0) 300 // rlwinm rA, rA, ShiftBits, 0, 31. 301 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 302 .addReg(Reg, RegState::Kill) 303 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 304 .addImm(0) 305 .addImm(31); 306 307 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 308 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 309 FrameIndex); 310 311 // Discard the pseudo instruction. 312 MBB.erase(II); 313} 314 315void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 316 unsigned FrameIndex, int SPAdj, 317 RegScavenger *RS) const { 318 // Get the instruction. 319 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 320 // Get the instruction's basic block. 321 MachineBasicBlock &MBB = *MI.getParent(); 322 DebugLoc dl = MI.getDebugLoc(); 323 324 // FIXME: Once LLVM supports creating virtual registers here, or the register 325 // scavenger can return multiple registers, stop using reserved registers 326 // here. 327 (void) SPAdj; 328 (void) RS; 329 330 bool LP64 = Subtarget.isPPC64(); 331 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 332 unsigned DestReg = MI.getOperand(0).getReg(); 333 assert(MI.definesRegister(DestReg) && 334 "RESTORE_CR does not define its destination"); 335 336 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 337 Reg), FrameIndex); 338 339 // If the reloaded register isn't CR0, shift the bits right so that they are 340 // in the right CR's slot. 341 if (DestReg != PPC::CR0) { 342 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 343 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 344 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 345 .addReg(Reg).addImm(32-ShiftBits).addImm(0) 346 .addImm(31); 347 } 348 349 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 350 .addReg(Reg); 351 352 // Discard the pseudo instruction. 353 MBB.erase(II); 354} 355 356bool 357PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 358 unsigned Reg, int &FrameIdx) const { 359 360 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 361 // ABI, return true to prevent allocating an additional frame slot. 362 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 363 // is arbitrary and will be subsequently ignored. For 32-bit, we have 364 // previously created the stack slot if needed, so return its FrameIdx. 365 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 366 if (Subtarget.isPPC64()) 367 FrameIdx = 0; 368 else { 369 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 370 FrameIdx = FI->getCRSpillFrameIndex(); 371 } 372 return true; 373 } 374 return false; 375} 376 377void 378PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 379 int SPAdj, unsigned FIOperandNum, 380 RegScavenger *RS) const { 381 assert(SPAdj == 0 && "Unexpected"); 382 383 // Get the instruction. 384 MachineInstr &MI = *II; 385 // Get the instruction's basic block. 386 MachineBasicBlock &MBB = *MI.getParent(); 387 // Get the basic block's function. 388 MachineFunction &MF = *MBB.getParent(); 389 // Get the frame info. 390 MachineFrameInfo *MFI = MF.getFrameInfo(); 391 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 392 DebugLoc dl = MI.getDebugLoc(); 393 394 // Take into account whether it's an add or mem instruction 395 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 396 if (MI.isInlineAsm()) 397 OffsetOperandNo = FIOperandNum-1; 398 399 // Get the frame index. 400 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 401 402 // Get the frame pointer save index. Users of this index are primarily 403 // DYNALLOC instructions. 404 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 405 int FPSI = FI->getFramePointerSaveIndex(); 406 // Get the instruction opcode. 407 unsigned OpC = MI.getOpcode(); 408 409 // Special case for dynamic alloca. 410 if (FPSI && FrameIndex == FPSI && 411 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 412 lowerDynamicAlloc(II, SPAdj, RS); 413 return; 414 } 415 416 // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 417 if (OpC == PPC::SPILL_CR) { 418 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 419 return; 420 } else if (OpC == PPC::RESTORE_CR) { 421 lowerCRRestore(II, FrameIndex, SPAdj, RS); 422 return; 423 } 424 425 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 426 427 bool is64Bit = Subtarget.isPPC64(); 428 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ? 429 (is64Bit ? PPC::X31 : PPC::R31) : 430 (is64Bit ? PPC::X1 : PPC::R1), 431 false); 432 433 // Figure out if the offset in the instruction is shifted right two bits. This 434 // is true for instructions like "STD", which the machine implicitly adds two 435 // low zeros to. 436 bool isIXAddr = false; 437 switch (OpC) { 438 case PPC::LWA: 439 case PPC::LD: 440 case PPC::STD: 441 case PPC::STD_32: 442 isIXAddr = true; 443 break; 444 } 445 446 bool noImmForm = false; 447 switch (OpC) { 448 case PPC::LVEBX: 449 case PPC::LVEHX: 450 case PPC::LVEWX: 451 case PPC::LVX: 452 case PPC::LVXL: 453 case PPC::LVSL: 454 case PPC::LVSR: 455 case PPC::STVEBX: 456 case PPC::STVEHX: 457 case PPC::STVEWX: 458 case PPC::STVX: 459 case PPC::STVXL: 460 noImmForm = true; 461 break; 462 } 463 464 // Now add the frame object offset to the offset from r1. 465 int Offset = MFI->getObjectOffset(FrameIndex); 466 if (!isIXAddr) 467 Offset += MI.getOperand(OffsetOperandNo).getImm(); 468 else 469 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 470 471 // If we're not using a Frame Pointer that has been set to the value of the 472 // SP before having the stack size subtracted from it, then add the stack size 473 // to Offset to get the correct offset. 474 // Naked functions have stack size 0, although getStackSize may not reflect that 475 // because we didn't call all the pieces that compute it for naked functions. 476 if (!MF.getFunction()->getAttributes(). 477 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) 478 Offset += MFI->getStackSize(); 479 480 // If we can, encode the offset directly into the instruction. If this is a 481 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 482 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 483 // clear can be encoded. This is extremely uncommon, because normally you 484 // only "std" to a stack slot that is at least 4-byte aligned, but it can 485 // happen in invalid code. 486 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 487 (!noImmForm && 488 isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 489 if (isIXAddr) 490 Offset >>= 2; // The actual encoded value has the low two bits zero. 491 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 492 return; 493 } 494 495 // The offset doesn't fit into a single register, scavenge one to build the 496 // offset in. 497 498 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 499 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 500 unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC); 501 502 // Insert a set of rA with the full offset value before the ld, st, or add 503 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 504 .addImm(Offset >> 16); 505 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 506 .addReg(SReg, RegState::Kill) 507 .addImm(Offset); 508 509 // Convert into indexed form of the instruction: 510 // 511 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 512 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 513 unsigned OperandBase; 514 515 if (noImmForm) 516 OperandBase = 1; 517 else if (OpC != TargetOpcode::INLINEASM) { 518 assert(ImmToIdxMap.count(OpC) && 519 "No indexed form of load or store available!"); 520 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 521 MI.setDesc(TII.get(NewOpcode)); 522 OperandBase = 1; 523 } else { 524 OperandBase = OffsetOperandNo; 525 } 526 527 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 528 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 529 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 530} 531 532unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 533 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 534 535 if (!Subtarget.isPPC64()) 536 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 537 else 538 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 539} 540 541unsigned PPCRegisterInfo::getEHExceptionRegister() const { 542 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 543} 544 545unsigned PPCRegisterInfo::getEHHandlerRegister() const { 546 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 547} 548