131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 106f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// This file contains the PowerPC implementation of the TargetRegisterInfo 116f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// class. 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 14f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 15f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#define DEBUG_TYPE "reginfo" 1679aa3417eb6f58d668aadfedf075240a41d35a26Craig Topper#include "PPCRegisterInfo.h" 172668959b8879097db368aec7d76c455260abc75bChris Lattner#include "PPC.h" 18d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "PPCFrameLowering.h" 1926bd0d48a164c419462133270e3ec1c2401a34d7Chris Lattner#include "PPCInstrBuilder.h" 202f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey#include "PPCMachineFunctionInfo.h" 21804e06704261f233111913a047ef7f7dec1b8725Chris Lattner#include "PPCSubtarget.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/BitVector.h" 23d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/STLExtras.h" 24d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/CodeGen/MachineFrameInfo.h" 25d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/CodeGen/MachineFunction.h" 26f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineInstrBuilder.h" 2744c3b9fdd416c79f4b67cde1aecfced5921efd81Jim Laskey#include "llvm/CodeGen/MachineModuleInfo.h" 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 297194aaf738a1b89441635340403f1c5b06ae18efBill Wendling#include "llvm/CodeGen/RegisterScavenging.h" 30d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/CodeGen/ValueTypes.h" 310b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/CallingConv.h" 320b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Constants.h" 330b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Function.h" 340b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Type.h" 35551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/CommandLine.h" 36551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/Debug.h" 37dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/ErrorHandling.h" 38ae232e7a1055033436370c0b3aecf054fa44d5e7Nate Begeman#include "llvm/Support/MathExtras.h" 39dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 40d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetFrameLowering.h" 41d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetInstrInfo.h" 42d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetMachine.h" 43d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetOptions.h" 44f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include <cstdlib> 4573f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 4673f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_TARGET_DESC 47a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "PPCGenRegisterInfo.inc" 48f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 4982bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohmanusing namespace llvm; 5082bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohman 517ce45783531cfa81bfd7be561ea7e4738e8c6ca8Evan ChengPPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 527ce45783531cfa81bfd7be561ea7e4738e8c6ca8Evan Cheng const TargetInstrInfo &tii) 530e6a052331f674dd70e28af41f654a7874405eabEvan Cheng : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 540e6a052331f674dd70e28af41f654a7874405eabEvan Cheng ST.isPPC64() ? 0 : 1, 550e6a052331f674dd70e28af41f654a7874405eabEvan Cheng ST.isPPC64() ? 0 : 1), 564edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt Subtarget(ST), TII(tii) { 57b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 58f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 59f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 60f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 61f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 62f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 63f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 641d9d7427c4a4e3c7bdcfd1f725447f355e509c20Nate Begeman ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 6582d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling 6682d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling // 64-bit 6782d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 6882d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 6982d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 7082d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 7182d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 72f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 73f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 74770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng/// getPointerRegClass - Return the register class to use to hold pointers. 75770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng/// This is used for addressing modes. 762cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerconst TargetRegisterClass * 77397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund OlesenPPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 78397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const { 79770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng if (Subtarget.isPPC64()) 80770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng return &PPC::G8RCRegClass; 812cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner return &PPC::GPRCRegClass; 82770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng} 83770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng 84015f228861ef9b337366f92f637d4e8d624bb006Craig Topperconst uint16_t* 8564d80e3387f328d21cd9cc06464b5de7861e3f27Evan ChengPPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 86e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky if (Subtarget.isDarwinABI()) 87e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 88e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky CSR_Darwin32_SaveList; 896b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller 90e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 91e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky} 926b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller 936ffb4024d875570a01d6b8db900a0385a491403bCraig Topperconst uint32_t* 94e46137f498fa81a088f13d24c79242eed3ff45a7Roman DivackyPPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 952a9ddfb903ae3baede7282348afae1f750905248Tilmann Scheller if (Subtarget.isDarwinABI()) 96e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 97e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky CSR_Darwin32_RegMask; 986b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller 99e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 1000f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 1010f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 102b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 103b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 10416c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const PPCFrameLowering *PPCFI = 10516c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 106d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 107b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R0); 108b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R1); 109b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::LR); 1107194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::LR8); 111b384ab9ea113ad22a9c7034b98060c7470f0dcc5Dale Johannesen Reserved.set(PPC::RM); 1127194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 113ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller // The SVR4 ABI reserves r2 and r13 1142a9ddfb903ae3baede7282348afae1f750905248Tilmann Scheller if (Subtarget.isSVR4ABI()) { 115ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller Reserved.set(PPC::R2); // System-reserved register 116ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller Reserved.set(PPC::R13); // Small Data Area pointer register 117ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller } 118ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller 1196b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller // On PPC64, r13 is the thread pointer. Never allocate this register. 1206b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller // Note that this is over conservative, as it also prevents allocation of R31 1216b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller // when the FP is not needed. 122b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (Subtarget.isPPC64()) { 123b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R13); 124b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R31); 1257194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 1267194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::X0); 1277194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::X1); 1287194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::X13); 1297194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::X31); 1306b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller 1316b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 1326b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller if (Subtarget.isSVR4ABI()) { 1336b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller Reserved.set(PPC::X2); 1346b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller } 135b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng } 1367194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 137c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov if (PPCFI->needsFP(MF)) 138b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R31); 1397194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 140b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 141b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 142b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 143768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkelunsigned 144768c65f677af3f05c2e94982043f90a1bfaceda5Hal FinkelPPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 145768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel MachineFunction &MF) const { 146768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 147768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel const unsigned DefaultSafety = 1; 148768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel 149768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel switch (RC->getID()) { 150768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel default: 151768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel return 0; 152768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::G8RCRegClassID: 153768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::GPRCRegClassID: { 154768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel unsigned FP = TFI->hasFP(MF) ? 1 : 0; 155768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel return 32 - FP - DefaultSafety; 156768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel } 157768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::F8RCRegClassID: 158768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::F4RCRegClassID: 159768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::VRRCRegClassID: 160768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel return 32 - DefaultSafety; 1612e313caa3631e2c94bb6d81429b77a30b116b520Hal Finkel case PPC::CRRCRegClassID: 1622e313caa3631e2c94bb6d81429b77a30b116b520Hal Finkel return 8 - DefaultSafety; 163768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel } 164768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel} 165768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel 166f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 167f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// Stack Frame Processing methods 168f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 169f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 1707194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// lowerDynamicAlloc - Generate the code for allocating an object in the 1712f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey/// current frame. The sequence of code with be in the general form 1722f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey/// 1730f8b53f19d29013ab18f3d444cea1e6305405611Dan Gohman/// addi R0, SP, \#frameSize ; get the address of the previous frame 1742f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 1750f8b53f19d29013ab18f3d444cea1e6305405611Dan Gohman/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 1762f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey/// 1777194aaf738a1b89441635340403f1c5b06ae18efBill Wendlingvoid PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 1787194aaf738a1b89441635340403f1c5b06ae18efBill Wendling int SPAdj, RegScavenger *RS) const { 1792f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction. 1802f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineInstr &MI = *II; 1812f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction's basic block. 1822f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineBasicBlock &MBB = *MI.getParent(); 1832f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the basic block's function. 1842f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineFunction &MF = *MBB.getParent(); 1852f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the frame info. 1862f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineFrameInfo *MFI = MF.getFrameInfo(); 1872f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Determine whether 64-bit pointers are used. 1882f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey bool LP64 = Subtarget.isPPC64(); 189536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen DebugLoc dl = MI.getDebugLoc(); 1902f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 191fab0439c62984b3dc851eb99c31c4f6edda092a1Evan Cheng // Get the maximum call stack size. 1922f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 1932f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the total frame size. 1942f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey unsigned FrameSize = MFI->getStackSize(); 1952f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 1962f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get stack alignments. 19716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 1982f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey unsigned MaxAlign = MFI->getMaxAlignment(); 19938cb1381b5ec8c75242650491c2b8e7e8a302665Dale Johannesen if (MaxAlign > TargetAlign) 20038cb1381b5ec8c75242650491c2b8e7e8a302665Dale Johannesen report_fatal_error("Dynamic alloca with large aligns not supported"); 2012f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 2022f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Determine the previous frame's address. If FrameSize can't be 2032f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // represented as 16 bits or we need special alignment, then we load the 2042f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // previous frame's address from 0(SP). Why not do an addis of the hi? 2052f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 2062f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Constructing the constant and adding would take 3 instructions. 2072f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Fortunately, a frame greater than 32K is rare. 2087194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 2097194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 2101c6c61a6089fb2bef47de5ee9a5f4acc34047600Hal Finkel unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 2117194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 21234247a0f356edf45ae3ad9ce04e1f90a77c6dba7Benjamin Kramer if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 213536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 2142f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addReg(PPC::R31) 2152f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addImm(FrameSize); 2162f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } else if (LP64) { 2177285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 2187285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel .addImm(0) 2197285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel .addReg(PPC::X1); 2202f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } else { 221536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 2222f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addImm(0) 2232f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addReg(PPC::R1); 2242f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } 2252f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 2267194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Grow the stack and update the stack pointer link, then determine the 2277194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // address of new allocated space. 2282f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey if (LP64) { 2297285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 2307285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel .addReg(Reg, RegState::Kill) 2317285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel .addReg(PPC::X1) 2327285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel .addReg(MI.getOperand(1).getReg()); 2337194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (!MI.getOperand(1).isKill()) 234536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 23571a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::X1) 23671a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(maxCallFrameSize); 2377194aaf738a1b89441635340403f1c5b06ae18efBill Wendling else 2387194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Implicitly kill the register. 239536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 24071a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::X1) 24171a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(maxCallFrameSize) 242587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 2432f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } else { 244ac81cc3282750d724f824547bc519caec0a01bceHal Finkel BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 245587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg, RegState::Kill) 246ac81cc3282750d724f824547bc519caec0a01bceHal Finkel .addReg(PPC::R1) 2472f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addReg(MI.getOperand(1).getReg()); 2487194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 2497194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (!MI.getOperand(1).isKill()) 250536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 25171a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::R1) 25271a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(maxCallFrameSize); 2537194aaf738a1b89441635340403f1c5b06ae18efBill Wendling else 2547194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Implicitly kill the register. 255536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 25671a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::R1) 25771a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(maxCallFrameSize) 258587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 2592f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } 2602f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 2612f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Discard the DYNALLOC instruction. 2622f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MBB.erase(II); 2632f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey} 2642f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 2657194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 2667194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// reserving a whole register (R0), we scrounge for one here. This generates 2677194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// code like this: 2687194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// 2697194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// mfcr rA ; Move the conditional register into GPR rA. 2707194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 2717194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// stw rA, FI ; Store rA to the frame. 2727194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// 2737194aaf738a1b89441635340403f1c5b06ae18efBill Wendlingvoid PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 2747194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned FrameIndex, int SPAdj, 2757194aaf738a1b89441635340403f1c5b06ae18efBill Wendling RegScavenger *RS) const { 2767194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Get the instruction. 277d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 2787194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Get the instruction's basic block. 2797194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock &MBB = *MI.getParent(); 280536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen DebugLoc dl = MI.getDebugLoc(); 2817194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 282fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // FIXME: Once LLVM supports creating virtual registers here, or the register 283fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // scavenger can return multiple registers, stop using reserved registers 284fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // here. 285fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (void) SPAdj; 286fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (void) RS; 287fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel 288951cd021c10966f3ae146588b2466deaef730cb6Roman Divacky bool LP64 = Subtarget.isPPC64(); 2894d53e7798c94143a22a9871261b8443592b929d5Hal Finkel unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 290fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel unsigned SrcReg = MI.getOperand(0).getReg(); 2917194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 2922b5fab67c1a2d3ec1184c065e0a6bdaaaec9253aBill Wendling // We need to store the CR in the low 4-bits of the saved value. First, issue 2935f07d5224ddc32f405d7e19de8e58e91ab2816bcDale Johannesen // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 294234bb38d6c421ea22229087a9835afe99e531276Hal Finkel BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 2955f07d5224ddc32f405d7e19de8e58e91ab2816bcDale Johannesen .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 2962b5fab67c1a2d3ec1184c065e0a6bdaaaec9253aBill Wendling 2977194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // If the saved register wasn't CR0, shift the bits left so that they are in 2987194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // CR0's slot. 2997194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (SrcReg != PPC::CR0) 3007194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // rlwinm rA, rA, ShiftBits, 0, 31. 301234bb38d6c421ea22229087a9835afe99e531276Hal Finkel BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 302587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg, RegState::Kill) 303966aeb5788c242cfaca35c56c0ddc0ff778d4376Evan Cheng .addImm(getPPCRegisterNumbering(SrcReg) * 4) 3047194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addImm(0) 3057194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addImm(31); 3067194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 307951cd021c10966f3ae146588b2466deaef730cb6Roman Divacky addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 308587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 3097194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FrameIndex); 3107194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 3117194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Discard the pseudo instruction. 3127194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MBB.erase(II); 3137194aaf738a1b89441635340403f1c5b06ae18efBill Wendling} 3147194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 315d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkelvoid PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 316d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel unsigned FrameIndex, int SPAdj, 317d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel RegScavenger *RS) const { 318d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // Get the instruction. 319d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 320d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // Get the instruction's basic block. 321d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel MachineBasicBlock &MBB = *MI.getParent(); 322d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel DebugLoc dl = MI.getDebugLoc(); 323d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 324fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // FIXME: Once LLVM supports creating virtual registers here, or the register 325fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // scavenger can return multiple registers, stop using reserved registers 326fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // here. 327fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (void) SPAdj; 328fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (void) RS; 329fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel 330fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel bool LP64 = Subtarget.isPPC64(); 3314d53e7798c94143a22a9871261b8443592b929d5Hal Finkel unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 332d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel unsigned DestReg = MI.getOperand(0).getReg(); 333d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel assert(MI.definesRegister(DestReg) && 334d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel "RESTORE_CR does not define its destination"); 335d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 336d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 337d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel Reg), FrameIndex); 338d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 339d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // If the reloaded register isn't CR0, shift the bits right so that they are 340d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // in the right CR's slot. 341d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel if (DestReg != PPC::CR0) { 342d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 343d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // rlwinm r11, r11, 32-ShiftBits, 0, 31. 34417d2dbd5f9dd6c0de86398178f302ef46ba6ec79Hal Finkel BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 345d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addReg(Reg).addImm(32-ShiftBits).addImm(0) 346d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addImm(31); 347d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel } 348d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 349234bb38d6c421ea22229087a9835afe99e531276Hal Finkel BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 350d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addReg(Reg); 351d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 352d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // Discard the pseudo instruction. 353d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel MBB.erase(II); 354d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel} 355d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 3569d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divackybool 3579d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman DivackyPPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 3589d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky unsigned Reg, int &FrameIdx) const { 3599d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 3609d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 3619d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // ABI, return true to prevent allocating an additional frame slot. 3629d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 3634edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt // is arbitrary and will be subsequently ignored. For 32-bit, we have 3644edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt // previously created the stack slot if needed, so return its FrameIdx. 3659d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 3664edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt if (Subtarget.isPPC64()) 3679d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky FrameIdx = 0; 3684edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt else { 3694edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3704edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt FrameIdx = FI->getCRSpillFrameIndex(); 3719d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 3729d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky return true; 3739d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 3749d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky return false; 3759d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky} 3769d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 377fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 378b58f498f7502e7e1833decbbbb4df771367c7341Jim GrosbachPPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 379108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int SPAdj, unsigned FIOperandNum, 380108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier RegScavenger *RS) const { 38197de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng assert(SPAdj == 0 && "Unexpected"); 38297de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng 3832f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction. 384f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MachineInstr &MI = *II; 3852f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction's basic block. 386f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MachineBasicBlock &MBB = *MI.getParent(); 3872f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the basic block's function. 388f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MachineFunction &MF = *MBB.getParent(); 3892f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the frame info. 3902f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineFrameInfo *MFI = MF.getFrameInfo(); 39116c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 392536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen DebugLoc dl = MI.getDebugLoc(); 393b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman 3942f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Take into account whether it's an add or mem instruction 395108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 396518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (MI.isInlineAsm()) 397108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier OffsetOperandNo = FIOperandNum-1; 3987194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 3992f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the frame index. 400108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 4017194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 4022f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the frame pointer save index. Users of this index are primarily 4032f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // DYNALLOC instructions. 4042f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4052f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey int FPSI = FI->getFramePointerSaveIndex(); 4062f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction opcode. 4072f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey unsigned OpC = MI.getOpcode(); 4082f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 4092f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Special case for dynamic alloca. 4102f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey if (FPSI && FrameIndex == FPSI && 4112f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 4127194aaf738a1b89441635340403f1c5b06ae18efBill Wendling lowerDynamicAlloc(II, SPAdj, RS); 413fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 4147194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 4157194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 416d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 4177285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel if (OpC == PPC::SPILL_CR) { 4187285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel lowerCRSpilling(II, FrameIndex, SPAdj, RS); 4197285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel return; 4207285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel } else if (OpC == PPC::RESTORE_CR) { 4217285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel lowerCRRestore(II, FrameIndex, SPAdj, RS); 4227285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel return; 423d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel } 424f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 425f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 4266d0e014b1fecb35a06e551165614c08edc30194aHal Finkel 4276d0e014b1fecb35a06e551165614c08edc30194aHal Finkel bool is64Bit = Subtarget.isPPC64(); 428108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ? 4296d0e014b1fecb35a06e551165614c08edc30194aHal Finkel (is64Bit ? PPC::X31 : PPC::R31) : 4306d0e014b1fecb35a06e551165614c08edc30194aHal Finkel (is64Bit ? PPC::X1 : PPC::R1), 431f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner false); 432f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 4337ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner // Figure out if the offset in the instruction is shifted right two bits. This 4347ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner // is true for instructions like "STD", which the machine implicitly adds two 4357ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner // low zeros to. 4367ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner bool isIXAddr = false; 4372f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey switch (OpC) { 4387ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner case PPC::LWA: 4397ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner case PPC::LD: 4407ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner case PPC::STD: 4417ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner case PPC::STD_32: 4427ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner isIXAddr = true; 4437ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner break; 4447ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner } 445324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel 446324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel bool noImmForm = false; 447324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel switch (OpC) { 448324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::LVEBX: 449324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::LVEHX: 450324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::LVEWX: 451324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::LVX: 452324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::LVXL: 453324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::LVSL: 454324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::LVSR: 455324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::STVEBX: 456324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::STVEHX: 457324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::STVEWX: 458324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::STVX: 459324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel case PPC::STVXL: 460324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel noImmForm = true; 461324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel break; 462324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel } 463324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel 464f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // Now add the frame object offset to the offset from r1. 4652f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey int Offset = MFI->getObjectOffset(FrameIndex); 4667ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner if (!isIXAddr) 4679a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner Offset += MI.getOperand(OffsetOperandNo).getImm(); 4687ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner else 4699a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 470f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 471f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // If we're not using a Frame Pointer that has been set to the value of the 472f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // SP before having the stack size subtracted from it, then add the stack size 473f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // to Offset to get the correct offset. 4748c5358c93675b009ba2d57c3a5980f6bc58ba536Dale Johannesen // Naked functions have stack size 0, although getStackSize may not reflect that 4758c5358c93675b009ba2d57c3a5980f6bc58ba536Dale Johannesen // because we didn't call all the pieces that compute it for naked functions. 476831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling if (!MF.getFunction()->getAttributes(). 477831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) 4788c5358c93675b009ba2d57c3a5980f6bc58ba536Dale Johannesen Offset += MFI->getStackSize(); 479b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman 480789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // If we can, encode the offset directly into the instruction. If this is a 481789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 482789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 483789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // clear can be encoded. This is extremely uncommon, because normally you 484789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // only "std" to a stack slot that is at least 4-byte aligned, but it can 485789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // happen in invalid code. 486f2f6182f6a88cf4b8d8cb95686d68aa14ddb6857Hal Finkel if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 487324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel (!noImmForm && 488324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 489789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner if (isIXAddr) 490f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner Offset >>= 2; // The actual encoded value has the low two bits zero. 491f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 492fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 493789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner } 4947194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 4957194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // The offset doesn't fit into a single register, scavenge one to build the 4967194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // offset in. 4977194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 4987285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 4997285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 5001c6c61a6089fb2bef47de5ee9a5f4acc34047600Hal Finkel unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC); 5017194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5027194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Insert a set of rA with the full offset value before the ld, st, or add 5036d0e014b1fecb35a06e551165614c08edc30194aHal Finkel BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 5047194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addImm(Offset >> 16); 5056d0e014b1fecb35a06e551165614c08edc30194aHal Finkel BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 506587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SReg, RegState::Kill) 5077194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addImm(Offset); 5087194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5097194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Convert into indexed form of the instruction: 5107194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // 5117194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 5127194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 513789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner unsigned OperandBase; 5147194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 515324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel if (noImmForm) 516324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel OperandBase = 1; 517324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel else if (OpC != TargetOpcode::INLINEASM) { 518789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner assert(ImmToIdxMap.count(OpC) && 519789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner "No indexed form of load or store available!"); 520789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 5215080f4d9919d39b367891dc51e739c571a66036cChris Lattner MI.setDesc(TII.get(NewOpcode)); 522789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner OperandBase = 1; 523f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner } else { 524789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner OperandBase = OffsetOperandNo; 525f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 526fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach 527108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 528789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 5292e95afa04cd1c89de7e4abaeead66cd8e51ec929Hal Finkel MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 530f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 531f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 5323f2bf85d14759cc4b28a86805f566ac805a54d00David Greeneunsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 53316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 534d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 535a94a203f346e65d40c4c3fe478c5d8d7a2ff5df6Chris Lattner if (!Subtarget.isPPC64()) 536d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 537a94a203f346e65d40c4c3fe478c5d8d7a2ff5df6Chris Lattner else 538d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 5394188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey} 5404188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey 54162819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned PPCRegisterInfo::getEHExceptionRegister() const { 54262819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 54362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 54462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 54562819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned PPCRegisterInfo::getEHHandlerRegister() const { 54662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 54762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 548