| 751bc8d4c9ee4298449fed264571ffc162852e06 |
|
20-Feb-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Fix #includes, so we include only what we really need.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 860e7cdab9d5eceda5ac52ae0ddfb4bdab0067f2 |
|
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.
Accordingly, change RegDefIter to contain MVTs instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| aa7744d75fc1769ccc12c65c07bb5b82afa58330 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.
Accordingly, change RegDefIter to contain MVTs instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| d4f759696d1bd0ba7c0e6eefd7ed8b556840419a |
|
17-Oct-2012 |
Evan Cheng <evan.cheng@apple.com> |
Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't use
any scheduling heuristics nor does it build up any scheduling data structure
that other heuristics use. It essentially linearize by doing a DFA walk but
it does handle glues correctly.
IMPORTANT: it probably can't handle all the physical register dependencies so
it's not suitable for x86. It also doesn't deal with dbg_value nodes right now
so it's definitely is still WIP.
rdar://12474515
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| a98f600a64b7b70754df58926ce8d60feeb9ce29 |
|
08-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: remove forceUnitLatencies. Defaults are handled by the default SchedModel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 74500bdba3eae36a1a8a17d8bad0b971b9c212ec |
|
08-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add SelectionDAG::getTargetIndex.
This adds support for TargetIndex operands during isel. The meaning of
these (index, offset, flags) operands is entirely defined by the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| b7e0289fb320c8440ba5eed121a8b932dbd806a2 |
|
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 953be893e8cffa0ef9bf410036cd96aeb526e98a |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 47c144505b9be28ed22c626b3a407c11dba2fec5 |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.
ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.
ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.
Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.
- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.
- Added ScheduleDAGInstrs::begin()/end() public API.
- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 84b454d1a270a5d685e01686ed15e68c44b0b56a |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule emission.
ScheduleDAG has nothing to do with how the instructions are scheduled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 73ba69b6843f7f23345b1e8745cb328952cae0d8 |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule printing.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 4c727204271067f3dbf50bd23098b2df8e1cc47a |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 56b94c52c9bf0342106ca7d274b9bb469d5ef619 |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
Cleanup in preparation for misched: Move DAG visualization logic.
Soon, ScheduleDAG will not refer to the BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 084e179f090f9a47bdf66f49775a125f4a2a8a8c |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 9cf37e8b48732fccd4c301ed51aafed7074bd84e |
|
19-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a RegisterMaskSDNode class.
This SelectionDAG node will be attached to call nodes by LowerCall(),
and eventually becomes a MO_RegisterMask MachineOperand on the
MachineInstr representing the call instruction.
LowerCall() will attach a register mask that depends on the calling
convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 702110159a53481227b01fed81fa4eec0ad3cc46 |
|
27-Jun-2011 |
Owen Anderson <resistor@mac.com> |
The index stored in the RegDefIter is one after the current index. When getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 77b4b13c2a525faf646a6784b24692cf0459b75e |
|
16-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 54699765064842fd08d1466adc93453660bc2a85 |
|
07-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Added a check in the preRA scheduler for potential interference on a
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.
Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 92e946630d5f9bb092853b93501387dd216899b9 |
|
04-Feb-2011 |
Andrew Trick <atrick@apple.com> |
Introducing a new method of tracking register pressure. We can't
precisely track pressure on a selection DAG, but we can at least keep
it balanced. This design accounts for various interesting aspects of
selection DAGS: register and subregister copies, glued nodes, dead
nodes, unused registers, etc.
Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter.
Note: I disabled PrescheduleNodesWithMultipleUses when register
pressure is enabled, based on no evidence other than I don't think it
makes sense to have both enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
|
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 302ef834e0a2fd03e4b435079a9fa6c1e1cdc23b |
|
10-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring, no functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 1cc3984148be113c6e5e470f23c9ddbd37679c5f |
|
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 15a16def6e70c8f7df1023da80ceb89887203b40 |
|
20-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add a hybrid bottom up scheduler that reduce register usage while avoiding
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| decc2671516e6c52ee2f29f7746f8d02753845ea |
|
07-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
Three changes:
1. Introduce some enums and accessors in the InlineAsm class
that eliminate a ton of magic numbers when handling inline
asm SDNode.
2. Add a new MDNodeSDNode selection dag node type that holds
a MDNode (shocking!)
3. Add a new argument to ISD::INLINEASM nodes that hold !srcloc
metadata, propagating it to the instruction emitter, which
drops it.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| c589e03865bb31da70e0037d5c32fdaaa5f79f24 |
|
22-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may improve cache locality. This is controlled by -cluster-loads for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 8c2b52552c90f39e4b2fed43e309e599e742b6ac |
|
30-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Initial target-independent CodeGen support for BlockAddresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| bcea859fc1dd1af9ac66ec93ea04ce9a19c8451c |
|
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Create a new InstrEmitter class for translating SelectionDAG nodes
into MachineInstrs. This is mostly just moving the code from
ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 98976e4dcd18adbbe676048c0069e67346eb4ade |
|
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
The ScheduleDAG framework now requires an AliasAnalysis argument, though
it isn't needed in the ScheduleDAGSDNodes schedulers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
|
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 88c7af096b09ad26cbcebfdf40151e04094b7460 |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| f8c7394781f7cf27ac52ca087e289436d36844da |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.
Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.
Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 47ac0f0c7c39289f5970688154e385be22b7f293 |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 56774d2b0d865b597f47235ad708e772636e6834 |
|
06-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Delete an unused member function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|
| 84fbac580941548a6ab1121ed3b0ffdc4e2bc080 |
|
06-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Move ScheduleDAGSDNodes.h to be a private header. Front-ends
that previously included this header should include
SchedulerRegistry.h instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
|