| a3d82ce19fd825cbf3bf85b5969424217fc40b45 |
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15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| e30f32a69ba57dfecbd670d971048bccaf727798 |
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24-Apr-2013 |
Andrew Trick <atrick@apple.com> |
Machine model: verify well-formed processor resource groups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 1ab961f6d3cdd284f5d6c696f3e26eb3627e2c8b |
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16-Mar-2013 |
Andrew Trick <atrick@apple.com> |
Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.
Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 8efd0f00beb4002940c341250c7db23fbe8ac2c1 |
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20-Dec-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix an uninitialized member variable, found by -fsanitize=bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 4ffd89fa4d2788611187d1a534d2ed46adf1702c |
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04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| dbe6d43dfac78d567973dac8fc2a0190dad5135f |
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10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter cleanup.
Consistently evaluate Aliases and Sequences recursively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 13745262a8db98d6c4513ff9934db4be75a8b26c |
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04-Oct-2012 |
Andrew Trick <atrick@apple.com> |
Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 2062b1260fa9df3e69e7b4d24a657a0ebb7f8710 |
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04-Oct-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter, nearly first class support for SchedAlias.
A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 92649883119aaa8edd9ccf612eaaff5ccc8fcc77 |
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22-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Machine Model (-schedmodel only). Added SchedAliases.
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 3b8fb648c6e1c519b7e0f487f4fb511744869d35 |
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19-Sep-2012 |
Andrew Trick <atrick@apple.com> |
SchedMachineModel: compress the CPU's WriteLatencyTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| e076bb1e938aa9f97609c926590b1e176b0efbd2 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| e3dbc98a4fc2a31102e4ace6317eac9cf16afb9c |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Use getSchedClassIdx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| e1b53287179b4b9b5c3c549586f688d3fa2ae8ef |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 5d9408214334c26c183cdcdda16e73a66cf857ce |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 41be51b72cabfcef39efa7e5d2ce1250407cea7d |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Use getSchedClassIdx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 3cbd1786ac06fe751dc4b5ad55e75115cb1d51ce |
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15-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget parser. Handle new machine model.
Collect processor resources from the subtarget defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 5e613c260bb3044eb059dea74cd6bccfa9b85bdd |
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15-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget parser. Handle new machine model.
Infer SchedClasses from variants defined by the target or subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 48605c340614fc1fb2ae1d975fc565a4188182e0 |
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15-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
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| 2661b411ccc81b1fe19194d3f43b2630cbef3f28 |
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07-Jul-2012 |
Andrew Trick <atrick@apple.com> |
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.h
|