| 6754ec831e5aaec516db929c8db6e7478a2f5540 |
|
13-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Fix accumulator_contains() test to also reject swizzles of the dst.
When faced with this sequence:
MOV R1, c[1];
MAD R0, R2, R1.x, R1.y;
we were concluding that the MOV of R1 set up our accumulator and so we could
just use the previous result. Only, it's got R1.xyzw in it instead of the
r1.y we're looking for.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46784
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9b4053cabd8bda180b352d2d2047209f6ca5f6e8 |
|
06-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop the confusing saturate argument to math instruction setup.
This was ridiculous. We were ignoring the inst->header.saturate flag in the
case of math and only math. On gen4, we would leave inst->header.saturate in
place if it happened to be set, which would end up being applied to the
implicit mov and thus trash the first argument. On gen6, we would overwrite
inst->header.saturate with the saturate flag from the argument, which was not
set appropriately in brw_vec4_emit.cpp, and was only not a bug due to our
incompetence at coalescing saturate moves.
By ripping the argument out and making saturate work just like all the other
brw_eu_emit.c code generation, we can avoid both these classes of bugs.
Fixes piglit fog-modes, and the new specific fs-saturate-exp2 case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f78f48b6d2c4034a62ab11a558c95901d2245c4a |
|
02-Apr-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove vestiges of function call support from the old VS backend.
This never worked. brwProgramStringNotify also explicitly rejects
programs that use CAL and RET. So there's no need for this to exist.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f0cecd43d6b6d3f5def3fd43b9c95baaf3be9b16 |
|
13-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Move VUE map computation to once at VS compile time.
With this and the previous patch, 640x480 nexuiz is running 0.169118%
+/- 0.0863696% faster (n=121). On a VS state change microbenchmark,
performance is increased 8.28645% +/- 0.460478% (n=52).
v2: Fix CACHE_NEW_VS comment.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9f3d3216cf25d8ffed4d72fbce6feacbc2990e4b |
|
13-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Make the userclip flag for the VUE map come from VS prog data.
This reduces recomputation of state based on non-clipping-related
transform changes, and is a step toward removing VUE map
recomputation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f1d89638c02afafbf82ef657cd6ba9965dad6738 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop.
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| ce6be334bbf7f44c71ad5d190f9fb075d2f9a38c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching.
The EU code itself can just do this work, since all the consumers were
duplicating it.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 32118cfe37495738ed5931c6b1a71b8ee2ad189c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9f8814752f306cb9a26d283f0b7cf876639e10f7 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop unused do_insn argument from gen6_CONT().
The branch distances get patched up later at the WHILE instruction.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| dca6a28a14f22d77273d79d44f57b0d853c0242d |
|
31-Oct-2011 |
Mathias Fröhlich <Mathias.Froehlich@web.de> |
mesa: Make gl_program::InputsRead 64 bits.
Make gl_program::InputsRead a 64 bits bitfield.
Adapt the intel and radeon driver to handle a 64 bits
InputsRead value.
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 018ea68d8780ab5baeef0b8122b8410e5e55ae6d |
|
27-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 Gen6+: De-compact clip planes.
Previously, if the user enabled a non-consecutive set of clip planes
(e.g. 0, 1, and 3), the driver would compact them down to a
consecutive set starting at 0. This optimization was of dubious
value, and complicated the implementation of gl_ClipDistance.
This patch changes the driver so that with Gen6 and later chipsets, we
no longer compact the clip planes. However, we still discard any clip
planes beyond the highest number that is in use, so performance should
not be affected for applications that use clip planes consecutively
from 0.
With chipsets previous to Gen6, we still compact the clip planes,
since the pre-Gen6 clipper thread relies on this behavior.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f4f686e825ad2d64e50fb9e2491ef60507d59c38 |
|
30-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 VS: Change nr_userclip to nr_userclip_planes.
The only remaining uses of brw_vs_prog_key::nr_userclip only occurred
when using clip planes (as opposed to gl_ClipDistance). This patch
renames the value to nr_userclip_planes and sets it to zero when
gl_ClipDistance is in use. This avoids unnecessary VS recompiles.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 18e2e19b07b312c978dfbb6d336f69fa84b3ffe2 |
|
27-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Make brw_compute_vue_map's userclip dependency a boolean.
Previously, brw_compute_vue_map required an argument indicating the
number of clip planes in use, but all it did with it was check if it
was nonzero.
This patch changes brw_compute_vue_map to take a boolean instead.
This allows us to avoid some unnecessary recompilation of the Gen4/5
GS and SF threads.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| becd54eedb26ec9076e6f5f98f485861b3e13a90 |
|
03-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Remove two_side_color from brw_compute_vue_map().
Since we now lay out the VUE the same way regardless of whether
two-sided color is enabled, brw_compute_vue_map() no longer needs to
know whether two-sided color is enabled. This allows the two-sided
color flag to be removed from the clip, GS, and VS keys, so that fewer
GPU programs need to be recompiled when turning two-sided color on and
off.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 85e57eb9cada5c97d49e11295e23cc6e472b3130 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: old VS: use the VUE map to compute the URB entry size.
Previously, the old VS backend computed the URB entry size by adding
the number of vertex shader outputs to the size of the URB header.
This often produced a larger result than necessary, because some
vertex shader outputs are stored in the header, so they were being
double counted. This patch changes the old VS backend to compute the
URB entry size directly from the number of slots in the VUE map.
Note: there's a subtle change in that we no longer count header
registers towards the size of the VF input. I believe this is
correct, because the header is only emitted in the output of the VS
stage--it is not present in the input. (As evidence for this, note
that brw_vs_state.c sets urb_entry_read_offset to 0--it does not
include space for the header as part of the VS input).
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 3c17efd14888e453d1a15d92e97c99f2a278e213 |
|
01-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: old VS: Use brw_vue_map instead of implicit assumptions about VUE structure.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 8654931d117f178fa575d3fdc5bbff9f8bf9e816 |
|
22-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Make the old VS backend record pull constant references in pull_params[].
We'll be using that to track things for the new VS backend, and this will
avoid cluttering brw_vs_surface_state.c for it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 116680ddc28c2c3b04fd78acdaa3ef2108c43872 |
|
03-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Remove all bits of NRM3 and NRM4 code
Nothing in Mesa generates these opcodes, and i965 hardware cannot
support it natively. If support were ever added for this opcode in
Mesa, there had better be a lowering pass for hardware that doesn't
support it natively.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| af3c9803d818fd33139f1247a387d64b967b8992 |
|
02-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Start adding the VS visitor and codegen.
The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's
currently controlled by the INTEL_NEW_VS=1 environment variable, and
only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 4683529048ee133481b2d8f1cae1685aa1736f9a |
|
04-Aug-2011 |
Bryan Cain <bryancain3@gmail.com> |
Merge branch 'glsl-to-tgsi'
Conflicts:
src/mesa/state_tracker/st_atom_pixeltransfer.c
src/mesa/state_tracker/st_program.c
|
| 54db6e618e43abbd69b59e0a03e2b6ec83d3120f |
|
30-Jun-2011 |
Bryan Cain <bryancain3@gmail.com> |
r200, r600c, i965: fix build
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| d92463d5dc42aca09a54588c322fc60582cf9131 |
|
22-Jul-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: vs optimization fix: Check val.{negate,abs} in accumulator_contains()
When emitting a MAC instruction in a vertex shader, brw_vs_emit()
calls accumulator_contains() to determine whether the accumulator
already contains the appropriate addend; if it does, then we can avoid
emitting an unnecessary MOV instruction.
However, accumulator_contains() wasn't checking the val.negate or
val.abs flags. As a result, if the desired value was the negation, or
the absolute value, of what was already in the accumulator, we would
generate an incorrect shader.
Fixes piglit test vs-refract-vec4-vec4-float.
Tested on Gen5 and Gen6.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 1d3f09f15998c60326bf6c53a8d32c82496264ae |
|
21-Jul-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: When emitting a src/dst read of an output, keep the swizzle and neg
Fixes i965 piglit vs-varying-array-mat[234]-row-rd.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 337e2dfad0bcd567755272271abd2593a1d0fd1f |
|
21-Jul-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: When emitting a src/dst write of an output, keep the write mask
Fixes i965 piglit:
vs-varying-array-mat[234]-col-row-wr
vs-varying-array-mat[234]-index-col-row-wr
vs-varying-array-mat[234]-index-row-wr
vs-varying-array-mat[234]-row-wr
vs-varying-mat[234]-col-row-wr
vs-varying-mat[234]-row-wr
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 95c2e0b601fd333cc73d7f214a3cd949f7e45aac |
|
12-Jun-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: fix mask used to write to clip distance registers when gen>6
In gen6 and above, clip distances 0-3 are written to message register
3's xyzw components, and 4-7 to message register 4's xyzw components.
Therefore when when writing the clip distances we need to examine the
lower 2 bits of the clip distance index to see which component to
write to.
emit_vertex_write() was examining the lower 3 bits, causing clip
distances 4-7 not to be written correctly.
Fixes piglit test vs-clip-vertex-01.shader_test
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 4176025d463e7733dac19788b45b6472b65d62d4 |
|
08-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_FIXED vertex attributes.
This sadly requires work in the VS to rescale them, because the
hardware doesn't support this format natively.
Fixes arb_es2_compatibility-fixed-type and gtf/fixed_data_type.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 8832920c298f4e13ffd5e53feeba509be69edb16 |
|
27-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge URB space partitioning, including push constants.
Currently this always reserves 16kB for push constants, regardless of
how much space is needed, and partitions it evenly betwen the VS and FS.
This is probably not ideal, but is straightforward.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 5936d96d33e767aa99f6afa92f2a6582ff04df23 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move IF stack handling into the EU abstraction layer/brw_compile.
This hides the IF stack and back-patching of IF/ELSE instructions from
each of the code generators, greatly simplifying the interface.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 484b51d484e52836bd2d2ded64626342203df0d3 |
|
30-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Align interleaved URB writes for overflow outputs as well.
Fixes glsl-max-varyings.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35614
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| d22e2ebe35ef9d33ec5f7a67f903f36bcd9fbc91 |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_color_buffer_float.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 3f7318c1b8d2ad4f4aef66362cdb7b9e8dc89eac |
|
13-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add comments about URB size units and limits.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 2279156fe7ac9718533b8b0de90ae96100486680 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename brw_(IF|CONT)_gen6 functions to gen6_(IF|CONT).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 6c324777a685d28d0a81d23157e4863240552999 |
|
01-Mar-2011 |
Zou Nan hai <nanhai.zou@intel.com> |
i965: bump VS thread number to 60 on SNB
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9351ef7a4418f5c1bb95a8f2016af0a15fa97679 |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: When MOVing to produce ABS, strip negate of the operand.
We were returning the negative absolute value, instead of the absolute
value. Fixes glsl-vs-abs-neg.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 1d1ad6306d0d55b6ba97d9ecc730d5f919d55df5 |
|
07-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Avoid double-negation of immediate values in the VS.
In general, we have to negate in immediate values we pass in because
the src1 negate field in the register description is in the bits3 slot
that the 32-bit value is loaded into, so it's ignored by the hardware.
However, the src0 negate field is in bits1, so after we'd negated the
immediate value loaded in, it would also get negated through the
register description. This broke this VP instruction in the position
calculation in civ4:
MAD TEMP[1], TEMP[1], CONST[256].zzzz, CONST[256].-y-y-y-y;
Bug #30156
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 82493216044b0320219fc631baa7b02381daa0de |
|
24-Dec-2010 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fix register region description
This fixes
brw_eu_emit.c:179: validate_reg: Assertion `width == 1' failed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 7cec7bf56c1b8aa03800e01fa06f29a02edae755 |
|
13-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix ARL to work on gen6.
RNDD isn't one of the instructions that can do conversion from
execution type to destination type.
Fixes glsl-vs-arrays-3.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e47eacdc53aec6743c42c8d9ab8298f802161733 |
|
10-Dec-2010 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: support for two-sided lighting on Sandybridge
VS places color attributes together so that SF unit can fetch the right
attribute according to object orientation. This fixes light issue in
mesa demo geartrain, projtex.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 3a3b1bd722786ab0b1386a3a505cadfa89798232 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 reladdr VS constant loading.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 15566183a64ef3f9940962a3b08b1c3469c98566 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 constant-index constant loading.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 8fab1c0e2e0610813dfaa7fbc83662ec0f3a049c |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix VS constants regression pre-gen6.
Last minute change for gen6 with 0 used params dropped the multiply.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 05e534e6c4395269b1ca3a9694a1f437363dd186 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Drop push-mode reladdr constant loading and always use constant_map.
This eases the gen6 implementation, which can only handle up to 32
registers of constants, while likely not penalizing real apps using
reladdr since all of those I've seen also end up hitting the pull
constant buffer. On gen6, the constant map means that simple NV VPs
fit under the 32-reg limit and now succeed. Fixes around 10 testcases.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| fa0d5a2c5bfb6109d365a6f0b9bee53dfee50325 |
|
07-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Always hand the absolute value to RSQ.
gen6 builtin RSQ apparently clamps negative values to 0 instead of
returning the RSQ of the absolute value like ARB_fragment_program
desires and pre-gen6 apparently does.
Fixes:
glean/fp1-RSQ test 2 (reciprocal square root of negative value)
glean/vp1-RSQ test 2 (reciprocal square root of negative value)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f361f8a8a9a71d84fc569445902adacc2f2cc069 |
|
02-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for loops in the VS.
This follows the changes done for the FS alongside the EU emit code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| c530fd3f8a5b5ac6918dece5d9083b2fac4ef78e |
|
01-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: also using align1 mode for math2 on sandybridge
Like Eric's workaround patch of commit 490c23ee6be2e8531b5a14d42f808de83d401130.
This forces to align1 mode for math2 too.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| a889f9ee5cccee031c1090a6ef92cba894b1d77c |
|
24-Nov-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Don't write mrf assignment for pointsize output
https://bugs.freedesktop.org/show_bug.cgi?id=31894
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| df24450bac404e2acd9569340dacc6e537fb919c |
|
15-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the new embedded compare in SEL on gen6 for VS MIN and MAX opcodes.
Cuts the extra CMP instruction that used to precede SEL.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 490c23ee6be2e8531b5a14d42f808de83d401130 |
|
10-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Work around strangeness in swizzling/masking of gen6 math.
Sometimes we swizzled in a different channel it looked like, and
sometimes we swizzled in zero. Or something.
Having looked at the output of another code generator for this chip,
this is approximately what they do, too: use align1 math on
temporaries, and then move the results into place.
Fixes:
glean/vp1-EX2 test
glean/vp1-EXP test
glean/vp1-LG2 test
glean/vp1-RCP test (reciprocal)
glean/vp1-RSQ test 1 (reciprocal square root)
shaders/glsl-cos
shaders/glsl-sin
shaders/glsl-vs-masked-cos
shaders/vpfp-generic/vp-exp-alias
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 65972f992f2b5505cc568a3fa29254e8d25c3042 |
|
10-Nov-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
Revert "i965: VS use SPF mode on sandybridge for now"
This reverts commit 9c39a9fcb2c76897e9b5aff68ce197a411c4e25c.
Remove VS SPF mode, conditional instruction works for VS now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e30a3e7aa09c373c0a02df555d090693718f0fe8 |
|
27-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add user clip planes support to gen6.
Fixes piglit user-clip, and compiz desktop switching when dragging a
window and using just 2 desktops. Bug #30446.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 022531209d1575b5c1cd84070757521566f856b7 |
|
18-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Assert out on gen6 VS constant buffer reads that hang the GPU for now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 17306c60ad61f5096010d210f5d3f6d0b3a99dad |
|
11-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't compute-to-MRF in gen6 VS math.
There was code to do this for pre-gen6 already, this just enables it
for gen6 as well.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9c39a9fcb2c76897e9b5aff68ce197a411c4e25c |
|
17-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: VS use SPF mode on sandybridge for now
Until conditional instructions were fixed, use SPF mode instead for now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| fa589770e8829f02d2742c32d05eecde0b70fe80 |
|
17-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fix point size setting in header on sandybridge
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 41c31c2ebd5ed2ca021ff9d89f79270562e6c368 |
|
16-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Fix color interpolation on sandybridge
Don't double store position in vertex attribute. This makes color
interpolation right by using barycentric coordinates.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 24c12e6c7f8aa8c2f4c163d23d740b070bfabfc3 |
|
07-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Store the byte address in the VS constant buffer as an integer.
We carefully multiplied our two ints (since we want to be precise
after all) then stored them in a float, which is not specced to really
work, in addition to wasting precision. Fixes
vp-arl-constant-array-huge-* things since the assertions were added.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e432fe09ddb105d4ca5a0654512adc300b0cd22e |
|
04-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: set the source width/stride when handling reladdr dests in the VS.
This is a requirement specified in the docs. No behavior change in
glsl-vs-varying-array.shader_test that violated these requirements.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 5360c48317f5806c7ea8814002e9aac2041960a7 |
|
30-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clear the cached constant buffer entry in the VS at control flow.
Fixes the 7 regressions with constant buffers forced on with piglit -t
glsl (glsl-vs-if-*).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 352dff62f8005add9e71e6b5ba3b3321cb953d73 |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Make brw_CONT and brw_BREAK take the pop count.
We always need to set it, so pass it in.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9629dbf4f2adc42bbc99f3c830be288a7b150f6a |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for destination RelAddr writes in the VS.
Fixes: glsl-vs-varying-array
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 93ba0055c325007656c14ba38302e21be3dc599f |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add AccWrCtl support on Sandybridge.
Whenever the accumulator results are needed, this bit must be set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 8de8c97275e9555183a7e8f2238143657bbe60b2 |
|
19-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the if stack pop count when breaking out of a loop inside an if.
Otherwise, we might end up with the if stack pointing at the wrong
place. Fixes GPU hang with glsl-vs-if-loop.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| bad29dc6dad7ed1bff46c67e61dab01f8d82b557 |
|
19-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't set the swizzle on an immediate value in the VS.
Fixes glsl-vs-if-nested (70.0 is not <= 70.000648 thanks to the
swizzle bits getting set). Some safety checks are added to make sure
this doesn't happen again as we increase the usage of immediate values
in program generation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 147ca9f3fc107b58bd6e1504c997af82a37de5ec |
|
17-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for DP2 in the VS.
Fixes glsl-vs-dot-vec2.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 81996ae8618759cf7fdd033042a96f3014659f6c |
|
10-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: More s/stderr/stdout/ for program debug.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 72fd0568db0ce5f25a1eee0266ec1e7cb3dafab0 |
|
05-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Settle on printing our program debug to stdout.
Mixing stderr (_mesa_print_program, _mesa_print_instruction,
_mesa_print_alu) with stdout means that when writing both to a file,
there isn't a consistent ordering between the two.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| afe125e0a18ac3886c45c7e6b02b122fb2d327b5 |
|
27-Jul-2010 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/master' into glsl2
This pulls in multiple i965 driver fixes which will help ensure better
testing coverage during development, and also gets past the conflicts
of the src/mesa/shader -> src/mesa/program move.
Conflicts:
src/mesa/Makefile
src/mesa/main/shaderapi.c
src/mesa/main/shaderobj.h
|
| 941b893032c9b27ae3b02e1faf9269a464e2b63f |
|
26-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow VS MOVs to use immediate constants.
Clarifies program assembly, and with a little tweak to always use
constant_map, we could cut down on constant buffer payload.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 35bbbf47425244188334a89163191d9f00bdeced |
|
23-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for VS relative addressing of temporary arrays.
Fixes glsl-vs-arrays. Bug #27388.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 86fb92f59c98168d41c7d827f60c12b244f26382 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Avoid extra MOV in VS indirect register reads.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| b69ef5744a5caf5cc169abf47ed2040f7ea8b923 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up VS temporary array access for fixed index offset != 0.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| c686ee0fa7e2298408259f5533b739c7d05c78b8 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: In the VS, multiply the address reg by the appropriate register size.
The ARL value is increments of vec4 in the register file. But
PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved
between the two verts being executed (thus a vec8 each), compared to
PROGRAM_STATE_VAR being packed vec4s.
Fixes:
glsl-vs-arrays-2
glsl-vs-mov-after-deref
(without regressing glsl-vs-arrays-3)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 21eaa62ba461854003e5f74e6fc32e559e9c8455 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 96b11f1e3ee12f06be1d33bf085bf1353f23e667 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Support relative addressed VS constant reads using the appropriate msg.
The previous support was overly complicated by trying to use the same
1-OWORD message for both offsets.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| d0326e0e4ee245ec471fc976fbe98183fbe6da4e |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up dead code from the VS get_constant/get_reladdr_constant split.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 171a25eaba5c29a5f14e472ca1860a6de248c6b2 |
|
21-Jul-2010 |
Carl Worth <cworth@cworth.org> |
i965: Remove an unused variable.
To quiet a compiler warning.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f9d11b8cee235dae42f757e21c2536391c07b3e8 |
|
20-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Mostly fix glsl-max-varyings.
There was confusion on both the size of message we can send, and on
what the URB destination offset means.
The remaining problems appear to be due to spilling of regs in the
fragment shader being broken.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e179fa9a0a0fb3bfd8f4cec998a886dc06f75d0a |
|
20-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up message register setup in emit_vertex_write().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| bdcaaed6ff3238ea4317aff2f7a6947e4a72de9c |
|
20-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't set up VUE space for the disabled user clip distances on gen6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e558786a3ed52222c07f916e213b63dcba1890a2 |
|
01-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for OPCODE_SSG.
The old compiler didn't use SSG, and instead emitted SGT/SGT/SUB. We
can do a little better for SSG than we do for the SGT series.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 36eda76fea02130d30be6a5f0d83f04698da2853 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Dump out the correct shared function for SEND on Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| d05c35914df1c382b90def7e7425d7f2fa4737dc |
|
28-Apr-2010 |
Eric Anholt <eric@anholt.net> |
i965: Implement VS MAX in a more obvious way.
This should be functionally equivalent, with the possible exception of
NaN handling.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 084d8fdd36bbf04520f59fecfad54be0695531f2 |
|
28-Apr-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use immediate float operands for some VS instructions.
We could use this to reduce constant register pressure, but for now it
makes the resulting program assembly much more readable.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 4485dd8a3e8aff8d4fb73684d0d7a5a1179f60cc |
|
18-Apr-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Assert that an OPCODE_IF was seen before an OPCODE_ELSE.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| d163d5fac0eb5e57a2afb77f557525110753359e |
|
19-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove gratuitous jump or nop from OPCODE_END to vertex emit.
Just emit the URB write at END time. Subroutine code that sits after
OPCODE_END won't be executed since we've ended the thread at the point
that the URB write is done.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 25becb8a7a40741afd6df445e6f96433fcb91b36 |
|
16-Mar-2010 |
Eric Anholt <eric@anholt.net> |
Revert "i965: Do VS SGT, SLT, and friends using CMP, SEL instead of CMP, MOV, MOV."
This reverts commit 8ef3b1834a896927bdd4f2aea552cdb732849da9. Fixes
piglit glsl-vs-if.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 8ef3b1834a896927bdd4f2aea552cdb732849da9 |
|
11-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Do VS SGT, SLT, and friends using CMP, SEL instead of CMP, MOV, MOV.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 512d8ca2f34bcaa96e18daace4ae9f95e679471e |
|
11-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up VS DP4 sequences to avoid dependency control.
This is recommended by the B-Spec. I wasn't able to measure any
difference in ETQW.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f6f547d87ea68f44c50a0b0231b7360ca94b2975 |
|
09-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix nested loops in the VS.
We were patching up all the break and continues between the start of
our loop and the end of our loop, even if they were breaks/continues
for an inner loop. Avoiding patching already patched breaks/continues
fixes piglit glsl-vs-loop-nested.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| a3593833dc2c14948c41654ed015c91634a78af3 |
|
02-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up Sandybridge VS sizing.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| c8e5100a3910fd9b36d4424ef94c0581982f0b1a |
|
26-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up the VUE handling for SNB, and hopefully clarify comments.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 1d7aec053b061caef928cfffc786660603d5f14c |
|
26-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Lump SNB in with Ironlake for bigger VUEs.
This gets the VS to the point of accepting vertices. \o/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 38c449409207c8948c1961a3132475bbd422f8f1 |
|
24-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add SNB math opcode support.
This is untested at this point.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| c8f781e0ad6d6516e8763b72d54f21c19f1abc3f |
|
31-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Silence uninitialized variable warning.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| fb4901593c9495714d3f54920a28c271852e2112 |
|
19-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Upload as many VS constants as possible through the push constants.
The pull constants require sending out to an overworked shared unit
and waiting for a response, while push constants are nicely loaded in
for us at thread dispatch time. By putting things we access in every
VS invocation there, ETQW performance improved by 2.5% +/- 1.6% (n=6).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 0714474ae225d12ea00da683785600c0c211f901 |
|
11-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up constbuf handling by splitting reladdr/non-reladdr loads.
The codepaths in the function were almost entirely different.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| c653f5f3872862da396353df63ef93ed86f608fa |
|
11-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Only set up the stack register if it's going to get used.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| d5b964234c37673ec6b444d0a8fa3b823f03fd05 |
|
09-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix loads of non-relative-addr constants after a reladdr load.
Fixes piglit vp-arl-constant-array-huge-overwritten.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| cb3810dd19760797e699c47929f655b829c4d339 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_965 checks with context structure usage.
Saves another 600 bytes or so of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f06c8bd8dd961c9b722759b5d1f8fca78023aba8 |
|
15-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add support for OPCODE_CMP in the VS to fix GLSL sqrt()
Bug #25628. Fixes piglit case glsl-vs-sqrt-zero.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 5606dfb572bf4b89b4882265924705bacc8c182b |
|
18-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'outputswritten64'
Add a GLbitfield64 type and several macros to operate on 64-bit
fields. The OutputsWritten field of gl_program is changed to use that
type. This results in a fair amount of fallout in drivers that use
programs.
No changes are strictly necessary at this point as all bits used are
below the 32-bit boundary. Fairly soon several bits will be added for
clip distances written by a vertex shader. This will cause several
bits used for varyings to be pushed above the 32-bit boundary. This
will affect any drivers that support GLSL.
At this point, only the i965 driver has been modified to support this
eventuality.
I did this as a "squash" merge. There were several places through the
outputswritten64 branch where things were broken. I foresee this
causing difficulties later for bisecting. The history is still
available in the branch.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 91bd593109c71310fb7e101c5f73a14f1bbd5f93 |
|
11-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Avoid moving the current value back into the accumulator for MAD.
This is a 2.9% (+/-.3%) performance win for my GL demo, which hits MAD
sequences for matrix transforms.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 56ab92bad8f1d05bc22b8a8471d5aeb663f220de |
|
10-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Unalias src/dst registers for SGE and friends.
Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/
Bug #22228
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| d52d78b4bcd6d4c0578f972c0b8ebac09e632196 |
|
10-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.
Fixes piglit arl.vp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 7c0152fbaeb21ab423a9de339b85c54d1713432b |
|
10-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Enable loops in the VS.
Passes piglit glsl-vs-loop testcase.
Bug #20171
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 0612ad4f19ecde4963e55551bc316610f97282ae |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Don't set the complete field when there is more VUE yet to come.
This should help with things like lightsmark, but I don't have a testcase
for this commit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 09549704c6579aae2506891d4e9d1c258eab95db |
|
29-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Support PROGRAM_ENV_PARAMs in brw_vs_emit.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9f981ec27dffa562cf743b4690293569477b4553 |
|
07-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Replace the subroutine-skipping jump in VS with a NOP if it's a NOP.
This showed a 1.9% (+/-.3%, n=3) improvement in OA performance with high
geometry settings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 63d7a2f53fb38e170f4e55f2b599e918edf2c512 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix dangerous warning I let slip in.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 78c022acd0b37bf8b32f04313d76255255e769c1 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Respect CondSwizzle in OPCODE_IF.
Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be
useful for the looping code.
Bug #18992
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 7007f8b352763af89805f287153cb7972bff0523 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Emit conditional code updates as required for GLSL VS if statements.
Previously, we'd be branching based on whatever condition code happened to be
laying around.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 1d4bace9fca64c61ccd9f4205262417fa0ae3883 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out,
and running intel-gen4disasm on it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e340d4f9866db4bae391288e83a630a310b0dd2b |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Even if no VS inputs are set, still load some amount of URB as required.
See comment on Vertex URB Entry Read Length for VS_STATE.
This, combined with the previous three commits, fixes #22945.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e93848e595176ae0bad3bfe64e0ca63fd089bb72 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Make sure the VS URB size is big enough to fit a VF VUE.
This fix is just from code and docs inspection, but it may fix hangs on
some applications.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 119eb4094256742013224afb7c5704b6254b6296 |
|
01-Jul-2009 |
Brian Paul <brianp@vmware.com> |
i965: first attempt at handling URB overflow when there's too many vs outputs
If we can't fit all the VS outputs into the MRF, we need to overflow into
temporary GRF registers, then use some MOVs and a second brw_urb_WRITE()
instruction to place the overflow vertex results into the URB.
This is hit when a vertex/fragment shader pair has a large number of varying
variables (12 or more).
There's still something broken here, but it seems close...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 6eb2ca500db940263bfcb9b3ca83f2b5c5431513 |
|
30-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: comments and a new assertion
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e90d6a3cbfdf26b67ccb000265eb529b82c03eb4 |
|
18-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: initial code for loops in vertex programs
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| fd7d764514c540987549c3ea88a2d669b0f0ea58 |
|
18-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: asst clean-ups, etc in brw_vs_emit()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f09e5a5b637822b89ba19b2e306b83f8fc3809d0 |
|
08-May-2009 |
Brian Paul <brianp@vmware.com> |
i965: const qualifiers
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f56893ea173454ed5367eafb038fa4905f9ebce3 |
|
06-May-2009 |
Brian Paul <brianp@vmware.com> |
i965: relAddr local var (to make debug/test a little easier)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| b9196c1fa39dd566c5d7ab340e353b77714edb5f |
|
01-May-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'const-buffer-changes'
Conflicts:
src/mesa/drivers/dri/i965/brw_curbe.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/i965/brw_wm_glsl.c
|
| 777b9ff43e88e456d686208c83712f26aba2dd95 |
|
27-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: only upload constant buffer data when we actually need the const buffer
Make the use_const_buffer field per-program and only call the code which
updates the constant buffer's data if the flag is set.
This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052
(cherry picked from master, commit dc9705d12d162ba6d087eb762e315de9f97bc456)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| dc9705d12d162ba6d087eb762e315de9f97bc456 |
|
27-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: only upload constant buffer data when we actually need the const buffer
Make the use_const_buffer field per-program and only call the code which
updates the constant buffer's data if the flag is set.
This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| ebfbd8c4fef78e3cd9604660e5bb96e3c6df07e5 |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: disable debug printf
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| ac22178eb049126003db40b0a77a111498a12ab7 |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: enable VS constant buffers
In the VS constants can now be handled in two different ways:
1. If there's room in the GRF, put constants there. They're preloaded from
the CURBE prior to VS execution. This is the historical approach. The
problem is the GRF may not have room for all the shader's constants and
temps and misc registers. Hence...
2. Use a separate constant buffer which is read from using a READ message.
This allows a very large number of constants and frees up GRF regs for
shader temporaries. This is the new approach. May be a little slower
than 1.
1 vs. 2 is chosen according to how many constants and temps the shader needs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 0bc214a834bbb12b9338837dd9fca9bc389b4bc2 |
|
18-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i915: fix broken indirect constant buffer reads
The READ message's msg_control value can be 0 or 1 to indicate that the
Oword should be read into the lower or upper half of the target register.
It seems that the other half of the register gets clobbered though. So
we read into two dest registers then use a MOV to combine the upper/lower
halves.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f8f23e33c21f41756d068b546f2aae37030b5773 |
|
16-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: updated CURBE allocation code
Now that we have real constant buffers, the demands on the CURBE are lessened.
When we use real VS/WM constant buffers we only use the CURBE for clip planes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| eb0d46490332091b2ee247f32a1f08a04e1fe00f |
|
17-Apr-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'register-negate'
|
| ee32e9b4753eca62e360f96ce61ef7ff683e6bb7 |
|
16-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement relative addressing for VS constant buffer reads
A scatter-read should be possible, but we're just using two READs for
the time being.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 19ac3e2729abd85346f88fd69c6bc72938d26101 |
|
15-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: handle address reg in get_dst()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f2cfbfa2baa15c4b56c6f22dbe37d75a3c07e549 |
|
15-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix const buffer temp register clobbering
Calls to release_tmps() were causing the temps holding constants to get
recycled.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 7db7ff878d3e5a6b345228e6eaee4797bb68b360 |
|
15-Apr-2009 |
Brian Paul <brianp@vmware.com> |
mesa: merge the prog_src_register::NegateBase and NegateAbs fields
There's really no need for two negation fields. This came from the
GL_NV_fragment_program extension. The new, unified Negate bitfield applies
after the absolute value step.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 92cc9970039d9c9385dc472fbfac58b93799f5ae |
|
15-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix VS constant buffer reads
This mostly came down to finding the right MRF incantation in the
brw_dp_READ_4_vs() function.
Note: this feature is still disabled (but getting close to done).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| cafea7528052624c8d3e4cd1c5b26a61bf04d1d0 |
|
14-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: checkpoint commit: VS constant buffers
Hook up a constant buffer, binding table, etc for the VS unit.
This will allow using large constant buffers with vertex shaders.
The new code is disabled at this time (use_const_buffer=FALSE).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 7709b26e6b615f4e5ace765110eb53ce713b0d6c |
|
24-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: formatting clean-ups
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9f146943ec3893c9aed1754a59eec45f37ca65cd |
|
23-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: whitespace changes, comments
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 460ee86d60112aa6417fbedb41dfe22a51e53927 |
|
13-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: debug code, use gl_register_file type
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| c51c822ee02cb47ddba46da668577d51b7c02831 |
|
14-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: rewrite the code for handling shader subroutine calls
Previously, the prog_instruction::Data field was used to map original Mesa
instructions to brw instructions in order to resolve subroutine calls. This
was a rather tangled mess. Plus it's an obstacle to implementing dynamic
allocation/growing of the instruction buffer (it's still a fixed size).
Mesa's GLSL compiler emits a label for each subroutine and CAL instruction.
Now we use those labels to patch the subroutine calls after code generation
has been done. We just keep a list of all CAL instructions that needs patching
and a list of all subroutine labels. It's a simple matter to resolve them.
This also consolidates some redundant post-emit code between brw_vs_emit.c and
brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data
fields at the end.
Plus, a bunch of new comments.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 74b6d55864b9264323a09856781f655e453b182b |
|
14-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: add missing break for OPCODE_RET case
This doesn't effect correctness, but we were emitting an extraneous ADD.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 14321fcfde9e30d0b9f15aab3c9a057271ae6295 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Delete old metaops code now that there are no remaining consumers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| fc3971d80051b34836716579fd060dbb122d036b |
|
09-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove gratuitous whitespace in INTEL_DEBUG=wm output.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 8112c9e2cc5b27a2b7fd1641c03d3660f992dabf |
|
07-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Note when we drop saturate mode on the floor in a VP.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f53d9913ac8efa5cefa428eb21f91298aca78293 |
|
07-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add support for LRP in VPs.
Bug #19226.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 0d797365deb579cfeb2a32f21692515eb6904921 |
|
05-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement OPCODE_TRUNC (round toward zero) on vertex path.
Also, fix some RNDD vs. RNDZ confusion elsewhere.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| e262da804014d57156346ff487904ce220974832 |
|
01-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix comment
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 131ac5b465d1f676ca2e592e4fecfcbc14b23b49 |
|
01-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement OPCODE_NRM3/NRM4
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 23b0ad4d7e9130a07fec1e968777dfa59bc1d54e |
|
01-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: whitespace, comment changes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 7e04272690e8d9deecc0bf71c37bfa4c321ae6ab |
|
18-Dec-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
965 / GLSL: Use full precision for EXP instruction
The partial precision mode doesn't have quite enough bits of precision
to pass conformance tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 4be624d693554ad3950afab90e331a6725cc5004 |
|
02-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Clean up stale NDC comment.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9fd4c27ae3e189df804b86843a6aad0e70640533 |
|
02-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Avoid vs header computation for negative rhw on G4X.
This cuts one MOV out when setting a zero header.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 34b1776e8d965605d12807884c9c447214d57281 |
|
02-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Merge GM45 into the G4X chipset define.
The mobile and desktop chipsets are the same, and having them separate is
more typing and more chances to screw up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 561787e69759ed757edb897c027d2d94beac8d11 |
|
25-Sep-2008 |
Sam Hocevar <sam@zoy.org> |
i965: support for sin() and cos() in vertex shaders.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 831bfb9053a6e1f065fc07f9f25ae0ea27053733 |
|
23-Sep-2008 |
Sam Hocevar <sam@zoy.org> |
i965: more meaningful message for unsupported opcodes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| be30fddc7c6d0a75cf0777cf24591c3a6439e2c6 |
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30-Jul-2008 |
Krzysztof Czurylo <krzysztof.czurylo@intel.com> |
965: Fix color clamping issues
Patch is correctly applied this time.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 1a244cd9e29e0163a3d68cc30cc6f4a81a9ea96d |
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30-Jul-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Formatting changes to ease application of patches
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 6118d830a63d1637587671bdfa9810f3e31c24e7 |
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24-Jul-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Revert "965: Fix color clamping issues"
This reverts commit b993d539a76e7f1446890a85e4b61deec4d4162d. The
patch was applied incorrectly. Actual fix coming soon. Sorry for the
noise.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| b993d539a76e7f1446890a85e4b61deec4d4162d |
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21-Jul-2008 |
Pawel Pieczul <Pawel.Pieczul@intel.com> |
965: Fix color clamping issues
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 92c075eeb7c330ea420400d1c2bae57356b19f03 |
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08-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: official name for GM45 chipset
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 08f9b190a798c9c61ae07208345d0c2b37e54d39 |
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17-Apr-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
Revert "[i965] renable regative rhw test"
This reverts commit 3158e981f5f37768e9b04765704b9eaece8b899b.
rhw issue has gone away on IGD.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 3158e981f5f37768e9b04765704b9eaece8b899b |
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31-Jan-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] renable regative rhw test
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
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29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 9bae03a583fc6d2d0b916961279abe9156078d1e |
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17-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Fix inversion of SLT/SGE results in vertex programs.
The WM code had this right, so copy its behavior. This reverts a flipping
of the arguments to SLT in brw_vs_tnl which came in with the GLSL code that
probably occurred to work around the flipped results, and brings the code back
in line with t_vp_build.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| d0ebdca4fa70506107a318e6cfd03f0fb4297897 |
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29-Dec-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fix fd.o bug #13847
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 6ef27b88e6f767cd476676b33cb7c4ea6922234e |
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26-Oct-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Merge branch '965-glsl'
Conflicts:
src/mesa/drivers/dri/i965/brw_sf.h
src/mesa/drivers/dri/i965/intel_context.c
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| 25bda451bbdbc51a7a4346e2c809f335fb46db72 |
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18-Sep-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fix double free in 965-glsl branch
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| acfeb3b6ea93bcb5b18e6f51a0727e39da608d76 |
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11-Sep-2007 |
Brian <brian.paul@tungstengraphics.com> |
Fix-up #includes to remove some -I options.
eg: #include "shader/program.h" and remove -I$(TOP)/src/mesa/program
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 46ac4531966e0edf802919def935c4125342e8bf |
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02-Aug-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Fix typo in logic for unalias2()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 285b326c606e9b2f90e4fe177b15b3fa23239b86 |
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04-Jul-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fix issue with output as src register.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 4fc02ad000a0948ab77306980492924f5beebc0a |
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03-Jul-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Fix a nasty bug...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| d19d0596daf004b56d80f78fa1a329b43c2ebf94 |
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21-Jun-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support branch and loop in pixel shader
most of the sample working with some small modification
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 58eac1bbf320b4104c3158aaeca4726f1a59daf9 |
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09-May-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Support loop, conditional update fix
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| a78b26fff04026a24189ecad7ec85bfe0df2cce1 |
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30-Apr-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support nested function call
else instruction fix.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| 35707dbe57873adb5a8088cd47c13bd216e143e4 |
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12-Apr-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Initial 965 GLSL support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 064ae479a770bf434958d673baf6f7530f642697 |
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23-Feb-2007 |
Brian <brian@yutani.localnet.net> |
Update DRI drivers for new glsl compiler.
Mostly:
- update #includes
- update STATE_* token code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| f2eb6434ab1cf72e938956c82d2f530368a6be4a |
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31-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
cleanup code, compiles with vbo changes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 496f9ddf351bd91ea17c257f94e3504e87992202 |
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05-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
eliminate rhw divide under some circumstances
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 72e810db9db663dd3ff5f746d942423d87928e86 |
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12-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Disassemble active program when DEBUG_VS is set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 6ec2d37ae80cc8b99e8ab2705aac4d9dd574f77e |
|
01-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Catch a few more cases of using a message reg as an instruction source
arg.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
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| db0e53af74beafa0ba07b200396bfe12fa9f5c89 |
|
01-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
fix a couple of cases where a message reg is used as an instruction source.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vs_emit.c
|