Searched defs:DstReg (Results 1 - 25 of 56) sorted by relevance

123

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp52 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, argument
56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
H A DR600ExpandSpecialInstrs.cpp96 unsigned DstReg = MI.getOperand(0).getReg(); local
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0);
125 unsigned DstBase = TRI.getHWRegIndex(DstReg);
126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
H A DAMDGPUInstrInfo.cpp37 unsigned &SrcReg, unsigned &DstReg,
36 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp52 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, argument
56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
H A DR600ExpandSpecialInstrs.cpp96 unsigned DstReg = MI.getOperand(0).getReg(); local
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0);
125 unsigned DstBase = TRI.getHWRegIndex(DstReg);
126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
/external/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp85 unsigned DstReg = MI->getOperand(0).getReg(); local
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
93 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
111 if (DstReg != InsReg) {
123 // Implicitly define DstReg for subsequent uses.
126 CopyMI->addRegisterDefined(DstReg);
H A DOptimizePHIs.cpp87 unsigned DstReg = MI->getOperand(0).getReg(); local
100 if (SrcReg == DstReg)
130 unsigned DstReg = MI->getOperand(0).getReg(); local
131 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg),
H A DRegisterCoalescer.h31 /// DstReg - The register that will be left after coalescing. It can be a
33 unsigned DstReg; member in class:llvm::CoalescerPair
38 /// DstIdx - The sub-register index of the old DstReg in the new coalesced
52 /// Flipped - True when DstReg and SrcReg are reversed from the original
56 /// NewRC - The register class of the coalesced register, or NULL if DstReg
58 /// SrcReg and DstReg.
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
78 /// because DstReg i
[all...]
H A DPeepholeOptimizer.cpp150 unsigned SrcReg, DstReg, SubIdx; local
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
154 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
162 // Ensure DstReg can get a register class that actually supports
164 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
181 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
264 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
277 // About to add uses of DstReg, clear DstReg's kill flags.
279 MRI->clearKillFlags(DstReg);
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp131 // DstReg = LDriw_pred [R30], ofst.
132 int DstReg = MI->getOperand(0).getReg(); local
133 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
154 DstReg).addReg(HEXAGON_RESERVED_REG_2);
163 DstReg).addReg(HEXAGON_RESERVED_REG_2);
169 DstReg).addReg(HEXAGON_RESERVED_REG_2);
H A DHexagonPeephole.cpp141 unsigned DstReg = Dst.getReg(); local
144 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
149 PeepholeMap[DstReg] = SrcReg;
163 unsigned DstReg = Dst.getReg(); local
165 PeepholeMap[DstReg] = SrcReg;
180 unsigned DstReg = Dst.getReg(); local
182 PeepholeDoubleRegsMap[DstReg] =
192 unsigned DstReg = Dst.getReg(); local
195 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
200 PeepholeMap[DstReg]
215 unsigned DstReg = Dst.getReg(); local
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp143 unsigned DstReg = MI.getOperand(0).getReg(); local
145 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
146 .addReg(DstReg).addImm(-Offset);
148 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
149 .addReg(DstReg).addImm(Offset);
/external/chromium_org/third_party/mesa/src/src/mesa/main/
H A Datifragshader.h56 struct atifragshader_dst_register DstReg[2]; member in struct:atifs_instruction
/external/llvm/lib/Target/R600/
H A DR600ExpandSpecialInstrs.cpp99 unsigned DstReg; local
102 DstReg = MI.getOperand(Chan).getReg();
104 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
107 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
128 unsigned DstReg; local
131 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
133 DstReg = MI.getOperand(Chan-2).getReg();
136 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
156 unsigned DstReg = MI.getOperand(0).getReg(); local
160 TRI.getSubReg(DstReg, TR
175 unsigned DstReg = MI.getOperand(0).getReg(); local
245 unsigned DstReg = MI.getOperand( local
[all...]
H A DR600InstrInfo.cpp81 unsigned DstReg, int64_t Imm) const {
84 MIB.addReg(DstReg, RegState::Define);
1090 unsigned DstReg,
1094 DstReg); // $dst
1167 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1182 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1212 unsigned DstReg,
1214 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
80 getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const argument
H A DSIInstrInfo.cpp200 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, argument
204 MIB.addReg(DstReg, RegState::Define);
H A DAMDGPUIndirectAddressing.cpp106 unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass); local
108 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY), DstReg)
111 RegisterAddressMap[DstReg] = Address;
112 LiveAddressRegisterMap[Address] = DstReg;
121 unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass); local
122 MOV.addReg(DstReg, RegState::Define | RegState::Implicit);
123 RegisterAddressMap[DstReg] = Addr;
124 LiveAddressRegisterMap[Addr] = DstReg;
H A DAMDGPUInstrInfo.cpp38 unsigned &SrcReg, unsigned &DstReg,
37 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument
H A DR600OptimizeVectorRegisters.cpp186 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); local
192 DstReg)
206 SrcVec = DstReg;
/external/mesa3d/src/mesa/main/
H A Datifragshader.h56 struct atifragshader_dst_register DstReg[2]; member in struct:atifs_instruction
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_program.h79 struct rc_dst_register DstReg; member in struct:rc_sub_instruction
/external/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp117 unsigned DstReg = MI->getOperand(0).getReg(); local
121 if (Uses.count(DstReg) || Defs.count(SrcReg))
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp47 unsigned DstReg, int Offset, DebugLoc dl,
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
45 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument
H A DXCoreRegisterInfo.cpp246 unsigned DstReg, int64_t Value, DebugLoc dl) const {
254 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
245 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int64_t Value, DebugLoc dl) const argument
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program.h79 struct rc_dst_register DstReg; member in struct:rc_sub_instruction

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