/external/llvm/lib/CodeGen/ |
H A D | LiveRegMatrix.cpp | 72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 74 << " to " << PrintReg(PhysReg, TRI) << ':'); 76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 77 MRI->setPhysRegUsed(PhysReg); 78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 87 unsigned PhysReg = VRM->getPhys(VirtReg.reg); local 89 << " from " << PrintReg(PhysReg, TRI) << ':'); 91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 100 unsigned PhysReg) { 111 // The BitVector is indexed by PhysReg, no 99 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 117 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 136 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument [all...] |
H A D | RegisterClassInfo.cpp | 97 unsigned PhysReg = RawOrder[i]; local 99 if (Reserved.test(PhysReg)) 101 unsigned Cost = TRI->getCostPerUse(PhysReg); 104 if (CSRNum[PhysReg]) 105 // PhysReg aliases a CSR, save it for later. 106 CSRAlias.push_back(PhysReg); 110 RCI.Order[N++] = PhysReg; 119 unsigned PhysReg = CSRAlias[i]; local 120 unsigned Cost = TRI->getCostPerUse(PhysReg); 123 RCI.Order[N++] = PhysReg; [all...] |
H A D | RegisterCoalescer.h | 68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | InterferenceCache.cpp | 38 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { argument 39 unsigned E = PhysRegEntries[PhysReg]; 40 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { 56 Entries[E].reset(PhysReg, LIUArray, TRI, MF); 57 PhysRegEntries[PhysReg] = E; 71 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) 82 PhysReg = physReg; 88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 97 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { 168 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { [all...] |
H A D | LiveRangeCalc.cpp | 137 unsigned PhysReg) { 154 if (findReachingDefs(LI, KillMBB, Kill, PhysReg)) 176 unsigned PhysReg) { 196 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) && 197 !MBB->isLiveIn(PhysReg)) { 135 extend(LiveInterval *LI, SlotIndex Kill, unsigned PhysReg) argument 173 findReachingDefs(LiveInterval *LI, MachineBasicBlock *KillMBB, SlotIndex Kill, unsigned PhysReg) argument
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H A D | RegAllocBasic.cpp | 113 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 167 // Spill or split all live virtual registers currently unified under PhysReg 170 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument 177 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 189 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << 193 // Spill each interfering vreg allocated to PhysReg or an alias. 231 while (unsigned PhysReg = Order.next()) { 232 // Check for interference in PhysReg 233 switch (Matrix->checkInterference(VirtReg, PhysReg)) { 235 // PhysReg i [all...] |
H A D | InterferenceCache.h | 39 /// of PhysReg in all basic blocks. 41 /// PhysReg - The register currently represented. 42 unsigned PhysReg; member in class:llvm::InterferenceCache::Entry 63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg. 85 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have 96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {} 100 PhysReg = 0; 106 unsigned getPhysReg() const { return PhysReg; } 146 // get - Get a valid entry for PhysReg. 147 Entry *get(unsigned PhysReg); 192 setPhysReg(InterferenceCache &Cache, unsigned PhysReg) argument [all...] |
H A D | MachineRegisterInfo.cpp | 408 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, argument 410 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 414 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
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H A D | VirtRegMap.cpp | 246 // assigned PhysReg must be marked as live-in to those blocks. 247 unsigned PhysReg = VRM->getPhys(VirtReg); local 248 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); 256 if (!LiveIn[i]->isLiveIn(PhysReg)) 257 LiveIn[i]->addLiveIn(PhysReg); 287 unsigned PhysReg = VRM->getPhys(VirtReg); local 288 assert(PhysReg != VirtRegMap::NO_PHYS_REG && 290 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); 298 SuperKills.push_back(PhysReg); 309 SuperDeads.push_back(PhysReg); [all...] |
H A D | RegAllocFast.cpp | 73 unsigned PhysReg; // Currently held here. member in struct:__anon21172::RAFast::LiveReg 78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {} 124 void markRegUsedInInstr(unsigned PhysReg) { argument 125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 130 bool isRegUsedInInstr(unsigned PhysReg) const { 131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 178 unsigned calcSpillCost(unsigned PhysReg) const; 179 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg); 186 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg); 345 unsigned PhysReg = MO.getReg(); local 399 definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState) argument 490 assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) argument 499 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument 539 unsigned PhysReg = *I; local 663 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument 737 unsigned PhysReg = LRI->PhysReg; local 760 unsigned PhysReg = LRI->PhysReg; local 965 unsigned PhysReg = LRI->PhysReg; local 1021 unsigned PhysReg = LRI->PhysReg; local [all...] |
H A D | RegAllocGreedy.cpp | 185 unsigned PhysReg; member in struct:__anon21176::RAGreedy::GlobalSplitCandidate 190 // Interference for PhysReg. 198 PhysReg = Reg; 218 /// Candidate info for for each PhysReg in AllocationOrder. 264 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg); 460 unsigned PhysReg; local 461 while ((PhysReg = Order.next())) 462 if (!Matrix->checkInterference(VirtReg, PhysReg)) 464 if (!PhysReg || Order.isHint()) 465 return PhysReg; 501 unsigned PhysReg; local 558 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument 640 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<LiveInterval*> &NewVRegs) argument [all...] |
H A D | MachineBasicBlock.cpp | 346 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { argument 348 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg"); 353 bool LiveIn = isLiveIn(PhysReg); 361 if (I->getOperand(1).getReg() == PhysReg) { 371 .addReg(PhysReg, RegState::Kill); 373 addLiveIn(PhysReg);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 113 unsigned &PhysReg, int &Cost) { 126 PhysReg = Reg; 468 unsigned PhysReg = 0; 471 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 472 assert((PhysReg == 0 || !isChain) && 480 PhysReg = 0; 489 : SDep(OpSU, SDep::Data, PhysReg); 110 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
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H A D | SelectionDAGBuilder.cpp | 5776 std::pair<unsigned, const TargetRegisterClass*> PhysReg = local 5786 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5790 MVT RegVT = *PhysReg.second->vt_begin(); 5815 if (unsigned AssignedReg = PhysReg.first) { 5816 const TargetRegisterClass *RC = PhysReg.second; 5848 if (const TargetRegisterClass *RC = PhysReg.second) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 457 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. 461 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { argument 463 assert(PhysReg < (1u << 30) && "Not a physical register"); 464 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); 467 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. 468 bool clobbersPhysReg(unsigned PhysReg) const { 469 return clobbersPhysReg(getRegMask(), PhysReg);
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