Searched refs:AArch64 (Results 1 - 23 of 23) sorted by relevance

/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64ELFObjectWriter.cpp1 //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
62 case AArch64::fixup_a64_ld_prel:
65 case AArch64::fixup_a64_adr_prel:
68 case AArch64::fixup_a64_adr_prel_page:
71 case AArch64::fixup_a64_adr_prel_got_page:
74 case AArch64::fixup_a64_tstbr:
77 case AArch64::fixup_a64_condbr:
80 case AArch64::fixup_a64_uncondbr:
83 case AArch64::fixup_a64_call:
86 case AArch64
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H A DAArch64AsmBackend.cpp1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
10 // This file contains the AArch64 implementation of the MCAsmBackend class,
69 if ((uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_page ||
70 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_got_page ||
71 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_gottprel_page ||
72 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_tlsdesc_adr_page)
94 return AArch64::NumTargetFixupKinds;
98 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
256 case AArch64::fixup_a64_ld_gottprel_prel19:
259 case AArch64
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H A DAArch64MCCodeEmitter.cpp1 //=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code =//
65 template<AArch64::Fixups fixupDesired>
155 static const unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_lo12,
156 AArch64::fixup_a64_ldst16_lo12,
157 AArch64::fixup_a64_ldst32_lo12,
158 AArch64::fixup_a64_ldst64_lo12,
159 AArch64::fixup_a64_ldst128_lo12 };
166 FixupKind = AArch64::fixup_a64_ld64_got_lo12_nc;
170 AArch64
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H A DAArch64MCTargetDesc.cpp1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions -------------===//
10 // This file provides AArch64 specific target descriptions.
56 InitAArch64MCRegisterInfo(X, AArch64::X30);
65 unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
126 if (Inst.getOpcode() == AArch64::Bcc
133 if (Inst.getOpcode() == AArch64::Bcc
141 unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
H A DAArch64FixupKinds.h1 //=- AArch64/AArch64FixupKinds.h - AArch64 Specific Fixup Entries -*- C++ -*-=//
10 // This file describes the LLVM fixups applied to MCInsts in the AArch64
21 namespace AArch64 { namespace in namespace:llvm
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
14 #include "AArch64.h"
38 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64
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H A DAArch64ISelDAGToDAG.cpp1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
10 // This file defines an instruction selector for the AArch64 target.
15 #include "AArch64.h"
29 /// AArch64 specific code to select AArch64 machine instructions for
49 return "AArch64 Instruction Selection";
152 default: llvm_unreachable("Unrecognised AArch64 memory constraint");
205 MOVOpcode = DestWidth == 64 ? AArch64::MOVZxii : AArch64::MOVZwii;
208 MOVOpcode = DestWidth == 64 ? AArch64
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H A DAArch64RegisterInfo.cpp1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
33 : AArch64GenRegisterInfo(AArch64::X30) {
52 if (RC == &AArch64::FlagClassRegClass)
53 return &AArch64::GPR64RegClass;
65 Reserved.set(AArch64::XSP);
66 Reserved.set(AArch64::WSP);
68 Reserved.set(AArch64::XZR);
69 Reserved.set(AArch64::WZR);
72 Reserved.set(AArch64
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H A DAArch64FrameLowering.cpp1 //===- AArch64FrameLowering.cpp - AArch64 Frame Information ---------------===//
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
14 #include "AArch64.h"
89 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
100 unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
114 if (FPNeedsSetting && MBBI->getOpcode() == AArch64::LSPair64_STR
115 && MBBI->getOperand(0).getReg() == AArch64::X29) {
120 emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
121 AArch64
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H A DAArch64BranchFixupPass.cpp1 //===-- AArch64BranchFixupPass.cpp - AArch64 branch fixup -----------------===//
10 // This file contains a pass that fixes AArch64 branches which have ended up out
16 #include "AArch64.h"
141 return "AArch64 branch fixup pass";
293 case AArch64::TBZxii:
294 case AArch64::TBZwii:
295 case AArch64::TBNZxii:
296 case AArch64::TBNZwii:
300 case AArch64::Bcc:
301 case AArch64
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H A DAArch64RegisterInfo.h1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl -*- C++ -*-===//
10 // This file contains the AArch64 implementation of the MCRegisterInfo class.
52 if (RC == &AArch64::tcGPR64RegClass)
53 return &AArch64::GPR64RegClass;
H A DAArch64ISelLowering.cpp1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
16 #include "AArch64.h"
51 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
52 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
53 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
54 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
55 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
56 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
60 addRegisterClass(MVT::v8i8, &AArch64
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H A DMakefile1 ##===- lib/Target/AArch64/Makefile -------------------------*- Makefile -*-===##
12 TARGET = AArch64
H A DAArch64AsmPrinter.cpp1 //===-- AArch64AsmPrinter.cpp - Print machine code to an AArch64 .s file --===//
11 // of machine-dependent LLVM code to GAS-format AArch64 assembly language.
55 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
61 if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) {
160 if (printModifiedFPRAsmOperand(MO, TRI, AArch64::VPR128RegClass, O))
193 AArch64::GPR32RegClass, O);
198 AArch64::GPR64RegClass, O);
216 AArch64::FPR8RegClass, O);
220 AArch64
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/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
10 // This file contains the functions necessary to decode AArch64 instruction
18 #include "AArch64.h"
39 /// AArch64 disassembler for all AArch64 platforms.
251 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
262 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
273 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
284 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
295 uint16_t Register = getReg(Decoder, AArch64
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/external/clang/lib/CodeGen/
H A DCGBuiltin.cpp1709 if (BuiltinID == AArch64::BI__clear_cache) {
1711 "Variadic __clear_cache slipped through on AArch64");
1748 // AArch64 builtins mapping to legacy ARM v7 builtins.
1751 case AArch64::BI__builtin_neon_vmul_v:
1753 case AArch64::BI__builtin_neon_vmulq_v:
1755 case AArch64::BI__builtin_neon_vabd_v:
1757 case AArch64::BI__builtin_neon_vabdq_v:
1759 case AArch64::BI__builtin_neon_vfma_v:
1761 case AArch64::BI__builtin_neon_vfmaq_v:
1763 case AArch64
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/external/clang/include/clang/Basic/
H A DTargetBuiltins.h24 /// \brief AArch64 builtins
25 namespace AArch64 { namespace in namespace:clang
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
10 // This file contains the (GNU-style) assembly parser for the AArch64
146 /// Instances of this class represent a parsed AArch64 machine instruction.
1540 if (RegNum == AArch64::NoRegister) {
1542 .Case("ip0", AArch64::X16)
1543 .Case("ip1", AArch64::X17)
1544 .Case("fp", AArch64::X29)
1545 .Case("lr", AArch64::X30)
1546 .Default(AArch64::NoRegister);
1548 if (RegNum == AArch64
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/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.h1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
10 // This class prints an AArch64 MCInst to a .s file.
164 return RegNo == AArch64::XSP || RegNo == AArch64::WSP;
H A DAArch64InstPrinter.cpp1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
10 // This class prints an AArch64 MCInst to a .s file.
334 if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP)
399 if (MI->getOpcode() == AArch64::TLSDESCCALL) {
/external/clang/lib/Basic/
H A DTargets.cpp3202 // AArch64 backend supports 64-bit operations at the moment. In principle
3214 // ACLE predefines. Many can only have one possible value on v8 AArch64.
3264 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3327 // There are no AArch64 clobbers shared by all asm statements.
/external/llvm/
H A Dconfigure4032 aarch64*-*) llvm_cv_target_arch="AArch64" ;;
4066 aarch64*-*) host_arch="AArch64" ;;
5418 AArch64) TARGET_HAS_JIT=0
5665 all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600" ;;
5672 aarch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
5690 AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
/external/llvm/projects/sample/
H A Dconfigure3847 aarch64*-*) llvm_cv_target_arch="AArch64" ;;
5105 AArch64) TARGET_HAS_JIT=0
5303 all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600" ;;
5310 aarch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
5328 AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;

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