| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCallingConvLower.h | 49 bool IsVarArg; member in class:llvm::Hexagon_CCState
67 bool isVarArg() const { return IsVarArg; }
|
| H A D | HexagonCallingConvLower.cpp | 30 : CallingConv(CC), IsVarArg(isVarArg), TM(tm), Locs(locs), Context(c) {
|
| H A D | HexagonISelLowering.cpp | 393 bool isVarArg = CLI.IsVarArg;
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.h | 111 CallingConv::ID CallConv, bool IsVarArg,
116 CallingConv::ID CallConv, bool IsVarArg,
|
| H A D | SparcISelLowering.cpp | 164 CallingConv::ID CallConv, bool IsVarArg,
169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
175 CallingConv::ID CallConv, bool IsVarArg,
185 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
238 CallingConv::ID CallConv, bool IsVarArg,
246 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
315 bool IsVarArg,
321 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
323 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, In
163 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
174 LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
237 LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
313 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
531 LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 157 bool IsVarArg; member in class:llvm::CCState
233 bool isVarArg() const { return IsVarArg; }
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 167 CallingConv::ID CallConv, bool IsVarArg,
183 bool IsVarArg,
|
| H A D | AArch64ISelLowering.cpp | 1146 bool IsVarArg = CLI.IsVarArg; local
1157 IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1167 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1395 IsVarArg, Ins, dl, DAG, InVals);
1400 CallingConv::ID CallConv, bool IsVarArg,
1406 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1446 bool IsVarArg,
1485 assert((!IsVarArg || CalleeCC == CallingConv::C)
1488 if (IsVarArg
1399 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1444 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, bool IsCalleeStructRet, bool IsCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.cpp | 72 bool IsVarArg = MF.getFunction()->isVarArg(); local
78 if (IsVarArg)
134 bool IsVarArg = MF.getFunction()->isVarArg(); local
160 if (IsVarArg) {
194 if (IsVarArg)
|
| H A D | SystemZISelLowering.h | 169 CallingConv::ID CallConv, bool IsVarArg,
|
| H A D | SystemZISelLowering.cpp | 575 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, argument
589 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
650 if (IsVarArg) {
704 bool IsVarArg = CLI.IsVarArg; local
713 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
817 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
840 CallingConv::ID CallConv, bool IsVarArg,
848 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
839 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
|
| /external/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 29 : CallingConv(CC), IsVarArg(isVarArg), MF(mf), TM(tm),
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2337 bool IsVarArg = CLI.IsVarArg; local
2346 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2352 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
2519 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
2527 CallingConv::ID CallConv, bool IsVarArg,
2535 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2566 bool IsVarArg,
2582 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2700 if (IsVarArg)
2526 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SDNode *CallNode, const Type *RetTy) const argument
2564 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2719 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
2730 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
3146 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, std::vector<ArgListEntry> &FuncArgs) argument
[all...] |
| H A D | MipsISelLowering.h | 253 bool IsVarArg, bool IsSoftFloat,
|
| /external/llvm/include/llvm/Target/ |
| H A D | TargetLowering.h | 1897 bool IsVarArg : 1;
1924 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()),
1940 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 500 bool is64Bit, bool IsVarArg, bool TailCallOpt);
|
| H A D | X86ISelLowering.cpp | 2480 bool isVarArg = CLI.IsVarArg;
3369 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3370 if (IsVarArg)
3368 isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool TailCallOpt) argument
|
| /external/llvm/include/llvm-c/ |
| H A D | Core.h | 794 LLVMBool IsVarArg);
|
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 289 bool isVarArg = CLI.IsVarArg;
|
| /external/llvm/lib/IR/ |
| H A D | Core.cpp | 307 LLVMBool IsVarArg) {
309 return wrap(FunctionType::get(unwrap(ReturnType), Tys, IsVarArg != 0));
305 LLVMFunctionType(LLVMTypeRef ReturnType, LLVMTypeRef *ParamTypes, unsigned ParamCount, LLVMBool IsVarArg) argument
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 860 bool isVarArg = CLI.IsVarArg;
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3488 bool isVarArg = CLI.IsVarArg;
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1408 bool isVarArg = CLI.IsVarArg;
|