/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 27 case ISD::SRL: return ARM_AM::lsr;
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/external/chromium_org/third_party/openssl/openssl/crypto/sha/asm/ |
H A D | sha512-mips.pl | 84 $SRL="dsrl"; # shift right logical 98 $SRL="srl"; # shift right logical 159 $SRL $h,$e,@Sigma1[0] 163 $SRL $tmp0,$e,@Sigma1[1] 167 $SRL $tmp0,$e,@Sigma1[2] 174 $SRL $h,$a,@Sigma0[0] 179 $SRL $tmp0,$a,@Sigma0[1] 183 $SRL $tmp0,$a,@Sigma0[2] 210 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i) 213 $SRL [all...] |
H A D | sha512-sparcv9.pl | 59 $SRL="srlx"; # shift right logical 85 $SRL="srl"; # shift right logical 222 $SRL $e,@Sigma1[0],$h !! $i 226 $SRL $e,@Sigma1[1],$tmp0 230 $SRL $e,@Sigma1[2],$tmp0 237 $SRL $a,@Sigma0[0],$h 242 $SRL $a,@Sigma0[1],$tmp0 246 $SRL $a,@Sigma0[2],$tmp0
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 181 { ISD::SRL, MVT::v4i32, 1 }, 184 { ISD::SRL, MVT::v8i32, 1 }, 187 { ISD::SRL, MVT::v2i64, 1 }, 189 { ISD::SRL, MVT::v4i64, 1 }, 194 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized. 195 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized. 229 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. 230 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 231 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 232 { ISD::SRL, MV [all...] |
/external/openssl/crypto/sha/asm/ |
H A D | sha512-mips.pl | 84 $SRL="dsrl"; # shift right logical 98 $SRL="srl"; # shift right logical 159 $SRL $h,$e,@Sigma1[0] 163 $SRL $tmp0,$e,@Sigma1[1] 167 $SRL $tmp0,$e,@Sigma1[2] 174 $SRL $h,$a,@Sigma0[0] 179 $SRL $tmp0,$a,@Sigma0[1] 183 $SRL $tmp0,$a,@Sigma0[2] 210 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i) 213 $SRL [all...] |
H A D | sha512-sparcv9.pl | 59 $SRL="srlx"; # shift right logical 85 $SRL="srl"; # shift right logical 222 $SRL $e,@Sigma1[0],$h !! $i 226 $SRL $e,@Sigma1[1],$tmp0 230 $SRL $e,@Sigma1[2],$tmp0 237 $SRL $a,@Sigma0[0],$h 242 $SRL $a,@Sigma0[1],$tmp0 246 $SRL $a,@Sigma0[2],$tmp0
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/external/libffi/src/mips/ |
H A D | ffitarget.h | 128 # define SRL srl macro 135 # define SRL dsrl
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H A D | n32.S | 119 SRL t4, t6, 1*FFI_FLAG_BITS 132 SRL t4, t6, 2*FFI_FLAG_BITS 145 SRL t4, t6, 3*FFI_FLAG_BITS 158 SRL t4, t6, 4*FFI_FLAG_BITS 171 SRL t4, t6, 5*FFI_FLAG_BITS 184 SRL t4, t6, 6*FFI_FLAG_BITS 197 SRL t4, t6, 7*FFI_FLAG_BITS 219 SRL t6, 8*FFI_FLAG_BITS
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/external/chromium_org/v8/src/mips/ |
H A D | constants-mips.cc | 248 case SRL:
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H A D | constants-mips.h | 310 SRL = ((0 << 3) + 2),
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 306 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon21394
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H A D | MSP430ISelLowering.cpp | 97 setOperationAction(ISD::SRL, MVT::i8, Custom); 100 setOperationAction(ISD::SRL, MVT::i16, Custom); 191 case ISD::SRL: 643 case ISD::SRL: 644 return DAG.getNode(MSP430ISD::SRL, dl, 655 if (Opc == ISD::SRL && ShiftAmount) { 859 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
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/external/v8/src/mips/ |
H A D | constants-mips.cc | 244 case SRL:
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H A D | constants-mips.h | 305 SRL = ((0 << 3) + 2),
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 580 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt); 679 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 808 case ISD::SRL: 1165 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1304 DAG.getNode(ISD::SRL, DL, NVT, InL, 1310 if (N->getOpcode() == ISD::SRL) { 1315 Lo = DAG.getNode(ISD::SRL, DL, 1323 DAG.getNode(ISD::SRL, D [all...] |
H A D | TargetLowering.cpp | 593 if (InOp.getOpcode() == ISD::SRL && 601 Opc = ISD::SRL; 643 case ISD::SRL: 661 unsigned Opc = ISD::SRL; 694 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 726 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 890 case ISD::SRL: 891 // Shrink SRL by a constant if none of the high bits shifted in are 894 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 918 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, d [all...] |
H A D | LegalizeVectorOps.cpp | 64 // Implement expansion for SIGN_EXTEND_INREG using SRL and SRA. 210 case ISD::SRL: 454 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); 703 // Make sure that the SINT_TO_FP and SRL instructions are available. 705 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) 725 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
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H A D | DAGCombiner.cpp | 891 else if (Opc == ISD::SRL) 1132 case ISD::SRL: return visitSRL(N); 1215 case ISD::SRL: 1952 SDValue SRL = DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN, local 1955 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL); 1956 AddToWorkList(SRL.getNode()); 2006 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, 2020 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add); 2164 N1 = DAG.getNode(ISD::SRL, D [all...] |
H A D | LegalizeDAG.cpp | 404 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 797 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, 808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, 1278 case ISD::SRL: 2303 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2324 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2358 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2511 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2516 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2517 Tmp1 = DAG.getNode(ISD::SRL, d [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 376 } else if (Opcode == ISD::SRL) { 423 Op0.getOperand(0).getOpcode() == ISD::SRL) { 425 Op1.getOperand(0).getOpcode() != ISD::SRL) { 431 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 433 Op1.getOperand(0).getOpcode() != ISD::SRL) { 444 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 451 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 1168 case ISD::SRL: {
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/external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/ |
H A D | mips.pl | 62 $SRL="dsrl"; 77 $SRL="srl"; 903 $SRL $at,$a1,$t1 917 $SRL $DH,$a2,4*$BNSZ # bits 925 $SRL $HH,$a0,4*$BNSZ # bits 926 $SRL $QT,4*$BNSZ # q=0xffffffff 933 $SRL $at,$a1,4*$BNSZ # bits 958 $SRL $HH,$a0,4*$BNSZ # bits 959 $SRL $QT,4*$BNSZ # q=0xffffffff 966 $SRL [all...] |
/external/openssl/crypto/bn/asm/ |
H A D | mips.pl | 62 $SRL="dsrl"; 77 $SRL="srl"; 903 $SRL $at,$a1,$t1 917 $SRL $DH,$a2,4*$BNSZ # bits 925 $SRL $HH,$a0,4*$BNSZ # bits 926 $SRL $QT,4*$BNSZ # q=0xffffffff 933 $SRL $at,$a1,4*$BNSZ # bits 958 $SRL $HH,$a0,4*$BNSZ # bits 959 $SRL $QT,4*$BNSZ # q=0xffffffff 966 $SRL [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 576 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 1686 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1687 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1733 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1734 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1774 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1799 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1897 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1899 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1938 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, D 2029 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); local [all...] |
H A D | MipsSEISelLowering.cpp | 72 setTargetDAGCombine(ISD::SRL); 507 case ISD::SRL:
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