| /external/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
198 unsigned SubReg = *SubRegs;
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
221 SubRegs.isValid(); ++SubRegs)
222 PartDefRegs.insert(*SubRegs);
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs
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| H A D | PostRASchedulerList.cpp | 428 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
429 SubRegs.isValid(); ++SubRegs)
430 LiveRegs.set(*SubRegs);
455 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
456 if (LiveRegs.test(*SubRegs)) {
457 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
500 for (MCSubRegIterator SubRegs(Re
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| H A D | RegisterScavenging.cpp | 34 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
35 SubRegs.isValid(); ++SubRegs)
36 RegsAvailable.reset(*SubRegs);
107 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
108 SubRegs.isValid(); ++SubRegs)
109 BV.set(*SubRegs);
220 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs
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| H A D | CriticalAntiDepBreaker.cpp | 204 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
205 SubRegs.isValid(); ++SubRegs)
206 KeepRegs.set(*SubRegs);
250 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
251 unsigned SubregReg = *SubRegs;
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| H A D | MachineInstrBundle.cpp | 174 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
175 unsigned SubReg = *SubRegs;
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| H A D | IfConversion.cpp | 973 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
974 SubRegs.isValid(); ++SubRegs)
975 Redefs.insert(*SubRegs);
993 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
994 SubRegs.isValid(); ++SubRegs)
995 Redefs.erase(*SubRegs);
1006 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs
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| H A D | MachineVerifier.cpp | 95 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
96 RV.push_back(*SubRegs);
453 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
455 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
456 regsReserved.set(*SubRegs);
676 for (MCSubRegIterator SubRegs(*
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| H A D | AggressiveAntiDepBreaker.cpp | 250 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
251 SubRegs.isValid(); ++SubRegs)
252 PassthruRegs.insert(*SubRegs);
317 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
318 unsigned SubregReg = *SubRegs;
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| H A D | BranchFolding.cpp | 138 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
139 SubRegs.isValid(); ++SubRegs)
140 ImpDefRegs.insert(*SubRegs);
1562 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
1563 Uses.erase(*SubRegs); // Use sub-registers to be conservative
|
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
123 "SubRegs and SubRegIndices must have the same size");
213 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
226 return SubRegs;
233 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
252 if (!SubRegs.insert(*SI).second)
265 CodeGenRegister *SR = SubRegs[Idx];
277 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
280 SubRegs
556 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); local
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| H A D | CodeGenRegisters.h | 141 return SubRegs;
234 SubRegMap SubRegs; member in struct:llvm::CodeGenRegister
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 405 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
406 LastDef[*SubRegs] = MI;
|
| /external/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 103 /// register. The SubRegs field is a zero terminated array of registers that
111 uint32_t SubRegs; // Sub-register set, described above member in struct:llvm::MCRegisterDesc
115 // sub-register in SubRegs.
445 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 682 unsigned SubRegs = 0; local
687 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
689 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
692 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
694 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
696 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
698 Opc = ARM::MOVr, BeginIdx = ARM::gsub_0, SubRegs = 2;
701 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
703 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
705 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs
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