1//===-- BuiltinsMips.def - Mips Builtin function database --------*- C++ -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MIPS-specific builtin function database. Users of 11// this file must define the BUILTIN macro to make use of this information. 12// 13//===----------------------------------------------------------------------===// 14 15// The format of this database matches clang/Basic/Builtins.def. 16 17// MIPS DSP Rev 1 18 19// Add/subtract with optional saturation 20BUILTIN(__builtin_mips_addu_qb, "V4ScV4ScV4Sc", "n") 21BUILTIN(__builtin_mips_addu_s_qb, "V4ScV4ScV4Sc", "n") 22BUILTIN(__builtin_mips_subu_qb, "V4ScV4ScV4Sc", "n") 23BUILTIN(__builtin_mips_subu_s_qb, "V4ScV4ScV4Sc", "n") 24 25BUILTIN(__builtin_mips_addq_ph, "V2sV2sV2s", "n") 26BUILTIN(__builtin_mips_addq_s_ph, "V2sV2sV2s", "n") 27BUILTIN(__builtin_mips_subq_ph, "V2sV2sV2s", "n") 28BUILTIN(__builtin_mips_subq_s_ph, "V2sV2sV2s", "n") 29 30BUILTIN(__builtin_mips_madd, "LLiLLiii", "nc") 31BUILTIN(__builtin_mips_maddu, "LLiLLiUiUi", "nc") 32BUILTIN(__builtin_mips_msub, "LLiLLiii", "nc") 33BUILTIN(__builtin_mips_msubu, "LLiLLiUiUi", "nc") 34 35BUILTIN(__builtin_mips_addq_s_w, "iii", "n") 36BUILTIN(__builtin_mips_subq_s_w, "iii", "n") 37 38BUILTIN(__builtin_mips_addsc, "iii", "n") 39BUILTIN(__builtin_mips_addwc, "iii", "n") 40 41BUILTIN(__builtin_mips_modsub, "iii", "nc") 42 43BUILTIN(__builtin_mips_raddu_w_qb, "iV4Sc", "nc") 44 45BUILTIN(__builtin_mips_absq_s_ph, "V2sV2s", "n") 46BUILTIN(__builtin_mips_absq_s_w, "ii", "n") 47 48BUILTIN(__builtin_mips_precrq_qb_ph, "V4ScV2sV2s", "nc") 49BUILTIN(__builtin_mips_precrqu_s_qb_ph, "V4ScV2sV2s", "n") 50BUILTIN(__builtin_mips_precrq_ph_w, "V2sii", "nc") 51BUILTIN(__builtin_mips_precrq_rs_ph_w, "V2sii", "n") 52BUILTIN(__builtin_mips_preceq_w_phl, "iV2s", "nc") 53BUILTIN(__builtin_mips_preceq_w_phr, "iV2s", "nc") 54BUILTIN(__builtin_mips_precequ_ph_qbl, "V2sV4Sc", "nc") 55BUILTIN(__builtin_mips_precequ_ph_qbr, "V2sV4Sc", "nc") 56BUILTIN(__builtin_mips_precequ_ph_qbla, "V2sV4Sc", "nc") 57BUILTIN(__builtin_mips_precequ_ph_qbra, "V2sV4Sc", "nc") 58BUILTIN(__builtin_mips_preceu_ph_qbl, "V2sV4Sc", "nc") 59BUILTIN(__builtin_mips_preceu_ph_qbr, "V2sV4Sc", "nc") 60BUILTIN(__builtin_mips_preceu_ph_qbla, "V2sV4Sc", "nc") 61BUILTIN(__builtin_mips_preceu_ph_qbra, "V2sV4Sc", "nc") 62 63BUILTIN(__builtin_mips_shll_qb, "V4ScV4Sci", "n") 64BUILTIN(__builtin_mips_shrl_qb, "V4ScV4Sci", "nc") 65BUILTIN(__builtin_mips_shll_ph, "V2sV2si", "n") 66BUILTIN(__builtin_mips_shll_s_ph, "V2sV2si", "n") 67BUILTIN(__builtin_mips_shra_ph, "V2sV2si", "nc") 68BUILTIN(__builtin_mips_shra_r_ph, "V2sV2si", "nc") 69BUILTIN(__builtin_mips_shll_s_w, "iii", "n") 70BUILTIN(__builtin_mips_shra_r_w, "iii", "nc") 71BUILTIN(__builtin_mips_shilo, "LLiLLii", "nc") 72 73BUILTIN(__builtin_mips_muleu_s_ph_qbl, "V2sV4ScV2s", "n") 74BUILTIN(__builtin_mips_muleu_s_ph_qbr, "V2sV4ScV2s", "n") 75BUILTIN(__builtin_mips_mulq_rs_ph, "V2sV2sV2s", "n") 76BUILTIN(__builtin_mips_muleq_s_w_phl, "iV2sV2s", "n") 77BUILTIN(__builtin_mips_muleq_s_w_phr, "iV2sV2s", "n") 78BUILTIN(__builtin_mips_mulsaq_s_w_ph, "LLiLLiV2sV2s", "n") 79BUILTIN(__builtin_mips_maq_s_w_phl, "LLiLLiV2sV2s", "n") 80BUILTIN(__builtin_mips_maq_s_w_phr, "LLiLLiV2sV2s", "n") 81BUILTIN(__builtin_mips_maq_sa_w_phl, "LLiLLiV2sV2s", "n") 82BUILTIN(__builtin_mips_maq_sa_w_phr, "LLiLLiV2sV2s", "n") 83BUILTIN(__builtin_mips_mult, "LLiii", "nc") 84BUILTIN(__builtin_mips_multu, "LLiUiUi", "nc") 85 86BUILTIN(__builtin_mips_dpau_h_qbl, "LLiLLiV4ScV4Sc", "nc") 87BUILTIN(__builtin_mips_dpau_h_qbr, "LLiLLiV4ScV4Sc", "nc") 88BUILTIN(__builtin_mips_dpsu_h_qbl, "LLiLLiV4ScV4Sc", "nc") 89BUILTIN(__builtin_mips_dpsu_h_qbr, "LLiLLiV4ScV4Sc", "nc") 90BUILTIN(__builtin_mips_dpaq_s_w_ph, "LLiLLiV2sV2s", "n") 91BUILTIN(__builtin_mips_dpsq_s_w_ph, "LLiLLiV2sV2s", "n") 92BUILTIN(__builtin_mips_dpaq_sa_l_w, "LLiLLiii", "n") 93BUILTIN(__builtin_mips_dpsq_sa_l_w, "LLiLLiii", "n") 94 95BUILTIN(__builtin_mips_cmpu_eq_qb, "vV4ScV4Sc", "n") 96BUILTIN(__builtin_mips_cmpu_lt_qb, "vV4ScV4Sc", "n") 97BUILTIN(__builtin_mips_cmpu_le_qb, "vV4ScV4Sc", "n") 98BUILTIN(__builtin_mips_cmpgu_eq_qb, "iV4ScV4Sc", "n") 99BUILTIN(__builtin_mips_cmpgu_lt_qb, "iV4ScV4Sc", "n") 100BUILTIN(__builtin_mips_cmpgu_le_qb, "iV4ScV4Sc", "n") 101BUILTIN(__builtin_mips_cmp_eq_ph, "vV2sV2s", "n") 102BUILTIN(__builtin_mips_cmp_lt_ph, "vV2sV2s", "n") 103BUILTIN(__builtin_mips_cmp_le_ph, "vV2sV2s", "n") 104 105BUILTIN(__builtin_mips_extr_s_h, "iLLii", "n") 106BUILTIN(__builtin_mips_extr_w, "iLLii", "n") 107BUILTIN(__builtin_mips_extr_rs_w, "iLLii", "n") 108BUILTIN(__builtin_mips_extr_r_w, "iLLii", "n") 109BUILTIN(__builtin_mips_extp, "iLLii", "n") 110BUILTIN(__builtin_mips_extpdp, "iLLii", "n") 111 112BUILTIN(__builtin_mips_wrdsp, "viIi", "n") 113BUILTIN(__builtin_mips_rddsp, "iIi", "n") 114BUILTIN(__builtin_mips_insv, "iii", "n") 115BUILTIN(__builtin_mips_bitrev, "ii", "nc") 116BUILTIN(__builtin_mips_packrl_ph, "V2sV2sV2s", "nc") 117BUILTIN(__builtin_mips_repl_qb, "V4Sci", "nc") 118BUILTIN(__builtin_mips_repl_ph, "V2si", "nc") 119BUILTIN(__builtin_mips_pick_qb, "V4ScV4ScV4Sc", "n") 120BUILTIN(__builtin_mips_pick_ph, "V2sV2sV2s", "n") 121BUILTIN(__builtin_mips_mthlip, "LLiLLii", "n") 122BUILTIN(__builtin_mips_bposge32, "i", "n") 123BUILTIN(__builtin_mips_lbux, "iv*i", "n") 124BUILTIN(__builtin_mips_lhx, "iv*i", "n") 125BUILTIN(__builtin_mips_lwx, "iv*i", "n") 126 127// MIPS DSP Rev 2 128 129BUILTIN(__builtin_mips_absq_s_qb, "V4ScV4Sc", "n") 130 131BUILTIN(__builtin_mips_addqh_ph, "V2sV2sV2s", "nc") 132BUILTIN(__builtin_mips_addqh_r_ph, "V2sV2sV2s", "nc") 133BUILTIN(__builtin_mips_addqh_w, "iii", "nc") 134BUILTIN(__builtin_mips_addqh_r_w, "iii", "nc") 135 136BUILTIN(__builtin_mips_addu_ph, "V2sV2sV2s", "n") 137BUILTIN(__builtin_mips_addu_s_ph, "V2sV2sV2s", "n") 138 139BUILTIN(__builtin_mips_adduh_qb, "V4ScV4ScV4Sc", "nc") 140BUILTIN(__builtin_mips_adduh_r_qb, "V4ScV4ScV4Sc", "nc") 141 142BUILTIN(__builtin_mips_append, "iiiIi", "nc") 143BUILTIN(__builtin_mips_balign, "iiiIi", "nc") 144 145BUILTIN(__builtin_mips_cmpgdu_eq_qb, "iV4ScV4Sc", "n") 146BUILTIN(__builtin_mips_cmpgdu_lt_qb, "iV4ScV4Sc", "n") 147BUILTIN(__builtin_mips_cmpgdu_le_qb, "iV4ScV4Sc", "n") 148 149BUILTIN(__builtin_mips_dpa_w_ph, "LLiLLiV2sV2s", "nc") 150BUILTIN(__builtin_mips_dps_w_ph, "LLiLLiV2sV2s", "nc") 151 152BUILTIN(__builtin_mips_dpaqx_s_w_ph, "LLiLLiV2sV2s", "n") 153BUILTIN(__builtin_mips_dpaqx_sa_w_ph, "LLiLLiV2sV2s", "n") 154BUILTIN(__builtin_mips_dpax_w_ph, "LLiLLiV2sV2s", "nc") 155BUILTIN(__builtin_mips_dpsx_w_ph, "LLiLLiV2sV2s", "nc") 156BUILTIN(__builtin_mips_dpsqx_s_w_ph, "LLiLLiV2sV2s", "n") 157BUILTIN(__builtin_mips_dpsqx_sa_w_ph, "LLiLLiV2sV2s", "n") 158 159BUILTIN(__builtin_mips_mul_ph, "V2sV2sV2s", "n") 160BUILTIN(__builtin_mips_mul_s_ph, "V2sV2sV2s", "n") 161 162BUILTIN(__builtin_mips_mulq_rs_w, "iii", "n") 163BUILTIN(__builtin_mips_mulq_s_ph, "V2sV2sV2s", "n") 164BUILTIN(__builtin_mips_mulq_s_w, "iii", "n") 165BUILTIN(__builtin_mips_mulsa_w_ph, "LLiLLiV2sV2s", "nc") 166 167BUILTIN(__builtin_mips_precr_qb_ph, "V4ScV2sV2s", "n") 168BUILTIN(__builtin_mips_precr_sra_ph_w, "V2siiIi", "nc") 169BUILTIN(__builtin_mips_precr_sra_r_ph_w, "V2siiIi", "nc") 170 171BUILTIN(__builtin_mips_prepend, "iiiIi", "nc") 172 173BUILTIN(__builtin_mips_shra_qb, "V4ScV4Sci", "nc") 174BUILTIN(__builtin_mips_shra_r_qb, "V4ScV4Sci", "nc") 175BUILTIN(__builtin_mips_shrl_ph, "V2sV2si", "nc") 176 177BUILTIN(__builtin_mips_subqh_ph, "V2sV2sV2s", "nc") 178BUILTIN(__builtin_mips_subqh_r_ph, "V2sV2sV2s", "nc") 179BUILTIN(__builtin_mips_subqh_w, "iii", "nc") 180BUILTIN(__builtin_mips_subqh_r_w, "iii", "nc") 181 182BUILTIN(__builtin_mips_subu_ph, "V2sV2sV2s", "n") 183BUILTIN(__builtin_mips_subu_s_ph, "V2sV2sV2s", "n") 184 185BUILTIN(__builtin_mips_subuh_qb, "V4ScV4ScV4Sc", "nc") 186BUILTIN(__builtin_mips_subuh_r_qb, "V4ScV4ScV4Sc", "nc") 187 188#undef BUILTIN 189