HexagonISelLowering.cpp revision ee498d3254b86bceb4f441741e9f442990647ce6
1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Hexagon uses to lower LLVM code 11// into a selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "HexagonISelLowering.h" 16#include "HexagonTargetMachine.h" 17#include "HexagonMachineFunctionInfo.h" 18#include "HexagonTargetObjectFile.h" 19#include "HexagonSubtarget.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Function.h" 22#include "llvm/InlineAsm.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/GlobalAlias.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/CallingConv.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/CodeGen/ValueTypes.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/CodeGen/MachineJumpTableInfo.h" 37#include "HexagonMachineFunctionInfo.h" 38#include "llvm/Support/CommandLine.h" 39 40const unsigned Hexagon_MAX_RET_SIZE = 64; 41using namespace llvm; 42 43static cl::opt<bool> 44EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, 45 cl::desc("Control jump table emission on Hexagon target")); 46 47int NumNamedVarArgParams = -1; 48 49// Implement calling convention for Hexagon. 50static bool 51CC_Hexagon(unsigned ValNo, MVT ValVT, 52 MVT LocVT, CCValAssign::LocInfo LocInfo, 53 ISD::ArgFlagsTy ArgFlags, CCState &State); 54 55static bool 56CC_Hexagon32(unsigned ValNo, MVT ValVT, 57 MVT LocVT, CCValAssign::LocInfo LocInfo, 58 ISD::ArgFlagsTy ArgFlags, CCState &State); 59 60static bool 61CC_Hexagon64(unsigned ValNo, MVT ValVT, 62 MVT LocVT, CCValAssign::LocInfo LocInfo, 63 ISD::ArgFlagsTy ArgFlags, CCState &State); 64 65static bool 66RetCC_Hexagon(unsigned ValNo, MVT ValVT, 67 MVT LocVT, CCValAssign::LocInfo LocInfo, 68 ISD::ArgFlagsTy ArgFlags, CCState &State); 69 70static bool 71RetCC_Hexagon32(unsigned ValNo, MVT ValVT, 72 MVT LocVT, CCValAssign::LocInfo LocInfo, 73 ISD::ArgFlagsTy ArgFlags, CCState &State); 74 75static bool 76RetCC_Hexagon64(unsigned ValNo, MVT ValVT, 77 MVT LocVT, CCValAssign::LocInfo LocInfo, 78 ISD::ArgFlagsTy ArgFlags, CCState &State); 79 80static bool 81CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT, 82 MVT LocVT, CCValAssign::LocInfo LocInfo, 83 ISD::ArgFlagsTy ArgFlags, CCState &State) { 84 85 // NumNamedVarArgParams can not be zero for a VarArg function. 86 assert ( (NumNamedVarArgParams > 0) && 87 "NumNamedVarArgParams is not bigger than zero."); 88 89 if ( (int)ValNo < NumNamedVarArgParams ) { 90 // Deal with named arguments. 91 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State); 92 } 93 94 // Deal with un-named arguments. 95 unsigned ofst; 96 if (ArgFlags.isByVal()) { 97 // If pass-by-value, the size allocated on stack is decided 98 // by ArgFlags.getByValSize(), not by the size of LocVT. 99 assert ((ArgFlags.getByValSize() > 8) && 100 "ByValSize must be bigger than 8 bytes"); 101 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4); 102 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 103 return false; 104 } 105 if (LocVT == MVT::i32) { 106 ofst = State.AllocateStack(4, 4); 107 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 108 return false; 109 } 110 if (LocVT == MVT::i64) { 111 ofst = State.AllocateStack(8, 8); 112 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 113 return false; 114 } 115 llvm_unreachable(0); 116} 117 118 119static bool 120CC_Hexagon (unsigned ValNo, MVT ValVT, 121 MVT LocVT, CCValAssign::LocInfo LocInfo, 122 ISD::ArgFlagsTy ArgFlags, CCState &State) { 123 124 if (ArgFlags.isByVal()) { 125 // Passed on stack. 126 assert ((ArgFlags.getByValSize() > 8) && 127 "ByValSize must be bigger than 8 bytes"); 128 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4); 129 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 130 return false; 131 } 132 133 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 134 LocVT = MVT::i32; 135 ValVT = MVT::i32; 136 if (ArgFlags.isSExt()) 137 LocInfo = CCValAssign::SExt; 138 else if (ArgFlags.isZExt()) 139 LocInfo = CCValAssign::ZExt; 140 else 141 LocInfo = CCValAssign::AExt; 142 } 143 144 if (LocVT == MVT::i32) { 145 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 146 return false; 147 } 148 149 if (LocVT == MVT::i64) { 150 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 151 return false; 152 } 153 154 return true; // CC didn't match. 155} 156 157 158static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, 159 MVT LocVT, CCValAssign::LocInfo LocInfo, 160 ISD::ArgFlagsTy ArgFlags, CCState &State) { 161 162 static const unsigned RegList[] = { 163 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 164 Hexagon::R5 165 }; 166 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 167 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 168 return false; 169 } 170 171 unsigned Offset = State.AllocateStack(4, 4); 172 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 173 return false; 174} 175 176static bool CC_Hexagon64(unsigned ValNo, MVT ValVT, 177 MVT LocVT, CCValAssign::LocInfo LocInfo, 178 ISD::ArgFlagsTy ArgFlags, CCState &State) { 179 180 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 181 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 182 return false; 183 } 184 185 static const unsigned RegList1[] = { 186 Hexagon::D1, Hexagon::D2 187 }; 188 static const unsigned RegList2[] = { 189 Hexagon::R1, Hexagon::R3 190 }; 191 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) { 192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 193 return false; 194 } 195 196 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2); 197 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 198 return false; 199} 200 201static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT, 202 MVT LocVT, CCValAssign::LocInfo LocInfo, 203 ISD::ArgFlagsTy ArgFlags, CCState &State) { 204 205 206 if (LocVT == MVT::i1 || 207 LocVT == MVT::i8 || 208 LocVT == MVT::i16) { 209 LocVT = MVT::i32; 210 ValVT = MVT::i32; 211 if (ArgFlags.isSExt()) 212 LocInfo = CCValAssign::SExt; 213 else if (ArgFlags.isZExt()) 214 LocInfo = CCValAssign::ZExt; 215 else 216 LocInfo = CCValAssign::AExt; 217 } 218 219 if (LocVT == MVT::i32) { 220 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 221 return false; 222 } 223 224 if (LocVT == MVT::i64) { 225 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 226 return false; 227 } 228 229 return true; // CC didn't match. 230} 231 232static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT, 233 MVT LocVT, CCValAssign::LocInfo LocInfo, 234 ISD::ArgFlagsTy ArgFlags, CCState &State) { 235 236 if (LocVT == MVT::i32) { 237 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { 238 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 239 return false; 240 } 241 } 242 243 unsigned Offset = State.AllocateStack(4, 4); 244 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 245 return false; 246} 247 248static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, 249 MVT LocVT, CCValAssign::LocInfo LocInfo, 250 ISD::ArgFlagsTy ArgFlags, CCState &State) { 251 if (LocVT == MVT::i64) { 252 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 253 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 254 return false; 255 } 256 } 257 258 unsigned Offset = State.AllocateStack(8, 8); 259 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 260 return false; 261} 262 263SDValue 264HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) 265const { 266 return SDValue(); 267} 268 269/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 270/// by "Src" to address "Dst" of size "Size". Alignment information is 271/// specified by the specific parameter attribute. The copy will be passed as 272/// a byval function parameter. Sometimes what we are copying is the end of a 273/// larger object, the part that does not fit in registers. 274static SDValue 275CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 276 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 277 DebugLoc dl) { 278 279 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 280 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 281 /*isVolatile=*/false, /*AlwaysInline=*/false, 282 MachinePointerInfo(), MachinePointerInfo()); 283} 284 285 286// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is 287// passed by value, the function prototype is modified to return void and 288// the value is stored in memory pointed by a pointer passed by caller. 289SDValue 290HexagonTargetLowering::LowerReturn(SDValue Chain, 291 CallingConv::ID CallConv, bool isVarArg, 292 const SmallVectorImpl<ISD::OutputArg> &Outs, 293 const SmallVectorImpl<SDValue> &OutVals, 294 DebugLoc dl, SelectionDAG &DAG) const { 295 296 // CCValAssign - represent the assignment of the return value to locations. 297 SmallVector<CCValAssign, 16> RVLocs; 298 299 // CCState - Info about the registers and stack slot. 300 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 301 getTargetMachine(), RVLocs, *DAG.getContext()); 302 303 // Analyze return values of ISD::RET 304 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon); 305 306 // If this is the first return lowered for this function, add the regs to the 307 // liveout set for the function. 308 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 309 for (unsigned i = 0; i != RVLocs.size(); ++i) 310 if (RVLocs[i].isRegLoc()) 311 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 312 } 313 314 SDValue Flag; 315 // Copy the result values into the output registers. 316 for (unsigned i = 0; i != RVLocs.size(); ++i) { 317 CCValAssign &VA = RVLocs[i]; 318 319 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 320 321 // Guarantee that all emitted copies are stuck together with flags. 322 Flag = Chain.getValue(1); 323 } 324 325 if (Flag.getNode()) 326 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 327 328 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, Chain); 329} 330 331 332 333 334/// LowerCallResult - Lower the result values of an ISD::CALL into the 335/// appropriate copies out of appropriate physical registers. This assumes that 336/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 337/// being lowered. Returns a SDNode with the same number of values as the 338/// ISD::CALL. 339SDValue 340HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 341 CallingConv::ID CallConv, bool isVarArg, 342 const 343 SmallVectorImpl<ISD::InputArg> &Ins, 344 DebugLoc dl, SelectionDAG &DAG, 345 SmallVectorImpl<SDValue> &InVals, 346 const SmallVectorImpl<SDValue> &OutVals, 347 SDValue Callee) const { 348 349 // Assign locations to each value returned by this call. 350 SmallVector<CCValAssign, 16> RVLocs; 351 352 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 353 getTargetMachine(), RVLocs, *DAG.getContext()); 354 355 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon); 356 357 // Copy all of the result registers out of their specified physreg. 358 for (unsigned i = 0; i != RVLocs.size(); ++i) { 359 Chain = DAG.getCopyFromReg(Chain, dl, 360 RVLocs[i].getLocReg(), 361 RVLocs[i].getValVT(), InFlag).getValue(1); 362 InFlag = Chain.getValue(2); 363 InVals.push_back(Chain.getValue(0)); 364 } 365 366 return Chain; 367} 368 369/// LowerCall - Functions arguments are copied from virtual regs to 370/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 371SDValue 372HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 373 CallingConv::ID CallConv, bool isVarArg, 374 bool &isTailCall, 375 const SmallVectorImpl<ISD::OutputArg> &Outs, 376 const SmallVectorImpl<SDValue> &OutVals, 377 const SmallVectorImpl<ISD::InputArg> &Ins, 378 DebugLoc dl, SelectionDAG &DAG, 379 SmallVectorImpl<SDValue> &InVals) const { 380 381 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 382 383 // Analyze operands of the call, assigning locations to each operand. 384 SmallVector<CCValAssign, 16> ArgLocs; 385 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 386 getTargetMachine(), ArgLocs, *DAG.getContext()); 387 388 // Check for varargs. 389 NumNamedVarArgParams = -1; 390 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee)) 391 { 392 const Function* CalleeFn = NULL; 393 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32); 394 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal()))) 395 { 396 // If a function has zero args and is a vararg function, that's 397 // disallowed so it must be an undeclared function. Do not assume 398 // varargs if the callee is undefined. 399 if (CalleeFn->isVarArg() && 400 CalleeFn->getFunctionType()->getNumParams() != 0) { 401 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams(); 402 } 403 } 404 } 405 406 if (NumNamedVarArgParams > 0) 407 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg); 408 else 409 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); 410 411 412 if(isTailCall) { 413 bool StructAttrFlag = 414 DAG.getMachineFunction().getFunction()->hasStructRetAttr(); 415 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 416 isVarArg, IsStructRet, 417 StructAttrFlag, 418 Outs, OutVals, Ins, DAG); 419 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){ 420 CCValAssign &VA = ArgLocs[i]; 421 if (VA.isMemLoc()) { 422 isTailCall = false; 423 break; 424 } 425 } 426 if (isTailCall) { 427 DEBUG(dbgs () << "Eligible for Tail Call\n"); 428 } else { 429 DEBUG(dbgs () << 430 "Argument must be passed on stack. Not eligible for Tail Call\n"); 431 } 432 } 433 // Get a count of how many bytes are to be pushed on the stack. 434 unsigned NumBytes = CCInfo.getNextStackOffset(); 435 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 436 SmallVector<SDValue, 8> MemOpChains; 437 438 SDValue StackPtr = 439 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(), 440 getPointerTy()); 441 442 // Walk the register/memloc assignments, inserting copies/loads. 443 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 444 CCValAssign &VA = ArgLocs[i]; 445 SDValue Arg = OutVals[i]; 446 ISD::ArgFlagsTy Flags = Outs[i].Flags; 447 448 // Promote the value if needed. 449 switch (VA.getLocInfo()) { 450 default: 451 // Loc info must be one of Full, SExt, ZExt, or AExt. 452 assert(0 && "Unknown loc info!"); 453 case CCValAssign::Full: 454 break; 455 case CCValAssign::SExt: 456 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 457 break; 458 case CCValAssign::ZExt: 459 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 460 break; 461 case CCValAssign::AExt: 462 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 463 break; 464 } 465 466 if (VA.isMemLoc()) { 467 unsigned LocMemOffset = VA.getLocMemOffset(); 468 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType()); 469 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 470 471 if (Flags.isByVal()) { 472 // The argument is a struct passed by value. According to LLVM, "Arg" 473 // is is pointer. 474 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain, 475 Flags, DAG, dl)); 476 } else { 477 // The argument is not passed by value. "Arg" is a buildin type. It is 478 // not a pointer. 479 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 480 MachinePointerInfo(),false, false, 481 0)); 482 } 483 continue; 484 } 485 486 // Arguments that can be passed on register must be kept at RegsToPass 487 // vector. 488 if (VA.isRegLoc()) { 489 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 490 } 491 } 492 493 // Transform all store nodes into one single node because all store 494 // nodes are independent of each other. 495 if (!MemOpChains.empty()) { 496 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], 497 MemOpChains.size()); 498 } 499 500 if (!isTailCall) 501 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, 502 getPointerTy(), true)); 503 504 // Build a sequence of copy-to-reg nodes chained together with token 505 // chain and flag operands which copy the outgoing args into registers. 506 // The InFlag in necessary since all emited instructions must be 507 // stuck together. 508 SDValue InFlag; 509 if (!isTailCall) { 510 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 511 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 512 RegsToPass[i].second, InFlag); 513 InFlag = Chain.getValue(1); 514 } 515 } 516 517 // For tail calls lower the arguments to the 'real' stack slot. 518 if (isTailCall) { 519 // Force all the incoming stack arguments to be loaded from the stack 520 // before any new outgoing arguments are stored to the stack, because the 521 // outgoing stack slots may alias the incoming argument stack slots, and 522 // the alias isn't otherwise explicit. This is slightly more conservative 523 // than necessary, because it means that each store effectively depends 524 // on every argument instead of just those arguments it would clobber. 525 // 526 // Do not flag preceeding copytoreg stuff together with the following stuff. 527 InFlag = SDValue(); 528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 529 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 530 RegsToPass[i].second, InFlag); 531 InFlag = Chain.getValue(1); 532 } 533 InFlag =SDValue(); 534 } 535 536 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 537 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 538 // node so that legalize doesn't hack it. 539 if (flag_aligned_memcpy) { 540 const char *MemcpyName = 541 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes"; 542 Callee = 543 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy()); 544 flag_aligned_memcpy = false; 545 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 546 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); 547 } else if (ExternalSymbolSDNode *S = 548 dyn_cast<ExternalSymbolSDNode>(Callee)) { 549 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 550 } 551 552 // Returns a chain & a flag for retval copy to use. 553 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 554 SmallVector<SDValue, 8> Ops; 555 Ops.push_back(Chain); 556 Ops.push_back(Callee); 557 558 // Add argument registers to the end of the list so that they are 559 // known live into the call. 560 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 561 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 562 RegsToPass[i].second.getValueType())); 563 } 564 565 if (InFlag.getNode()) { 566 Ops.push_back(InFlag); 567 } 568 569 if (isTailCall) 570 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 571 572 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 573 InFlag = Chain.getValue(1); 574 575 // Create the CALLSEQ_END node. 576 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 577 DAG.getIntPtrConstant(0, true), InFlag); 578 InFlag = Chain.getValue(1); 579 580 // Handle result values, copying them out of physregs into vregs that we 581 // return. 582 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, 583 InVals, OutVals, Callee); 584} 585 586static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, 587 bool isSEXTLoad, SDValue &Base, 588 SDValue &Offset, bool &isInc, 589 SelectionDAG &DAG) { 590 if (Ptr->getOpcode() != ISD::ADD) 591 return false; 592 593 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 594 isInc = (Ptr->getOpcode() == ISD::ADD); 595 Base = Ptr->getOperand(0); 596 Offset = Ptr->getOperand(1); 597 // Ensure that Offset is a constant. 598 return (isa<ConstantSDNode>(Offset)); 599 } 600 601 return false; 602} 603 604// TODO: Put this function along with the other isS* functions in 605// HexagonISelDAGToDAG.cpp into a common file. Or better still, use the 606// functions defined in HexagonImmediates.td. 607static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) { 608 ConstantSDNode *N = cast<ConstantSDNode>(S); 609 610 // immS4 predicate - True if the immediate fits in a 4-bit sign extended. 611 // field. 612 int64_t v = (int64_t)N->getSExtValue(); 613 int64_t m = 0; 614 if (ShiftAmount > 0) { 615 m = v % ShiftAmount; 616 v = v >> ShiftAmount; 617 } 618 return (v <= 7) && (v >= -8) && (m == 0); 619} 620 621/// getPostIndexedAddressParts - returns true by value, base pointer and 622/// offset pointer and addressing mode by reference if this node can be 623/// combined with a load / store to form a post-indexed load / store. 624bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 625 SDValue &Base, 626 SDValue &Offset, 627 ISD::MemIndexedMode &AM, 628 SelectionDAG &DAG) const 629{ 630 EVT VT; 631 SDValue Ptr; 632 bool isSEXTLoad = false; 633 634 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 635 VT = LD->getMemoryVT(); 636 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 637 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 638 VT = ST->getMemoryVT(); 639 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) { 640 return false; 641 } 642 } else { 643 return false; 644 } 645 646 bool isInc = false; 647 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 648 isInc, DAG); 649 // ShiftAmount = number of left-shifted bits in the Hexagon instruction. 650 int ShiftAmount = VT.getSizeInBits() / 16; 651 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) { 652 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 653 return true; 654 } 655 656 return false; 657} 658 659SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, 660 SelectionDAG &DAG) const { 661 SDNode *Node = Op.getNode(); 662 MachineFunction &MF = DAG.getMachineFunction(); 663 HexagonMachineFunctionInfo *FuncInfo = 664 MF.getInfo<HexagonMachineFunctionInfo>(); 665 switch (Node->getOpcode()) { 666 case ISD::INLINEASM: { 667 unsigned NumOps = Node->getNumOperands(); 668 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 669 --NumOps; // Ignore the flag operand. 670 671 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 672 if (FuncInfo->hasClobberLR()) 673 break; 674 unsigned Flags = 675 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 676 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 677 ++i; // Skip the ID value. 678 679 switch (InlineAsm::getKind(Flags)) { 680 default: llvm_unreachable("Bad flags!"); 681 case InlineAsm::Kind_RegDef: 682 case InlineAsm::Kind_RegUse: 683 case InlineAsm::Kind_Imm: 684 case InlineAsm::Kind_Clobber: 685 case InlineAsm::Kind_Mem: { 686 for (; NumVals; --NumVals, ++i) {} 687 break; 688 } 689 case InlineAsm::Kind_RegDefEarlyClobber: { 690 for (; NumVals; --NumVals, ++i) { 691 unsigned Reg = 692 cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 693 694 // Check it to be lr 695 if (Reg == TM.getRegisterInfo()->getRARegister()) { 696 FuncInfo->setHasClobberLR(true); 697 break; 698 } 699 } 700 break; 701 } 702 } 703 } 704 } 705 } // Node->getOpcode 706 return Op; 707} 708 709 710// 711// Taken from the XCore backend. 712// 713SDValue HexagonTargetLowering:: 714LowerBR_JT(SDValue Op, SelectionDAG &DAG) const 715{ 716 SDValue Chain = Op.getOperand(0); 717 SDValue Table = Op.getOperand(1); 718 SDValue Index = Op.getOperand(2); 719 DebugLoc dl = Op.getDebugLoc(); 720 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 721 unsigned JTI = JT->getIndex(); 722 MachineFunction &MF = DAG.getMachineFunction(); 723 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 724 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); 725 726 // Mark all jump table targets as address taken. 727 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables(); 728 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs; 729 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { 730 MachineBasicBlock *MBB = JTBBs[i]; 731 MBB->setHasAddressTaken(); 732 // This line is needed to set the hasAddressTaken flag on the BasicBlock 733 // object. 734 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock())); 735 } 736 737 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl, 738 getPointerTy(), TargetJT); 739 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 740 DAG.getConstant(2, MVT::i32)); 741 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase, 742 ShiftIndex); 743 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress, 744 MachinePointerInfo(), false, false, false, 745 0); 746 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget); 747} 748 749 750SDValue 751HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 752 SelectionDAG &DAG) const { 753 SDValue Chain = Op.getOperand(0); 754 SDValue Size = Op.getOperand(1); 755 DebugLoc dl = Op.getDebugLoc(); 756 757 unsigned SPReg = getStackPointerRegisterToSaveRestore(); 758 759 // Get a reference to the stack pointer. 760 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 761 762 // Subtract the dynamic size from the actual stack size to 763 // obtain the new stack size. 764 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 765 766 // 767 // For Hexagon, the outgoing memory arguments area should be on top of the 768 // alloca area on the stack i.e., the outgoing memory arguments should be 769 // at a lower address than the alloca area. Move the alloca area down the 770 // stack by adding back the space reserved for outgoing arguments to SP 771 // here. 772 // 773 // We do not know what the size of the outgoing args is at this point. 774 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the 775 // stack pointer. We patch this instruction with the correct, known 776 // offset in emitPrologue(). 777 // 778 // Use a placeholder immediate (zero) for now. This will be patched up 779 // by emitPrologue(). 780 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl, 781 MVT::i32, 782 Sub, 783 DAG.getConstant(0, MVT::i32)); 784 785 // The Sub result contains the new stack start address, so it 786 // must be placed in the stack pointer register. 787 SDValue CopyChain = DAG.getCopyToReg(Chain, dl, 788 TM.getRegisterInfo()->getStackRegister(), 789 Sub); 790 791 SDValue Ops[2] = { ArgAdjust, CopyChain }; 792 return DAG.getMergeValues(Ops, 2, dl); 793} 794 795SDValue 796HexagonTargetLowering::LowerFormalArguments(SDValue Chain, 797 CallingConv::ID CallConv, 798 bool isVarArg, 799 const 800 SmallVectorImpl<ISD::InputArg> &Ins, 801 DebugLoc dl, SelectionDAG &DAG, 802 SmallVectorImpl<SDValue> &InVals) 803const { 804 805 MachineFunction &MF = DAG.getMachineFunction(); 806 MachineFrameInfo *MFI = MF.getFrameInfo(); 807 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 808 HexagonMachineFunctionInfo *FuncInfo = 809 MF.getInfo<HexagonMachineFunctionInfo>(); 810 811 812 // Assign locations to all of the incoming arguments. 813 SmallVector<CCValAssign, 16> ArgLocs; 814 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 815 getTargetMachine(), ArgLocs, *DAG.getContext()); 816 817 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon); 818 819 // For LLVM, in the case when returning a struct by value (>8byte), 820 // the first argument is a pointer that points to the location on caller's 821 // stack where the return value will be stored. For Hexagon, the location on 822 // caller's stack is passed only when the struct size is smaller than (and 823 // equal to) 8 bytes. If not, no address will be passed into callee and 824 // callee return the result direclty through R0/R1. 825 826 SmallVector<SDValue, 4> MemOps; 827 828 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 829 CCValAssign &VA = ArgLocs[i]; 830 ISD::ArgFlagsTy Flags = Ins[i].Flags; 831 unsigned ObjSize; 832 unsigned StackLocation; 833 int FI; 834 835 if ( (VA.isRegLoc() && !Flags.isByVal()) 836 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) { 837 // Arguments passed in registers 838 // 1. int, long long, ptr args that get allocated in register. 839 // 2. Large struct that gets an register to put its address in. 840 EVT RegVT = VA.getLocVT(); 841 if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) { 842 unsigned VReg = 843 RegInfo.createVirtualRegister(Hexagon::IntRegsRegisterClass); 844 RegInfo.addLiveIn(VA.getLocReg(), VReg); 845 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 846 } else if (RegVT == MVT::i64) { 847 unsigned VReg = 848 RegInfo.createVirtualRegister(Hexagon::DoubleRegsRegisterClass); 849 RegInfo.addLiveIn(VA.getLocReg(), VReg); 850 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 851 } else { 852 assert (0); 853 } 854 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) { 855 assert (0 && "ByValSize must be bigger than 8 bytes"); 856 } else { 857 // Sanity check. 858 assert(VA.isMemLoc()); 859 860 if (Flags.isByVal()) { 861 // If it's a byval parameter, then we need to compute the 862 // "real" size, not the size of the pointer. 863 ObjSize = Flags.getByValSize(); 864 } else { 865 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3; 866 } 867 868 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset(); 869 // Create the frame index object for this incoming parameter... 870 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true); 871 872 // Create the SelectionDAG nodes cordl, responding to a load 873 // from this parameter. 874 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 875 876 if (Flags.isByVal()) { 877 // If it's a pass-by-value aggregate, then do not dereference the stack 878 // location. Instead, we should generate a reference to the stack 879 // location. 880 InVals.push_back(FIN); 881 } else { 882 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 883 MachinePointerInfo(), false, false, 884 false, 0)); 885 } 886 } 887 } 888 889 if (!MemOps.empty()) 890 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], 891 MemOps.size()); 892 893 if (isVarArg) { 894 // This will point to the next argument passed via stack. 895 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize, 896 HEXAGON_LRFP_SIZE + 897 CCInfo.getNextStackOffset(), 898 true); 899 FuncInfo->setVarArgsFrameIndex(FrameIndex); 900 } 901 902 return Chain; 903} 904 905SDValue 906HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 907 // VASTART stores the address of the VarArgsFrameIndex slot into the 908 // memory location argument. 909 MachineFunction &MF = DAG.getMachineFunction(); 910 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>(); 911 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32); 912 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 913 return DAG.getStore(Op.getOperand(0), Op.getDebugLoc(), Addr, 914 Op.getOperand(1), MachinePointerInfo(SV), false, 915 false, 0); 916} 917 918SDValue 919HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 920 SDNode* OpNode = Op.getNode(); 921 922 SDValue Cond = DAG.getNode(ISD::SETCC, Op.getDebugLoc(), MVT::i1, 923 Op.getOperand(2), Op.getOperand(3), 924 Op.getOperand(4)); 925 return DAG.getNode(ISD::SELECT, Op.getDebugLoc(), OpNode->getValueType(0), 926 Cond, Op.getOperand(0), 927 Op.getOperand(1)); 928} 929 930SDValue 931HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { 932 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 933 MachineFunction &MF = DAG.getMachineFunction(); 934 MachineFrameInfo *MFI = MF.getFrameInfo(); 935 MFI->setReturnAddressIsTaken(true); 936 937 EVT VT = Op.getValueType(); 938 DebugLoc dl = Op.getDebugLoc(); 939 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 940 if (Depth) { 941 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 942 SDValue Offset = DAG.getConstant(4, MVT::i32); 943 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 944 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 945 MachinePointerInfo(), false, false, false, 0); 946 } 947 948 // Return LR, which contains the return address. Mark it an implicit live-in. 949 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); 950 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 951} 952 953SDValue 954HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 955 const HexagonRegisterInfo *TRI = TM.getRegisterInfo(); 956 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 957 MFI->setFrameAddressIsTaken(true); 958 959 EVT VT = Op.getValueType(); 960 DebugLoc dl = Op.getDebugLoc(); 961 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 962 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 963 TRI->getFrameRegister(), VT); 964 while (Depth--) 965 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 966 MachinePointerInfo(), 967 false, false, false, 0); 968 return FrameAddr; 969} 970 971 972SDValue HexagonTargetLowering::LowerMEMBARRIER(SDValue Op, 973 SelectionDAG& DAG) const { 974 DebugLoc dl = Op.getDebugLoc(); 975 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0)); 976} 977 978 979SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, 980 SelectionDAG& DAG) const { 981 DebugLoc dl = Op.getDebugLoc(); 982 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0)); 983} 984 985 986SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, 987 SelectionDAG &DAG) const { 988 SDValue Result; 989 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 990 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 991 DebugLoc dl = Op.getDebugLoc(); 992 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 993 994 HexagonTargetObjectFile &TLOF = 995 (HexagonTargetObjectFile&)getObjFileLowering(); 996 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 997 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result); 998 } 999 1000 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result); 1001} 1002 1003//===----------------------------------------------------------------------===// 1004// TargetLowering Implementation 1005//===----------------------------------------------------------------------===// 1006 1007HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine 1008 &targetmachine) 1009 : TargetLowering(targetmachine, new HexagonTargetObjectFile()), 1010 TM(targetmachine) { 1011 1012 // Set up the register classes. 1013 addRegisterClass(MVT::i32, Hexagon::IntRegsRegisterClass); 1014 addRegisterClass(MVT::i64, Hexagon::DoubleRegsRegisterClass); 1015 1016 addRegisterClass(MVT::i1, Hexagon::PredRegsRegisterClass); 1017 1018 computeRegisterProperties(); 1019 1020 // Align loop entry 1021 setPrefLoopAlignment(4); 1022 1023 // Limits for inline expansion of memcpy/memmove 1024 maxStoresPerMemcpy = 6; 1025 maxStoresPerMemmove = 6; 1026 1027 // 1028 // Library calls for unsupported operations 1029 // 1030 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2"); 1031 1032 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf"); 1033 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf"); 1034 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf"); 1035 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf"); 1036 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf"); 1037 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf"); 1038 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf"); 1039 1040 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi"); 1041 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi"); 1042 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti"); 1043 1044 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi"); 1045 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi"); 1046 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti"); 1047 1048 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf"); 1049 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi"); 1050 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti"); 1051 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi"); 1052 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti"); 1053 1054 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2"); 1055 1056 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3"); 1057 setOperationAction(ISD::SDIV, MVT::i32, Expand); 1058 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3"); 1059 setOperationAction(ISD::SREM, MVT::i32, Expand); 1060 1061 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3"); 1062 setOperationAction(ISD::SDIV, MVT::i64, Expand); 1063 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3"); 1064 setOperationAction(ISD::SREM, MVT::i64, Expand); 1065 1066 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3"); 1067 setOperationAction(ISD::UDIV, MVT::i32, Expand); 1068 1069 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3"); 1070 setOperationAction(ISD::UDIV, MVT::i64, Expand); 1071 1072 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3"); 1073 setOperationAction(ISD::UREM, MVT::i32, Expand); 1074 1075 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3"); 1076 setOperationAction(ISD::UREM, MVT::i64, Expand); 1077 1078 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3"); 1079 setOperationAction(ISD::FDIV, MVT::f32, Expand); 1080 1081 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3"); 1082 setOperationAction(ISD::FDIV, MVT::f64, Expand); 1083 1084 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2"); 1085 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand); 1086 1087 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf"); 1088 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 1089 1090 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3"); 1091 setOperationAction(ISD::FADD, MVT::f64, Expand); 1092 1093 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3"); 1094 setOperationAction(ISD::FADD, MVT::f32, Expand); 1095 1096 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3"); 1097 setOperationAction(ISD::FADD, MVT::f32, Expand); 1098 1099 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2"); 1100 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 1101 1102 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi"); 1103 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); 1104 1105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi"); 1106 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); 1107 1108 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf"); 1109 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 1110 1111 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2"); 1112 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 1113 1114 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2"); 1115 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 1116 1117 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2"); 1118 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); 1119 1120 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2"); 1121 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 1122 1123 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2"); 1124 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 1125 1126 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2"); 1127 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand); 1128 1129 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2"); 1130 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); 1131 1132 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3"); 1133 setOperationAction(ISD::SREM, MVT::i32, Expand); 1134 1135 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3"); 1136 setOperationAction(ISD::FMUL, MVT::f64, Expand); 1137 1138 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3"); 1139 setOperationAction(ISD::MUL, MVT::f32, Expand); 1140 1141 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2"); 1142 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 1143 1144 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2"); 1145 1146 1147 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3"); 1148 setOperationAction(ISD::SUB, MVT::f64, Expand); 1149 1150 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3"); 1151 setOperationAction(ISD::SUB, MVT::f32, Expand); 1152 1153 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2"); 1154 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); 1155 1156 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2"); 1157 setCondCodeAction(ISD::SETUO, MVT::f64, Expand); 1158 1159 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2"); 1160 setCondCodeAction(ISD::SETO, MVT::f64, Expand); 1161 1162 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2"); 1163 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 1164 1165 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2"); 1166 setCondCodeAction(ISD::SETO, MVT::f32, Expand); 1167 1168 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2"); 1169 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); 1170 1171 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 1172 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 1173 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); 1174 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal); 1175 1176 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); 1177 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); 1178 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); 1179 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal); 1180 1181 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 1182 1183 // Turn FP extload into load/fextend. 1184 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1185 // Hexagon has a i1 sign extending load. 1186 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand); 1187 // Turn FP truncstore into trunc + store. 1188 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1189 1190 // Custom legalize GlobalAddress nodes into CONST32. 1191 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 1192 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom); 1193 // Truncate action? 1194 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand); 1195 1196 // Hexagon doesn't have sext_inreg, replace them with shl/sra. 1197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1198 1199 // Hexagon has no REM or DIVREM operations. 1200 setOperationAction(ISD::UREM, MVT::i32, Expand); 1201 setOperationAction(ISD::SREM, MVT::i32, Expand); 1202 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1203 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1204 setOperationAction(ISD::SREM, MVT::i64, Expand); 1205 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 1206 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 1207 1208 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 1209 1210 // Expand fp<->uint. 1211 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 1212 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 1213 1214 // Hexagon has no select or setcc: expand to SELECT_CC. 1215 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1216 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1217 1218 // Lower SELECT_CC to SETCC and SELECT. 1219 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1220 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1221 // This is a workaround documented in DAGCombiner.cpp:2892 We don't 1222 // support SELECT_CC on every type. 1223 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 1224 1225 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 1226 setOperationAction(ISD::BRIND, MVT::Other, Expand); 1227 if (EmitJumpTables) { 1228 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 1229 } else { 1230 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1231 } 1232 1233 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 1234 1235 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 1236 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 1237 1238 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1239 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1240 setOperationAction(ISD::FREM , MVT::f64, Expand); 1241 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1242 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1243 setOperationAction(ISD::FREM , MVT::f32, Expand); 1244 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 1245 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1247 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1249 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1250 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1251 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1252 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1253 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1254 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1255 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1256 1257 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1258 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1259 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1260 1261 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1262 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1263 1264 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 1265 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 1266 1267 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 1268 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 1269 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 1270 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 1271 1272 setOperationAction(ISD::EH_RETURN, MVT::Other, Expand); 1273 1274 if (TM.getSubtargetImpl()->isSubtargetV2()) { 1275 setExceptionPointerRegister(Hexagon::R20); 1276 setExceptionSelectorRegister(Hexagon::R21); 1277 } else { 1278 setExceptionPointerRegister(Hexagon::R0); 1279 setExceptionSelectorRegister(Hexagon::R1); 1280 } 1281 1282 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1283 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1284 1285 // Use the default implementation. 1286 setOperationAction(ISD::VAARG , MVT::Other, Expand); 1287 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1288 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1289 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1290 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1291 1292 1293 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1294 setOperationAction(ISD::INLINEASM , MVT::Other, Custom); 1295 1296 setMinFunctionAlignment(2); 1297 1298 // Needed for DYNAMIC_STACKALLOC expansion. 1299 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister(); 1300 setStackPointerRegisterToSaveRestore(StackRegister); 1301 setSchedulingPreference(Sched::VLIW); 1302} 1303 1304 1305const char* 1306HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { 1307 switch (Opcode) { 1308 default: return 0; 1309 case HexagonISD::CONST32: return "HexagonISD::CONST32"; 1310 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC"; 1311 case HexagonISD::CMPICC: return "HexagonISD::CMPICC"; 1312 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC"; 1313 case HexagonISD::BRICC: return "HexagonISD::BRICC"; 1314 case HexagonISD::BRFCC: return "HexagonISD::BRFCC"; 1315 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC"; 1316 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC"; 1317 case HexagonISD::Hi: return "HexagonISD::Hi"; 1318 case HexagonISD::Lo: return "HexagonISD::Lo"; 1319 case HexagonISD::FTOI: return "HexagonISD::FTOI"; 1320 case HexagonISD::ITOF: return "HexagonISD::ITOF"; 1321 case HexagonISD::CALL: return "HexagonISD::CALL"; 1322 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG"; 1323 case HexagonISD::BR_JT: return "HexagonISD::BR_JT"; 1324 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN"; 1325 } 1326} 1327 1328bool 1329HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 1330 EVT MTy1 = EVT::getEVT(Ty1); 1331 EVT MTy2 = EVT::getEVT(Ty2); 1332 if (!MTy1.isSimple() || !MTy2.isSimple()) { 1333 return false; 1334 } 1335 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32)); 1336} 1337 1338bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 1339 if (!VT1.isSimple() || !VT2.isSimple()) { 1340 return false; 1341 } 1342 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32)); 1343} 1344 1345SDValue 1346HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1347 switch (Op.getOpcode()) { 1348 default: assert(0 && "Should not custom lower this!"); 1349 // Frame & Return address. Currently unimplemented. 1350 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1351 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1352 case ISD::GlobalTLSAddress: 1353 assert(0 && "TLS not implemented for Hexagon."); 1354 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 1355 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 1356 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); 1357 case ISD::VASTART: return LowerVASTART(Op, DAG); 1358 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1359 1360 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1361 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1362 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1363 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG); 1364 1365 } 1366} 1367 1368 1369 1370//===----------------------------------------------------------------------===// 1371// Hexagon Scheduler Hooks 1372//===----------------------------------------------------------------------===// 1373MachineBasicBlock * 1374HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1375 MachineBasicBlock *BB) 1376const { 1377 switch (MI->getOpcode()) { 1378 case Hexagon::ADJDYNALLOC: { 1379 MachineFunction *MF = BB->getParent(); 1380 HexagonMachineFunctionInfo *FuncInfo = 1381 MF->getInfo<HexagonMachineFunctionInfo>(); 1382 FuncInfo->addAllocaAdjustInst(MI); 1383 return BB; 1384 } 1385 default: 1386 assert(false && "Unexpected instr type to insert"); 1387 } // switch 1388 return NULL; 1389} 1390 1391//===----------------------------------------------------------------------===// 1392// Inline Assembly Support 1393//===----------------------------------------------------------------------===// 1394 1395std::pair<unsigned, const TargetRegisterClass*> 1396HexagonTargetLowering::getRegForInlineAsmConstraint(const 1397 std::string &Constraint, 1398 EVT VT) const { 1399 if (Constraint.size() == 1) { 1400 switch (Constraint[0]) { 1401 case 'r': // R0-R31 1402 switch (VT.getSimpleVT().SimpleTy) { 1403 default: 1404 assert(0 && "getRegForInlineAsmConstraint Unhandled data type"); 1405 case MVT::i32: 1406 case MVT::i16: 1407 case MVT::i8: 1408 return std::make_pair(0U, Hexagon::IntRegsRegisterClass); 1409 case MVT::i64: 1410 return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass); 1411 } 1412 default: 1413 assert(0 && "Unknown asm register class"); 1414 } 1415 } 1416 1417 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1418} 1419 1420/// isLegalAddressingMode - Return true if the addressing mode represented by 1421/// AM is legal for this target, for a load/store of the specified type. 1422bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1423 Type *Ty) const { 1424 // Allows a signed-extended 11-bit immediate field. 1425 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { 1426 return false; 1427 } 1428 1429 // No global is ever allowed as a base. 1430 if (AM.BaseGV) { 1431 return false; 1432 } 1433 1434 int Scale = AM.Scale; 1435 if (Scale < 0) Scale = -Scale; 1436 switch (Scale) { 1437 case 0: // No scale reg, "r+i", "r", or just "i". 1438 break; 1439 default: // No scaled addressing mode. 1440 return false; 1441 } 1442 return true; 1443} 1444 1445/// isLegalICmpImmediate - Return true if the specified immediate is legal 1446/// icmp immediate, that is the target has icmp instructions which can compare 1447/// a register against the immediate without having to materialize the 1448/// immediate into a register. 1449bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 1450 return Imm >= -512 && Imm <= 511; 1451} 1452 1453/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1454/// for tail call optimization. Targets which want to do tail call 1455/// optimization should implement this function. 1456bool HexagonTargetLowering::IsEligibleForTailCallOptimization( 1457 SDValue Callee, 1458 CallingConv::ID CalleeCC, 1459 bool isVarArg, 1460 bool isCalleeStructRet, 1461 bool isCallerStructRet, 1462 const SmallVectorImpl<ISD::OutputArg> &Outs, 1463 const SmallVectorImpl<SDValue> &OutVals, 1464 const SmallVectorImpl<ISD::InputArg> &Ins, 1465 SelectionDAG& DAG) const { 1466 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1467 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1468 bool CCMatch = CallerCC == CalleeCC; 1469 1470 // *************************************************************************** 1471 // Look for obvious safe cases to perform tail call optimization that do not 1472 // require ABI changes. 1473 // *************************************************************************** 1474 1475 // If this is a tail call via a function pointer, then don't do it! 1476 if (!(dyn_cast<GlobalAddressSDNode>(Callee)) 1477 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) { 1478 return false; 1479 } 1480 1481 // Do not optimize if the calling conventions do not match. 1482 if (!CCMatch) 1483 return false; 1484 1485 // Do not tail call optimize vararg calls. 1486 if (isVarArg) 1487 return false; 1488 1489 // Also avoid tail call optimization if either caller or callee uses struct 1490 // return semantics. 1491 if (isCalleeStructRet || isCallerStructRet) 1492 return false; 1493 1494 // In addition to the cases above, we also disable Tail Call Optimization if 1495 // the calling convention code that at least one outgoing argument needs to 1496 // go on the stack. We cannot check that here because at this point that 1497 // information is not available. 1498 return true; 1499} 1500