1//===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements a TargetTransformInfo analysis pass specific to the
11/// PPC target machine. It uses the target's detailed information to provide
12/// more precise answers to certain TTI queries, while letting the target
13/// independent and default TTI implementations handle the rest.
14///
15//===----------------------------------------------------------------------===//
16
17#define DEBUG_TYPE "ppctti"
18#include "PPC.h"
19#include "PPCTargetMachine.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Target/TargetLowering.h"
23#include "llvm/Target/CostTable.h"
24using namespace llvm;
25
26// Declare the pass initialization routine locally as target-specific passes
27// don't havve a target-wide initialization entry point, and so we rely on the
28// pass constructor initialization.
29namespace llvm {
30void initializePPCTTIPass(PassRegistry &);
31}
32
33namespace {
34
35class PPCTTI : public ImmutablePass, public TargetTransformInfo {
36  const PPCTargetMachine *TM;
37  const PPCSubtarget *ST;
38  const PPCTargetLowering *TLI;
39
40  /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41  /// are set if the result needs to be inserted and/or extracted from vectors.
42  unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
43
44public:
45  PPCTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46    llvm_unreachable("This pass cannot be directly constructed");
47  }
48
49  PPCTTI(const PPCTargetMachine *TM)
50      : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51        TLI(TM->getTargetLowering()) {
52    initializePPCTTIPass(*PassRegistry::getPassRegistry());
53  }
54
55  virtual void initializePass() {
56    pushTTIStack(this);
57  }
58
59  virtual void finalizePass() {
60    popTTIStack();
61  }
62
63  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64    TargetTransformInfo::getAnalysisUsage(AU);
65  }
66
67  /// Pass identification.
68  static char ID;
69
70  /// Provide necessary pointer adjustments for the two base classes.
71  virtual void *getAdjustedAnalysisPointer(const void *ID) {
72    if (ID == &TargetTransformInfo::ID)
73      return (TargetTransformInfo*)this;
74    return this;
75  }
76
77  /// \name Scalar TTI Implementations
78  /// @{
79  virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
80
81  /// @}
82
83  /// \name Vector TTI Implementations
84  /// @{
85
86  virtual unsigned getNumberOfRegisters(bool Vector) const;
87  virtual unsigned getRegisterBitWidth(bool Vector) const;
88  virtual unsigned getMaximumUnrollFactor() const;
89  virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
90                                          OperandValueKind,
91                                          OperandValueKind) const;
92  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
93                                  int Index, Type *SubTp) const;
94  virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
95                                    Type *Src) const;
96  virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
97                                      Type *CondTy) const;
98  virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
99                                      unsigned Index) const;
100  virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
101                                   unsigned Alignment,
102                                   unsigned AddressSpace) const;
103
104  /// @}
105};
106
107} // end anonymous namespace
108
109INITIALIZE_AG_PASS(PPCTTI, TargetTransformInfo, "ppctti",
110                   "PPC Target Transform Info", true, true, false)
111char PPCTTI::ID = 0;
112
113ImmutablePass *
114llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
115  return new PPCTTI(TM);
116}
117
118
119//===----------------------------------------------------------------------===//
120//
121// PPC cost model.
122//
123//===----------------------------------------------------------------------===//
124
125PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
126  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
127  if (ST->hasPOPCNTD() && TyWidth <= 64)
128    return PSK_FastHardware;
129  return PSK_Software;
130}
131
132unsigned PPCTTI::getNumberOfRegisters(bool Vector) const {
133  if (Vector && !ST->hasAltivec())
134    return 0;
135  return 32;
136}
137
138unsigned PPCTTI::getRegisterBitWidth(bool Vector) const {
139  if (Vector) {
140    if (ST->hasAltivec()) return 128;
141    return 0;
142  }
143
144  if (ST->isPPC64())
145    return 64;
146  return 32;
147
148}
149
150unsigned PPCTTI::getMaximumUnrollFactor() const {
151  unsigned Directive = ST->getDarwinDirective();
152  // The 440 has no SIMD support, but floating-point instructions
153  // have a 5-cycle latency, so unroll by 5x for latency hiding.
154  if (Directive == PPC::DIR_440)
155    return 5;
156
157  // The A2 has no SIMD support, but floating-point instructions
158  // have a 6-cycle latency, so unroll by 6x for latency hiding.
159  if (Directive == PPC::DIR_A2)
160    return 6;
161
162  // FIXME: For lack of any better information, do no harm...
163  if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
164    return 1;
165
166  // For most things, modern systems have two execution units (and
167  // out-of-order execution).
168  return 2;
169}
170
171unsigned PPCTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
172                                        OperandValueKind Op1Info,
173                                        OperandValueKind Op2Info) const {
174  assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
175
176  // Fallback to the default implementation.
177  return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
178                                                     Op2Info);
179}
180
181unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
182                                Type *SubTp) const {
183  return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
184}
185
186unsigned PPCTTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
187  assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
188
189  return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
190}
191
192unsigned PPCTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
193                                    Type *CondTy) const {
194  return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
195}
196
197unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
198                                    unsigned Index) const {
199  assert(Val->isVectorTy() && "This must be a vector type");
200
201  int ISD = TLI->InstructionOpcodeToISD(Opcode);
202  assert(ISD && "Invalid opcode");
203
204  // Estimated cost of a load-hit-store delay.  This was obtained
205  // experimentally as a minimum needed to prevent unprofitable
206  // vectorization for the paq8p benchmark.  It may need to be
207  // raised further if other unprofitable cases remain.
208  unsigned LHSPenalty = 12;
209
210  // Vector element insert/extract with Altivec is very expensive,
211  // because they require store and reload with the attendant
212  // processor stall for load-hit-store.  Until VSX is available,
213  // these need to be estimated as very costly.
214  if (ISD == ISD::EXTRACT_VECTOR_ELT ||
215      ISD == ISD::INSERT_VECTOR_ELT)
216    return LHSPenalty +
217      TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
218
219  return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
220}
221
222unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
223                                 unsigned AddressSpace) const {
224  // Legalize the type.
225  std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
226  assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
227         "Invalid Opcode");
228
229  // Each load/store unit costs 1.
230  unsigned Cost = LT.first * 1;
231
232  // PPC in general does not support unaligned loads and stores. They'll need
233  // to be decomposed based on the alignment factor.
234  unsigned SrcBytes = LT.second.getStoreSize();
235  if (SrcBytes && Alignment && Alignment < SrcBytes)
236    Cost *= (SrcBytes/Alignment);
237
238  return Cost;
239}
240
241