1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
2
3; CHECK: @fmul_f32
4; CHECK: MUL_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5
6define void @fmul_f32() {
7   %r0 = call float @llvm.R600.load.input(i32 0)
8   %r1 = call float @llvm.R600.load.input(i32 1)
9   %r2 = fmul float %r0, %r1
10   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
11   ret void
12}
13
14declare float @llvm.R600.load.input(i32) readnone
15
16declare void @llvm.AMDGPU.store.output(float, i32)
17
18; CHECK: @fmul_v2f32
19; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
20; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
21define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
22entry:
23  %0 = fmul <2 x float> %a, %b
24  store <2 x float> %0, <2 x float> addrspace(1)* %out
25  ret void
26}
27
28; CHECK: @fmul_v4f32
29; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
30; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
31; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
32; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
33
34define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
35  %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
36  %a = load <4 x float> addrspace(1) * %in
37  %b = load <4 x float> addrspace(1) * %b_ptr
38  %result = fmul <4 x float> %a, %b
39  store <4 x float> %result, <4 x float> addrspace(1)* %out
40  ret void
41}
42