| 37886438dd9e8b734f1a090eb2ede48a4d184f0e |
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27-Jul-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Fix a memory leak in the hexagon scheduler. We call initialize here more
than once, and the second time through we leaked memory. Found thanks to
the vg-leak bot, but I can't locally reproduce it with valgrind. The
debugger confirms that it is in fact leaking here.
This whole code is totally gross. Why is initialize being called on each
runOnFunction??? Why aren't these OwningPtr<>s, and why aren't their
lifetimes better defined? Anyways, this is just a surgical change to
help out the leak checking bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| b86a0cdb674549d8493043331cecd9cbf53b80da |
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15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize
These can be used to more precisely model instruction execution if desired.
Disabled some misched tests temporarily. They'll be reenabled in a few commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| 54a56fad36a32f12709da5f96998336f08524be9 |
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07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| 760fa5dc8022dcf6982969c26ef566dfbeea979c |
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10-Mar-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Cleanup #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| 1c01af8f26f1ddca69d332dd8456fdeab3d1936e |
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02-Mar-2013 |
Andrew Trick <atrick@apple.com> |
Added FIXME for future Hexagon cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| ecb8c2ba6029f02b01b20b110cc1b3b3ea2e1f1c |
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13-Feb-2013 |
Andrew Trick <atrick@apple.com> |
MIsched: HazardRecognizers are created for each DAG. Free them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| 4e1fb1894048455d49d62543b3f83672b27b0000 |
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25-Jan-2013 |
Andrew Trick <atrick@apple.com> |
MIsched: Improve the interface to SchedDFS analysis (subtrees).
Allow the strategy to select SchedDFS. Allow the results of SchedDFS
to affect initialization of the scheduler state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
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03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| a78d3228e8b2a14915ea9908dbaaf2c934803e11 |
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06-Nov-2012 |
Andrew Trick <atrick@apple.com> |
ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| 412cd2f81374865dfa708bef6d5b896ca10dece0 |
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10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.
Allows the HazardRecognizer to be disabled along with itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| c6a6660c6271d3309379ff439f66eb0e6ad48e3a |
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14-Sep-2012 |
Sergei Larin <slarin@codeaurora.org> |
DAG post-process for Hexagon MI scheduler
This patch introduces a possibility for Hexagon MI scheduler
to perform some target specific post- processing on the scheduling
DAG prior to scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| e5c4fe568e91a3f6571b3cf32ef4718515628a64 |
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14-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove redundant private field.
clang warned about this being unused in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| 78e5efe1b202f71975ad93f33b1fda21d83fd1fb |
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11-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Reorganize MachineScheduler interfaces and publish them in the header.
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.
For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| 7ae51be2a3a56be5cf0ee4557aa13a069c96a241 |
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10-Sep-2012 |
Sergei Larin <slarin@codeaurora.org> |
Add "blocked" heuristic to the Hexagon MI scheduler.
Improve AQ instruction selection in the Hexagon MI scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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| 3e59040810d0e6e04269ac8f781fa44df6088458 |
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04-Sep-2012 |
Sergei Larin <slarin@codeaurora.org> |
Porting Hexagon MI Scheduler to the new API.
Change current Hexagon MI scheduler to use new converging
scheduler. Integrates DFA resource model into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
|