| 9b4053cabd8bda180b352d2d2047209f6ca5f6e8 |
|
06-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop the confusing saturate argument to math instruction setup.
This was ridiculous. We were ignoring the inst->header.saturate flag in the
case of math and only math. On gen4, we would leave inst->header.saturate in
place if it happened to be set, which would end up being applied to the
implicit mov and thus trash the first argument. On gen6, we would overwrite
inst->header.saturate with the saturate flag from the argument, which was not
set appropriately in brw_vec4_emit.cpp, and was only not a bug due to our
incompetence at coalescing saturate moves.
By ripping the argument out and making saturate work just like all the other
brw_eu_emit.c code generation, we can avoid both these classes of bugs.
Fixes piglit fog-modes, and the new specific fs-saturate-exp2 case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 148c8e639da7ee10fc9e002e3c6d60e17d218b21 |
|
19-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Use sendc for all render target writes on Gen6+.
The sendc instruction causes the fragment shader thread to wait for
any dependent threads (i.e. threads rendering to overlapping pixels)
to complete before sending the message. We need to use sendc on the
first render target write in order to guarantee that fragment shader
outputs are written to the render target in the correct order.
Previously, we only used the "sendc" instruction when writing to
binding table index 0. This did the right thing for fragment shaders,
because our fragment shader back-ends always issue their first render
target write to binding table index 0. However, it did the wrong
thing for blorp, which performs its render target writes to binding
table index 1.
A more robust solution is to use sendc for all render target writes.
This should not produce any performance penalty, since after the first
sendc, all of the dependent threads will have completed.
For more information about sendc, see the Ivy Bridge PRM, Vol4 Part3
p218 (sendc - Conditional Send Message), and p54 (TDR Registers).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 6a27506181b29c8b7eda7bd6cf80689f849e181d |
|
07-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Add support for AVG instruction.
From the Ivy Bridge PRM, Vol4 Part3 p152:
"The avg instruction performs component-wise integer average of
src0 and src1 and stores the results in dst. An integer average
uses integer upward rounding. It is equivalent to increment one to
the addition of src0 and src1 and then apply an arithmetic right
shift to this intermediate value."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 29362875f2613ad87abe7725ce3c56c36d16cf9b |
|
25-Apr-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for GL_ARB_blend_func_extended.
v2: Add support for gen6, and don't turn it on if blending is
disabled. (fixes GPU hang), and note it in docs/GL3.txt
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 9e9ae280e215988287b0f875c81bc2e146b9f5dd |
|
04-May-2012 |
Eric Anholt <eric@anholt.net> |
Revert "i965/fs: Jump from discard statements to the end of the program when done."
This reverts commit 31866308fcf989df992ace28b5b986c3d3770e90.
Fixes piglit glsl-fs-discard-exit-3 and unigine tropics rendering.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 31866308fcf989df992ace28b5b986c3d3770e90 |
|
19-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Jump from discard statements to the end of the program when done.
From the GLSL 1.30 spec:
The discard keyword is only allowed within fragment shaders. It
can be used within a fragment shader to abandon the operation on
the current fragment. This keyword causes the fragment to be
discarded and no updates to any buffers will occur. Control flow
exits the shader, and subsequent implicit or explicit derivatives
are undefined when this control flow is non-uniform (meaning
different fragments within the primitive take different control
paths).
v2: Don't emit the final HALT if no other HALTs were emitted.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 172bb92db1a3c317867d9cfec6f15c09c37a0f6c |
|
19-Feb-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Only set Last Render Target Select on the last FB write.
Fixes GPU hangs in OilRush, Trine, and Amnesia: The Dark Descent,
which all use MRT (multiple render targets).
NOTE: This is a candidate for release branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38720
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40059
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45216
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2b28fd6ca603df40a5d02aac4035eced3a1d079a |
|
22-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the MAD opcode on gen6+.
v2: Fix MRF handling on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| e910241e9754b6e673ed0fc3133c8b1de56e76c7 |
|
27-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix rendering corruption in unigine tropics.
We were allocating registers into the MRF hack region, resulting in
sparkly renering in a few of the scenes. We could do better
allocation by making an MRF class, having MRFs conflict with the
corresponding GRFs, and tracking the live intervals of the "MRF"s and
setting up the conflicts. But this is way easier for the moment.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 5f4575d42fdaaf671d4b3cdcf2c733ad9d35d339 |
|
26-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Expose brw_set_sampler_message for use outside brw_eu_emit.c.
brw_SAMPLE is full of complex workarounds for original Broadwater
hardware, and I'd rather avoid all that for my next Ivybridge patch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 5acc7f38d42859db459567d4442c18764a4072e7 |
|
17-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Bump Ivybridge's fake MRF range to g112-127 instead of g111-126.
When I originally implemented the hack to use GRFs 111+ as fake MRFs, I
did so purely to avoid rewriting all the code that dealt with MRFs.
However, it turns out that a similar hack is actually required.
Newly discovered language in the BSpec indicates that SEND instructions
with EOT set "should" use g112-g127 as their source registers. Based on
assertions in the simulator, this is actually a requirement on certain
platforms.
Since we're faking MRFs already, we may as well use the officially
sanctioned range. My guess is that we avoided this issue because we
seldom use m0: URB writes in the new VS backend start at m1, and RT
writes in the new FS backend start at m2.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| bf2c7469fba256e8d5fb3b5c6c130204550ec253 |
|
30-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Silence gcc warning from resizing EU store changes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 3aa3c3f75894ca0eb08087c0ec3dd114eeae4bb7 |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: increase the brw eu instruction store size dynamically
Here is the final patch to enable dynamic eu instruction store size:
increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would
limit it to 10000'.
v2: comments from ken, do not hardcode the eu limit to (1024 * 1024)
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 8d1b378939768c4054b35b5da592af102345ebed |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: call next_insn() before referencing a instruction by index
A single next_insn may change the base address of instruction store
memory(p->store), so call it first before referencing the instruction
store pointer from an index.
This the final prepare work to enable the dynamic store size.
v2: comments from Ken, define emit_endif as bool type
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 328e6a5497e54b0e8aed803cf6d2ae9a2a00b2fe |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: get the jmp distance by instruction index
If dynamic instruction store size is enabled, while after the brw_JMPI()
and before the brw_land_fwd_jump() function, the eu instruction store
base address(p->store) may change. Thus, the safe way to reference the
jmp instruction is by index instead of by the instruction address.
v2: comments from Eric, don't change the prototype of brw_JMPI
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 0a17093eaf84696b05d04a45d6d51281f7b2786b |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: let the if_stack just store the instruction index
If dynamic instruction store size is enabled, while after
the brw_IF/ELSE() and before the brw_ENDIF() function, the
eu instruction store base address(p->store) may change.
Thus let if_stack just store the instruction index. This is
somehow more flexible and safe than store the instruction
memory address.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| f1d89638c02afafbf82ef657cd6ba9965dad6738 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop.
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| ce6be334bbf7f44c71ad5d190f9fb075d2f9a38c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching.
The EU code itself can just do this work, since all the consumers were
duplicating it.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 32118cfe37495738ed5931c6b1a71b8ee2ad189c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 9f8814752f306cb9a26d283f0b7cf876639e10f7 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop unused do_insn argument from gen6_CONT().
The branch distances get patched up later at the WHILE instruction.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 9308f298300beaa757194a0db8ed50924754c011 |
|
28-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Initial implementation of transform feedback.
This patch adds basic transform feedback capability for Gen6 hardware.
This consists of several related pieces of functionality:
(1) In gen6_sol.c, we set up binding table entries for use by
transform feedback. We use one binding table entry per transform
feedback varying (this allows us to avoid doing pointer arithmetic in
the shader, since we can set up the binding table entries with the
appropriate offsets and surface pitches to place each varying at the
correct address).
(2) In brw_context.c, we advertise the hardware capabilities, which
are as follows:
MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64
MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4
MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16
OpenGL 3.0 requires these values to be at least 64, 4, and 4,
respectively. The reason we advertise a larger value than required
for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already
set aside 64 binding table entries, so we might as well make them all
available in both separate attribs and interleaved modes.
(3) We set aside a single SVBI ("streamed vertex buffer index") for
use by transform feedback. The hardware supports four independent
SVBI's, but we only need one, since vertices are added to all
transform feedback buffers at the same rate. Note: at the moment this
index is reset to 0 only when the driver is initialized. It needs to
be reset to 0 whenever BeginTransformFeedback() is called, and
otherwise preserved.
(4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader
program to output transform feedback data as a side effect.
(5) In gen6_gs_state.c, we configure the geometry shader stage to
handle the SVBI pointer correctly.
Note: ordering of vertices is not yet correct for triangle strips
(alternate triangles are improperly oriented). This will be addressed
in a future patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| fd5d0c8b12a0e144aa8e95540c0da2161d8e089a |
|
05-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6+: Use 1-wide null operands for IF instructions
The Sandy Bridge PRM, volume 4, part 2, section 5.3.10 ("5.3.10
Register Region Restrictions") contains the following restriction on
the execution size and operand width of instructions:
"3. ExecSize must be equal to or greater than Width."
When emitting an IF instruction in single program flow mode on Gen6+,
we use an ExecSize of 1, therefore the Width of each operand must also
be 1.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| dabe15da4f81546b5c9fca8c208d31bfe98ada9f |
|
25-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Only convert if/else to conditional adds prior to Gen6.
Normally when outputting instructions in SPF (single program flow)
mode, we convert IF and ELSE instructions to conditional ADD
instructions applied to the IP register. On platforms prior to Gen6,
flow control instructions cause an implied thread switch, so this is a
significant savings.
However, according to the SandyBridge PRM (Volume 4 part 2, p79):
[Errata DevSNB{WA}] - When SPF is ON, IP may not be updated by
non-flow control instructions.
So we have to disable this optimization on Gen6.
On later platforms, there is no significant benefit to converting flow
control instructions to ADDs, so for the sake of consistency, this
patch disables the optimization on later platforms too.
The reason we never noticed this problem before is that so far we
haven't needed to use SPF mode on Gen6. However, later patches in
this series will introduce a Gen6 GS program which uses SPF mode.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| e304aa3600f865db533d273e2c1a554cb6a54f05 |
|
15-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make gen6_resolve_implied_move a no-op for MRF sources.
Attempting to move an MRF to a MRF is not only pointless, it will fail
because MRFs are read-only, resulting in garbage in your register.
If we already set up a MRF source, there's nothing to resolve anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 7e84a64dd02794a59586ba58ef0864118534d3c6 |
|
10-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Fix sampling from integer textures.
On original gen4, the surface format didn't determine the return data
type from sampling like it does on g45 and later.
Fixes GL_EXT_texture_integer/texture_integer_glsl130
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| a73c65c5342bf41fa0dfefe7daa9197ce6a11db4 |
|
18-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable faster workaround-free math on Ivybridge.
According to the documentation, Ivybridge's math instruction works in
SIMD16 mode for the fragment shader, and no longer forbids align16 mode
for the vertex shader.
The documentation claims that SIMD16 mode isn't supported for INT DIV,
but empirical evidence shows that it works fine. Presumably the note
is trying to warn us that the variant that returns both quotient and
remainder in (dst, dst + 1) doesn't work in SIMD16 mode since dst + 1
would be sechalf(dst), trashing half your results. Since we don't use
that variant, we don't care and can just enable SIMD16 everywhere.
The documentation also still claims that source modifiers and
conditional modifiers aren't supported, but empirical evidence and
study of the simulator both show that they work just fine.
Goodbye workarounds. Math just works now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 973b4ddd0e2f25cfd72cb945fbd38aed629a6fed |
|
19-Oct-2011 |
Brian Paul <brianp@vmware.com> |
i965: remove unused vars in brw_set_ff_sync_message()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 53798f90e818e9bf213c3ae4298751362a5ecd50 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename pixel_scoreboard_clear to last_render_target for clarity.
Finding this bit in the documentation proved challenging. It wasn't in
the SEND instruction's message descriptor section, nor the data port
message descriptor section. It turns out to be part of the Render
Target Write message's control bits, and in the documentation is named
"Last Render Target Select".
Shaders that use Multiple Render Targets should set this bit on the last
RT write, but not on any prior ones.
The GPU does update the Pixel Scoreboard appropriately, but doesn't
document this bit as directly causing a scoreboard clear.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| fa0aa3796d3483cf8924fa127085d075d34019e8 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Factor out code for setting Message Descriptors.
Every brw_set_???_message function had duplicated code, per-generation,
to set the Message Descriptor and Extended Message Descriptor bits
(SFID, message length, response length, header present, end of thread).
However, these fields are actually specified as part of the SEND
instruction itself; individual types of messages don't even specify
them (except for header present, but that's in the same bit location).
Since these are exactly the same regardless of the message type, just
create a function to set them, using the generic message structs. This
not only shortens the code, but hides a lot of the per-generation
complexity (like the SFID being in destreg__conditionalmod) in one spot.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 43ccd3200c394dd4d89ed96f039ca7d6cfff972f |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove EOT parameter from brw_SAMPLE and brw_set_sampler_message.
The existing code asserted that eot == 0, as it doesn't make sense for
a thread to sample a texture as the last thing it does.
It doesn't make much sense to pass around a dead parameter either.
Especially for a function which already has a long parameter list.
So, remove the parameter and just set EOT to 0.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2e124388a4642d1e7f5154e7b83d38578c6b2789 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename BRW_MESSAGE_TARGET_* to BRW_SFID_* and document them.
When reading the data port code, it was not clear to me what these
values meant, nor where I could find them in the documentation.
Especially since the latest BSpec and older PRMs document them in
radically different places...neither of which are near the descriptions
of individual messages.
Cite the documentation, and rename them to SFID to signify that these
are Shared Function IDs that one can read about in the GPU overview,
rather than arbitrary bitfields. While we're add it, make them an enum.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| bbea5c5a5a7fb327d4ef03f80fe19cfa8d8edccd |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Clarify check for which cache to use on Gen6 data port reads.
Currently, we use the Render Cache for scratch access (read/write data)
and the Sampler Cache for all read only data (pull constants).
Reversing the condition here is clearer: if the caller requested the
Render Cache, use that. Otherwise, they requested the Data Cache
(which does not exist on Gen6) or Sampler Cache, so use the Sampler
Cache.
This should not change behavior in any way.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 0d4a9ba9b247664bc5662b3db774064778f9aa17 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use Ivybridge's "Legacy Data Port" for reads/writes.
Using the constant cache for reads isn't going to work for scratch
reads (variably-indexed arrays or register spills), as these aren't
constant at all.
Also, in the new VS backend, use the proper message number for OWord
Dual Block Write messages. It's now 10, instead of 9.
+205 piglits.
NOTE: This is a candidate for the 7.11 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| b861479f83ea140bfe24357d09f18a6d026d97b5 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix inconsistent indentation in brw_eu_emit.c.
Most of these functions used three spaces for the first level of
indentation, but four spaces for the next level. One used tabs and then
three spaces. Some used 3/4 in a then block but 3/3 in the else block.
Normally I try to avoid field days like this, but since the functions
were so inconsistent, even internally, it was making it difficult to
edit without introducing spurious whitespace changes.
So, just get it over with. git diff -b shows 0 lines changed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 6960f786c8e1bfbaa0d9eb5f43b3b6bfc7135fcf |
|
29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set the signed/unsigned type bit in Gen4/5 math messages.
It never mattered before since we only did floating point math.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 6b10aab2bbe0e69e2e8efca5e754870c8a543064 |
|
29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix message and response length calculations for INT DIV.
Both POW and INT DIV need a message length of 2; previously, we only
checked for POW.
Also, BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER has a response
length of 2; previously, we only checked for SINCOS. We don't use this
message, but in case we ever decide to, we may as well fix it now.
While we're at it, just move these computations into
brw_set_math_message, since they're entirely based on the function.
This fixes it for both brw_math and the old backend's brw_math_16.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| ee2bf3a4b6b37287e6d150d3dd6742b7fa4f8215 |
|
29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix assertions about register types for INT DIV in brw_math.
BRW_MATH_FUNCTION_REMAINDER was missing. Also, it seems worthwhile to
assert that INT DIV's arguments are signed/unsigned integers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 483f5b348b0f3c0ca7082fd2047c354e8af285e7 |
|
22-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for pull constant loads for uniform arrays.
v2: reworked the instruction emit and made use of gen6_resolve_implied_move,
from Ken's review
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| f7d2dcae3b6bf39b14c1e71f0721d0e4a2833962 |
|
18-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.
Makes the new vertex shader backend work on Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| d0c595ac8032aa9aed402a513870b8dc92e42903 |
|
12-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Force WHILE exec size to 8.
We can't just look at the instruction that happens to appear at the
start of the loop, because it might be some other exec size and cause
us to only loop on the first N channels. We always want 8 in our
current code (since 16 doesn't work so we don't do 16-wide fragment in
that case).
Fixes loop-03.vert, which was triggering the assertions.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| d376fa8e84b044ead47586d1b56a10742bcbdac7 |
|
16-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix assertion failure on a loop consisting of while (true) { break }.
On enabling the precompile step in the VS, we tripped over this
assertion failure in glsl-link-bug-30552.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 0f22f98ccd69bb5e8df3c78203bce9bc630965c1 |
|
07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Make some EU emit code for DP read/write messages non-static.
We keep building these strange interfaces for DP read/write where
there's a helper function with some partially-specific,
partially-general controls, which is used in exactly one place in code
generation. Making these public will let us set up those instructions
in the one place they're to be generated.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| b5846865deb20c54e88c7c1a7c732d29e9c47975 |
|
23-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Warnings cleanup.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 136eb2bde769713b100351ff96bceb970f068c0a |
|
10-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for "if" statements in 16-wide mode on gen6+.
It turns out there's nothing in the hardware preventing this. It
appears that it ought to work on pre-gen6 as well, but just produces
GPU hangs.
Improves glbenchmark Egypt framerate 4.4% +/- 0.3% (n=3), and Pro by
2.6% +/- 0.6% (n=3).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 344283de5d3f4e2bfa10455f6b974cf731184b55 |
|
11-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix RNDZ and RNDE on Sandybridge and Ivybridge.
On gen4/5, the RNDZ and RNDE instructions return floor(x), but set special
"round increment bits" in the flag register; a predicated ADD (+1) fixes
the result.
The documentation still lists '.r' as existing, and says that the
predicated add is necessary, but it apparently lies. According to the
simulator, BRW_CONDITIONAL_R (7) is not a valid conditional modifier
and the RNDZ and RNDE instructions simply produce the correct value.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 199a2f90abdd5dd11f8e2b95e587401d3b46f3ff |
|
11-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix data port reads on Ivybridge.
These also need to use gen7_dp.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 6e918163dfbdc829f31a0aefc07248c49b890d1d |
|
30-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make the CONT instruction point to the WHILE instruction.
This fixes piglit test glsl-fs-loop-continue.shader_test on Ivybridge.
According to the documentation, the CONT instruction's UIP field should
point to the WHILE instruction on both Sandybridge and Ivybridge.
The previous code made UIP point to the implicit DO instruction, which
seems incorrect. I'm not sure how it could have worked on Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 77397ef96edbc17a698ae2a02ec4807b1059c036 |
|
30-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for loops on Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 64ce592679a5b08d66e3cbbf964f9e695e14aee1 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge.
Ivybridge's IF instruction doesn't support conditional modifiers.
It also introduces UIP, which must point to the ENDIF instruction.
ELSE and ENDIF remain the same except that JIP moves from dst to src1.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 36f8de02e71ee5c2ca55d86c486eb00d043ae1f5 |
|
29-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix sampler message descriptor on Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 09d881bf7420c97a0f684283c24b8ec3e42404ff |
|
27-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable channel masks in Ivybridge's URB_WRITE_HWORD header.
This shouldn't be done using MRFs, but until I have a proper solution
for dealing with MRFs, this allows my hack to keep working.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 97d4d6f77e885d2c343697f26a5ecf821caaf13b |
|
19-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix the URB write message descriptor on Ivybridge.
The message header is still incorrect, but this is a start.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| ce526a7452abf552af38b86bd3546d6ff9a83194 |
|
19-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix render target writes on Ivybridge.
Ivybridge shifts the data port messages by one bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 482e8a6cd59292c58b11a9282632aaa9b24f44ae |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Mad hacks to avoid using MRFs on Ivybridge.
Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately,
a lot of our code explicitly uses MRFs, and rewriting it would take a
fair bit of effort. In the meantime, use a hack:
- Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly
convert any MRFs into the top 16 GRFs.
- Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0
actually moves it to g111 thanks to the previous hack.
It remains to officially reserve these registers so the allocator
doesn't try to reuse them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| c638180fc715aff84422c1092926120af966d417 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rework IF/ELSE jump target back-patching.
The primary motivation for this is to better support Ivybridge control
flow. Ivybridge IF instructions need to point to the first instruction
of the ELSE block -and- the ENDIF instruction; the existing code only
supported back-patching one instruction ago.
A second goal is to simplify and centralize the back-patching, hopefully
clarifying the code somewhat.
Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF
back-patched the previous instruction (IF or ELSE). With this patch,
brw_ENDIF is responsible for patching both the IF and (optional) ELSE.
To support this, the control flow stack (if_stack) maintains pointers to
both the IF and ELSE instructions. Unfortunately, in single program
flow (SPF) mode, both were emitted as ADD instructions, and thus
indistinguishable.
To remedy this, this patch simply emits IF and ELSE, rather than ADDs;
brw_ENDIF will convert them to ADDs (the SPF version of back-patching).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 5936d96d33e767aa99f6afa92f2a6582ff04df23 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move IF stack handling into the EU abstraction layer/brw_compile.
This hides the IF stack and back-patching of IF/ELSE instructions from
each of the code generators, greatly simplifying the interface.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 1309d2ea723613f1e755dd7785d22456dd39bb08 |
|
11-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_compile pointer to brw_set_src[01].
This makes it symmetric with brw_set_dest, which is convenient, and will
also allow for assertions to be made based off of intel->gen.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2bba244329a6751d5ac07041874b2969b67fa8ee |
|
13-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use BRW_DATAPORT_READ_TARGET_DATA_CACHE instead of 0.
Using the #define'd constant is better than 0 with a comment.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| c77855d64eae45786d2d637bd065c8a700b788e5 |
|
13-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename dp_render_target struct to gen6_dp.
This is actually just the message descriptor for Gen6+ dataport access;
it has nothing to do with the render cache. Access to the sampler cache
and constant cache also would use this struct; rename for clarity.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 17eaff77b09d356aae46c5d89a8eaa67cfa4c1e7 |
|
13-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Attempt to un-muddle Gen6 data port message target defines.
These are documented on page 245 of IHD_OS_Vol4_Part2.pdf (the public
Sandybridge documentation/SEND instruction description).
Somebody had the bright idea to reuse gen4/5 defines labelled READ/WRITE
which just happened to be the same values as Render Cache/Sampler Cache.
It turns out that this field has nothing to do with READ/WRITE on
Sandybridge, but rather represents which data port to direct it to.
This was especially confusing in brw_set_dp_read_message, which
used "BRW_MESSAGE_TARGET_DATAPORT_WRITE." In a read function.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 7c647a2fe98a645723fa5eace7f7f6c5c26f4f8e |
|
14-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move the destination reg setup for 8/16 wide to the emit code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 4673f9433fb73febce796945e3883274636fbf62 |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Quit spamming gen6 DP read/write send instructions with gen5 bits.
This was copy-and-paste from originally trying to get DP read/write
working reliably, and notably for other common messages (URB, sampler)
we weren't doing this.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 59c6b775a6aacfe03c84dae62c2fd45d4af9d70b |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add gen6 register spilling support.
Most of this is code movement to get the scratch space allocated in a
shared location. Other than that, the only real changes are that the
old oword block messages now operate on oword-aligned areas (with new
messages for unaligned access, which we don't do), and that the
caching control is in the SFID part of the descriptor instead of
message control.
Fixes glsl-fs-convolution-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2432ca1c2e205100d48070305ba2d5f8978bce03 |
|
12-Apr-2011 |
Zou Nan hai <nanhai.zou@intel.com> |
Revert "i965: clear global offset to zero in m0.2 for VS DP read."
This reverts commit 66b66295d0bc856c69fdcccc22575580c7ecee16.
it was already fixed by commit 9d60a7ce08a67eb8b79c60f829d090ba4a37ed7e
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 66b66295d0bc856c69fdcccc22575580c7ecee16 |
|
07-Apr-2011 |
Zou Nan hai <nanhai.zou@intel.com> |
i965: clear global offset to zero in m0.2 for VS DP read.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| a019dd0d6e5bba00e8ee7818e004ee42ca507102 |
|
03-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix null register use in Sandybridge implied move resolution.
Fixes regressions caused by commit 9a21bc6401, namely GPU hangs when
running gnome-shell or compiz (Mesa bugs #35820 and #35853).
I incorrectly refactored the case that dealt with ARF_NULL; even in that
case, the source register needs to be changed to the MRF.
NOTE: This is a candidate for the 7.10 branch (if 9a21bc6401 is
cherry-picked, take this one too).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 9d60a7ce08a67eb8b79c60f829d090ba4a37ed7e |
|
29-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Resolve implied moves in brw_dp_READ_4_vs_relative.
Fixes piglit test glsl-vs-arrays-3 on Sandybridge, as well as garbage
rendering in 3DMarkMobileES 2.0's Taiji demo and GLBenchmark 2.0's
Egypt and PRO demos.
NOTE: This a candidate for stable release branches. It depends on
commit 9a21bc640188e4078075b9f8e6701853a4f0bbe4.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 9a21bc640188e4078075b9f8e6701853a4f0bbe4 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Refactor Sandybridge implied move handling.
This was open-coded in three different places, and more are necessary.
Extract this into a function so it can be reused.
Unfortunately, not all variations were the same: in particular, one set
compression control and checked that the source register was not
ARF_NULL. This seemed like a good idea, so all cases now do so.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2279156fe7ac9718533b8b0de90ae96100486680 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename brw_(IF|CONT)_gen6 functions to gen6_(IF|CONT).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2baac48f3900b6e7a6443c6c116899cf95275629 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename BRW_DATAPORT_..._GEN6 messages to GEN6_... for consistency.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| dc987adc9f5f9f851be124985fa6bbcdbfa4a7a5 |
|
24-Dec-2010 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: use align1 access mode for instructions with execSize=1 in VS
All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c
in oglconform.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 5dc53444c8323c1787dddbe6b67048828df9c684 |
|
23-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Correct the dp_read message descriptor setup on g4x.
It's mostly like gen4 message descriptor setup, except that the sizes
of type/control changed to be like gen5. Fixes 21 piglit cases on
gm45, including the regressions in bug #32311 from increased VS
constant buffer usage.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 4374703a9b2ce0be105ee544c8402a932e3e1f52 |
|
22-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: explicit tell header present for fb write on sandybridge
Determine header present for fb write by msg length is not right
for SIMD16 dispatch, and if there're more output attributes, header
present is not easy to tell from msg length. This explicitly adds
new param for fb write to say header present or not.
Fixes many cases' hang and failure in GL conformance test.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 4fe78d3e12fa963273de4d83b1fd55a78a5d41bf |
|
21-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Avoid using float type for raw moves, to work around SNB issue.
The SNB alt-mode math does the denorm and inf reduction even for a
"raw MOV" like we do for g0 message header setup, where we are moving
values that aren't actually floats. Just use UD type, where raw MOVs
really are raw MOVs.
Fixes glxgears since c52adfc2e1d130effea940e75690897eb5d3ceaa, but no
piglit tests had regressed(!)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 3a3b1bd722786ab0b1386a3a505cadfa89798232 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 reladdr VS constant loading.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 15566183a64ef3f9940962a3b08b1c3469c98566 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 constant-index constant loading.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 14a9153a32255f186a30b500d6db412388f4de28 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up VS constant buffer location setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 7ca7e9b626389dd6dac683c6664b8478e6d5c3b9 |
|
07-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Work around gen6 ignoring source modifiers on math instructions.
With the change of extended math from having the arguments moved into
mrfs and handed off through message passing to being directly hooked
up to the EU, it looks like the piece for doing source modifiers
(negate and abs) was left out.
Fixes:
fog-modes
glean/fp1-ARB_fog_exp test
glean/fp1-ARB_fog_exp2 test
glean/fp1-Computed fog exp test
glean/fp1-Computed fog exp2 test
ext_fog_coord-modes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 72845d206e692581b6084c56b8d1f3bc689e8a03 |
|
07-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Handle saturates on gen6 math instructions.
We get saturate as an argument to brw_math() instead of as compile
state, since that's how the pre-gen6 send instructions work. Fixes
fp-ex2-sat.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 245662f3083795e272fe9ef5d4cbeb6d048cf0e5 |
|
03-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the instruction compression bits on gen6.
Since the 8-wide first-quarter and 16-wide first-half have the same
bit encoding, we now need to track "do you want instruction
compression" in the compile state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 237aa33c67039f6660cac19f061057250b8b3697 |
|
04-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Make the sampler's implied move on gen6 be a raw move.
We were accidentally doing a float-to-uint conversion.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 5340dd8ccacda82d4e68a4357f90503c84831594 |
|
03-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up gen6 samplers for their usage by brw_wm_emit.c
We were trying to do the implied move even when we'd already manually
moved the real header in place.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| ae0df25ab439508c8bca707b91bbf085ff16d47c |
|
13-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't smash a group of coordinates doing gen6 16-wide sampler headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 843a6a308e05bd4bf2056e08ec65ac4770097b93 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 CONTINUE instruction emit.
At this point, piglit tests for fragment shader loops are working.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 00e5a743e2ee3981a34b95067a97fa73c0f5d779 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 BREAK ISA emit.
There are now two targets: the hop-to-end-of-block target, and the
target for where to resume execution for active channels.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 4890e0f09c934e3ffb692b417e5444e43685c876 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 DO/WHILE ISA emit.
There's no more DO since there's no more mask stack, and WHILE has
been shuffled like IF was.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 9249af17b857e8d9a359b4cd04e9393aca517e9c |
|
10-Nov-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fix dest type of 'endif' on sandybridge
That should also be immediate value for type W.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 88087ba1bf5566c8fe1c7d88028d2485126af286 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Drop the eot argument to read messages, which can never be set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 3ee5d68075d1b198c92daf01826aba83a35fccf5 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for constant buffer loads on gen6.
Fixes glsl-fs-uniform-array-5.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 1732a8bc72fe0a8eaf7449eda65eba1a017ae909 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use SENDC on the first render target write on gen6.
This is apparently required, as the thread will be initiated while it
still has dependencies, and this is what waits for those to be
resolved before writing color.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 748f3744bebc37cc753a5ea1c321854c580a7317 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clarify an XXX comment in FB writes with real info.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 3789d5025a3200c40a39119c94c3d38a13e4b65a |
|
25-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add EU code for dword scattered reads (constant buffer array indexing).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 07cd8f46acc34b04308f81de2faf05ba33da264b |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for pull constants to the new FS backend.
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 0b77d57394a3712851ec271aa7ad353d56f302a1 |
|
21-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't emit register spill offsets directly into g0.
g0 is used by others, and is expected to be left exactly as it was
dispatched to us. So manually move g0 into our message reg when
spilling/unspilling and update the offset in the MRF. Fixes failures
in texture sampling after having spilled a register.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 99b2c8570ea6f46c6564681631f0e0750a0641cc |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for register spilling.
It can be tested with if (0) replaced with if (1) to force spilling for all
virtual GRFs. Some simple tests work, but large texturing tests fail.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 6ea108e7db79cb7135a8a1ef216e25381f72c225 |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the source operand types for gen6 if/else/endif to integer.
I don't think this should matter, but I'm not sure, and it's
recommended by a kernel checker in fulsim.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| d0c87b90a85af0bd9ca7f8cec411a458742190cc |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add EU emit support for gen6's new IF instruction with comparison.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| f157812bbbcf9caac1f84988e738fc9d1e051056 |
|
14-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for ir_unop_round_even via the RNDE instruction.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 897f6d3c7d06316b0535971cc2de318157c23692 |
|
14-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correctly emit the RNDZ instruction.
Simply using RNDU, RNDZ, or RNDE does not produce the desired result.
Rather, the RND* instructions place a value in the destination register
that may be 1 less than the correct answer. They can also set per-channel
"increment bits" in a flag register, which, if set, mean dest needs to
be incremented by 1. A second instruction - a predicated add -
completes the job.
Notably, RNDD always produces the correct answer in a single
instruction.
Fixes piglit test glsl-fs-trunc.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| e8e79c1d7eed0f5ae8820611cb86bdbd6ce595e6 |
|
14-Oct-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Fix GS hang on Sandybridge
Don't use r0 for FF_SYNC dest reg on Sandybridge, which would
smash FFID field in GS payload, that cause later URB write fail.
Also not use r0 in any URB write requiring allocate.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 7b5bc38c44269fc51db2f8b5e4ba0222212c6d71 |
|
11-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a couple of checks for gen6 math instruction limits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 978ffa1d61902f0d55e15fbc51af75d444f35124 |
|
09-Oct-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Silence unused variable warning on non-debug builds.
Fixes this GCC warning.
brw_eu_emit.c: In function 'brw_math2':
brw_eu_emit.c:1189: warning: unused variable 'intel'
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| feca6609390d4642418cf7aab878e654964510c4 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up IF/ELSE/ENDIF for gen6.
The jump delta is now in the part of the instruction where the
destination fields used to be, and the src args are ignored (or not,
for the new non-predicated IF that we don't use yet).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| f7cb28fad9855020e9fbd1481df03bb09346d4be |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Gen6 no longer has the IFF instruction; always use IF.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| ea909be58dda7e916cb9ce434ecb78597881ad33 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 FB writes to the new FS.
This uses message headers for now, since we'll need it for MRT. We
can cut out the header later.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 956f866030f7bea5fc4a2de28c72e60bdc3a5b3d |
|
17-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Fix sampler on sandybridge
Sandybridge has not much change on texture sampler with Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| c5a3b25bb954db49dcb5e7737018979782d2edba |
|
28-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fix jump count on sandybridge
Jump count is for 64bit long each, so one instruction requires 2
like on Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 67dafa4b56422b44ca26b093d8feb6e743eb89e6 |
|
17-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: ff sync message change for sandybridge
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| fe2d4a5ea02df38c9940a726aa04bcf550fab1da |
|
22-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for POW in gen6 FS.
Fixes glsl-algebraic-pow-2 in brw_wm_glsl.c mode.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| a560a509fab467b0ed4be2bceaf1c5a60890ca0d |
|
05-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add some validation on BRW_OPCODE_MUL and ADD's arguments.
Now that we're playing with other types in brw_fs.cpp, it's easy to
trip over issues like these.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 0002069fd5117b52f0ae2be0b7e3d8e839a3a61c |
|
05-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add assertion for another requirement about types.
This catches a failure in the FS backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 5c777928591279886e015c10f640828f77b97559 |
|
04-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a bit of validation for some ISA restrictions in the docs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 352dff62f8005add9e71e6b5ba3b3321cb953d73 |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Make brw_CONT and brw_BREAK take the pop count.
We always need to set it, so pass it in.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| e6ec500e19f455237828f4f3955f888ad0b56382 |
|
21-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 5266c0a0c82de625ccac57e7559f57399f761e9e |
|
21-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add support for FB writes on Sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 3ce2eccbfb925a3af0b91a89a9f7a3603fa45d2d |
|
21-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Set the destination horiz stride even for da16, as SNB seems to need it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 21eaa62ba461854003e5f74e6fc32e559e9c8455 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 96b11f1e3ee12f06be1d33bf085bf1353f23e667 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Support relative addressed VS constant reads using the appropriate msg.
The previous support was overly complicated by trying to use the same
1-OWORD message for both offsets.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 04de6861c1a41859dd85ca066b964e5df3ad63b6 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i956: Set the execution size correctly for scratch space writes.
Otherwise, the second half isn't written, and we end up reading back
black.
Fixes the remaining junk drawn in glsl-max-varyings, and will likely
help with a number of large real-world shaders.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| a3bfb2f755cb2255879600d12d8440fad7136a9a |
|
21-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the pretty define for 4-oword DP reads.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| d2f3eac8ffba8db8b141f07c22f612362c63ffe9 |
|
21-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the send commit bit on register spills as required pre-gen6.
Otherwise, the subsequent read may not get the written value.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 20be3ff57670529a410b30a1008a71e768d08428 |
|
25-Jun-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add 'wait' instruction support
When EU executes 'wait' instruction, it stalls and sets notification
register state. Host can issue MMIO write to clear notification
register state to allow EU continue on executing again.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 5dbbb48f46f99baeba3a24a8371029e216b931bb |
|
13-Jun-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Use the new message header format for FF_SYNC on gen6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 881ec3a81455f8449d06429811107e1f955f2c60 |
|
13-Jun-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add support for math instructions in the gen6 WM.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 81951393e1e675d6ca3ea052875def70d5e7ab93 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove constant or ignored-by-hw args from FF sync message setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| a9acde6a723c8f343f65243d1ccac6836215ba0c |
|
19-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Ignore execution mask for the mov(m0, g0) of VS URB write header on SNB.
Otherwise, we may not get the FFTID set up which would break freeing
of resources.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 56ff30a9f97a1a7094432333906544d6138d6bf2 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the PLN instruction when possible in interpolation.
Saves an instruction in PINTERP, LINTERP, and PIXEL_W from
brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have
to be laid out differently.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| dc8c0359448cdae7b367552ba58783c04b199778 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set up the execution size before relying on it.
Fixes hangs with texturing in the non-GLSL path since
f6d210c284751ac50a8d6358de7e75a1ff1e4ac7
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| f6d210c284751ac50a8d6358de7e75a1ff1e4ac7 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the response len of masked sampler messages for 8-wide dispatch.
The bad response length would hang the GPU with a masked sample in a
shader using control flow. For 8-wide, the response length is always
4, and masked slots are just not written to. brw_wm_glsl.c already
allocates registers in the right locations.
Fixes piglit glsl-fs-bug25902 (fd.o bug #25902).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 839e6bd8b90a124e88020d54ded46460b2a3bc2d |
|
26-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Try to hook up the Sandybridge URB_WRITE SEND message.
My units still hang when doing this if the VS is enabled.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 38c449409207c8948c1961a3132475bbd422f8f1 |
|
24-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add SNB math opcode support.
This is untested at this point.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 25024d948298a9f3f3210a0b91486f79a3917b0f |
|
31-Dec-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
configs/darwin
src/gallium/auxiliary/util/u_clear.h
src/gallium/state_trackers/xorg/xorg_exa_tgsi.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c67bb15d4e3da430d511444bd7d159ccb0c84b73 |
|
29-Dec-2009 |
Vinson Lee <vlee@vmware.com> |
intel: Silence compiler warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| d0b7ff551ab25153e3023871af3daa65b394a828 |
|
27-Dec-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch' into mesa_7_7_branch
Conflicts:
src/gallium/auxiliary/util/u_network.c
src/gallium/auxiliary/util/u_network.h
src/gallium/drivers/i915/i915_state.c
src/gallium/drivers/trace/tr_rbug.c
src/gallium/state_trackers/vega/bezier.c
src/gallium/state_trackers/vega/vg_context.c
src/gallium/state_trackers/xorg/xorg_crtc.c
src/gallium/state_trackers/xorg/xorg_driver.c
src/gallium/winsys/xlib/xlib_brw_context.c
src/mesa/main/mtypes.h
|
| 2447786ed00a19466c9cc9b9efbfa084e88114eb |
|
25-Dec-2009 |
Vinson Lee <vlee@vmware.com> |
i965: Fix assert.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 0b87f143c466f7e5bd730895ee29f1cd20a68f9b |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_G4X() across the driver with context structure usage.
Saves ~2KB of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 8baee3d25beb616f6d5ba575684e889d60e38740 |
|
07-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use Compr4 instruction compression mode on G4X and newer.
No statistically significant performance difference at n=3 with either
openarena or my GL demo, but cutting program size seems like a good
thing to be doing for the hypothetical app that has a working set near
icache size.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 011244853b538a1a5adf602c8ed2de5c0f047548 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Don't set pop_count in the reserved MBZ area of IF statements.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| b010814e9c7ed30cbdd60a49d81a6ea774c8c3a3 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Spell "conditional" correctly.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 868aa160745ed0b3f1a83353ef2f3a8fcb5d235e |
|
15-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNG
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 73137997e23ff6c1145d036315d1a9ad96651281 |
|
02-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fixes for JMPI
1. the data type of <src1> (JMPI offset) must be D
2. execution size must be 1
3. NoMask
4. instruction compression isn't allowed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 1b6ae2e004b7a7a76508e0da3c45eb0d851ed10c |
|
01-Jul-2009 |
Brian Paul <brianp@vmware.com> |
i965: use BRW_MAX_MRF
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 4fdc6ad41b843109febbe9596dde87f676a8b0e9 |
|
26-Jun-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: fix fetching constants from constant buffer in glsl path
the driver used to overwrite grf0 then use implicit move by send instruction
to move contents of grf0 to mrf1. However, we must not overwrite grf0 since
it's still used later for fb write.
Instead, do the move directly do mrf1 (we could use implicit move from another
grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't
seem to make sense).
I think the dp_READ/WRITE_16 functions may suffer from the same issue.
While here also remove unnecessary msg_reg_nr parameter from the dataport
functions since always message register 1 is used.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 0bc214a834bbb12b9338837dd9fca9bc389b4bc2 |
|
18-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i915: fix broken indirect constant buffer reads
The READ message's msg_control value can be 0 or 1 to indicate that the
Oword should be read into the lower or upper half of the target register.
It seems that the other half of the register gets clobbered though. So
we read into two dest registers then use a MOV to combine the upper/lower
halves.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| ee32e9b4753eca62e360f96ce61ef7ff683e6bb7 |
|
16-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement relative addressing for VS constant buffer reads
A scatter-read should be possible, but we're just using two READs for
the time being.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 92cc9970039d9c9385dc472fbfac58b93799f5ae |
|
15-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix VS constant buffer reads
This mostly came down to finding the right MRF incantation in the
brw_dp_READ_4_vs() function.
Note: this feature is still disabled (but getting close to done).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| cafea7528052624c8d3e4cd1c5b26a61bf04d1d0 |
|
14-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: checkpoint commit: VS constant buffers
Hook up a constant buffer, binding table, etc for the VS unit.
This will allow using large constant buffers with vertex shaders.
The new code is disabled at this time (use_const_buffer=FALSE).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2078e6cf55e3068454df9d843618b412b6abb811 |
|
10-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: new SURF_INDEX_ macros
Used to map drawables, textures and constant buffers to surface binding
table indexes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 8131123effd2124b8ca2aad04bf543e2fe82c7b0 |
|
09-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: set BRW_MASK_DISABLE flag in "send" instruction in brw_dp_READ_4()
This fixes the random results that were seen when fetching a constant
inside an IF/ELSE clause. Disabling the execution mask ensures that all
the components of the register are written.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| a330a6fcd0b018829194ffab260f50956bce4832 |
|
02-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: s/GL_FALSE/BRW_COMPRESSION_NONE/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 30adf0518168ded9c7f519a7c772cab728852b1f |
|
01-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix response length param in brw_dp_READ_4()
We were accidentally clobbering the next register.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 8127e49b93820d1768e2d298bbe238dd55c20732 |
|
31-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: added new brw_dp_READ_4() function
Used to read float[4] vectors from the constant buffer/surface.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 6b18a8d3e7114a1af931a2fc20a1e23cb2d7789c |
|
31-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: new and updated comments
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 1146d40b9c35d80c0860c773de1eef27c76e8c01 |
|
25-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: comments for brw_SAMPLE()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| a10ec13143599344ecb4a486db1454b488cd9645 |
|
13-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: add some register number assertions
Haven't seen failures yet, but if/when there are, more investigation will
be done.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 2f2082bf16ca86b8ebea9e04b77011f74d09c3db |
|
12-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: minor clean-ups
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 0d797365deb579cfeb2a32f21692515eb6904921 |
|
05-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement OPCODE_TRUNC (round toward zero) on vertex path.
Also, fix some RNDD vs. RNDZ confusion elsewhere.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 34b1776e8d965605d12807884c9c447214d57281 |
|
02-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Merge GM45 into the G4X chipset define.
The mobile and desktop chipsets are the same, and having them separate is
more typing and more chances to screw up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 72c914805b8b3b37bf8f44d94bc25ca3d146ac66 |
|
01-Nov-2008 |
Keith Packard <keithp@keithp.com> |
Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1
Quoting section 11.3.10, paragraph 10.2 of the 965PRM:
10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is
relaxed from rule 10.1.2. Also note that this rule for destination
horizontal stride is different from that for source as stated in
rule #7.
GM45 gets very angry when rule 10.2 is violated.
Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode)
added support for additional horizontal strides in the ExecSize 1 case, but
failed to notice that mesa occasionally re-purposes a register as a
temporary destination, even though it was constructed as a repeating source
with HorzStride = 0.
While, ideally, we should probably fix the code using these register
specifications, this patch simply rewrites them to use HorzStride 1 as the
pre-58dc8b7 code did.
Signed-off-by: Keith Packard <keithp@keithp.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 58dc8b7db5829188dbb45c020ab44732d6053888 |
|
30-Oct-2008 |
Gary Wong <gtw@gnu.org> |
i965: support destination horiz strides in align1 access mode.
This is required for scatter writes in destination regions to work.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 7a2ab6d05573508389b38f8f1fa261ba56062865 |
|
29-Aug-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: force thread switch after IF/ELSE/ENDIF. partial fix for #16882.
A thread switch is implicitly invoked after the issuance of an IF/ELSE/ENDIF
instruction if necessary. Unfortunately it seems sometimes a forced thread
switch is needed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 6073b49c7915147c28e9887039a51b8e4e2e62c5 |
|
29-Aug-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: mask control for BREAK/CONT/DO/WHILE. partial fix fox #16882
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 92c075eeb7c330ea420400d1c2bae57356b19f03 |
|
08-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: official name for GM45 chipset
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 46e03d584a18b89fef956fed3d52e15775846250 |
|
27-Nov-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: The jump instruction count is added
to IP pre-increment, and should point to
the first instruction after the do instruction
of the do-while block of code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| b0b48798c7e854d2e36e0317bf94b7385e815242 |
|
29-Sep-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support continue, fix conditional
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| d19d0596daf004b56d80f78fa1a329b43c2ebf94 |
|
21-Jun-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support branch and loop in pixel shader
most of the sample working with some small modification
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 35707dbe57873adb5a8088cd47c13bd216e143e4 |
|
12-Apr-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Initial 965 GLSL support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 1b9f78195f62959601d440475a6cbba5e8046813 |
|
18-Oct-2006 |
Eric Anholt <eric@anholt.net> |
i965: Avoid branch instructions while in single program flow mode.
There is an errata for Broadwater that threads don't have the instruction/loop
mask stacks initialized on thread spawn. In single program flow mode, those
stacks are not writable, so we can't initialize them. However, they do get
read during ELSE and ENDIF instructions. So, instead, replace branch
instructions in single program flow mode with predicated jumps (ADD to the ip
register), avoiding use of the more complicated branch instructions that may
fail. This is also a minor optimization as no ENDIF equivalent is necessary.
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| db0e53af74beafa0ba07b200396bfe12fa9f5c89 |
|
01-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
fix a couple of cases where a message reg is used as an instruction source.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu_emit.c
|