History log of /hardware/qcom/display/msm8974/libhwcomposer/hwc_copybit.h
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7fedef6549adbbffe15188e96ac6a5de272de27e 05-Aug-2013 Shivaraj Shetty <shivaraj@codeaurora.org> HWC/copybit : Add support to indicate driver on layer with Zorder 0

Some applications send RGBA layer with constant alpha 0xFF and
isOpaque=1. For these types of layer we don't get any wormHole
regions. Hence we see the previous content (framebuffer) due to
wrong selection of blending logic at kernel side.

To fix these kind of issues on MDP3 we make layer with Z order
zero as FG layer. This makes sure that proper blending logic
is chosen in kernel.

CRs-fixed: 521638
CRs-fixed: 517944
Change-Id: I172a46c3284916264a1413a6a16875afea2b1aad
/hardware/qcom/display/msm8974/libhwcomposer/hwc_copybit.h
39fd54ca5748e660fd3c05131b94bcab33121cd3 03-Jul-2013 Xiaoming Zhou <zhoux@codeaurora.org> hwcomposer: 8x10: increase frame buffer count to 3 for copybit

On 8x10, ppp composition is enabled. For PPP blending operation,
it can take around 14-15ms. This results that when the frame is
given to the display for rendering, it can happen around the
vsync boundary. While DMA does the page flipping, it makes sure
it happens on vsync boundary. However, in the ppp case, the vsync
can be from the previous frame, not the new frame just delivered.
Because of that, there will be tearing. Increase the buffer count
to 3 will resolve this issue, and improve the frame rate as well.

Change-Id: I53bff1a61b38eaecd286fdbe8a069522e28df6ba
/hardware/qcom/display/msm8974/libhwcomposer/hwc_copybit.h
513ddc2124abf90c63af41999201f0d2031af0c8 12-Jun-2013 Vineeta Srivastava <vsrivastava@google.com> Splitting hardware/qcom/display chip specific.

Moved msm8960 specific code in msm8960/ directory.
Moved msm8974 specific code in msm8974/ directory.
Updated Makefiles to point to correct header files.

Change-Id: I0623022f324be0ae42571660074f16afa1f71df5
/hardware/qcom/display/msm8974/libhwcomposer/hwc_copybit.h