/external/llvm/lib/CodeGen/ |
H A D | AntiDepBreaker.h | 61 /// other machine instruction to use NewReg. 62 void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) { argument 65 MI->getOperand(0).setReg(NewReg);
|
H A D | CriticalAntiDepBreaker.cpp | 303 // be replaced by NewReg. Return true if any of their parent instructions may 308 // the two-address instruction also defines NewReg, as may happen with 312 // both NewReg and AntiDepReg covers it. 316 unsigned NewReg) 322 // operands, in case they may be assigned to NewReg. In this case antidep 327 // Handle cases in which this instructions defines NewReg. 332 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) 336 CheckOper.getReg() != NewReg) 339 // Don't allow the instruction to define NewReg and AntiDepReg. 345 // NewReg 314 isNewRegClobberedByRefs(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned NewReg) argument 368 unsigned NewReg = Order[i]; local [all...] |
H A D | MachineSSAUpdater.cpp | 233 void MachineSSAUpdater::ReplaceRegWith(unsigned OldReg, unsigned NewReg) { argument 234 MRI->replaceRegWith(OldReg, NewReg); 240 I->second = NewReg;
|
H A D | MachineCSE.cpp | 522 unsigned NewReg = CSMI->getOperand(i).getReg(); local 528 if (OldReg == NewReg) { 534 TargetRegisterInfo::isVirtualRegister(NewReg) && 537 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) { 546 if (!MRI->constrainRegClass(NewReg, OldRC)) { 552 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
|
H A D | StrongPHIElimination.cpp | 139 // Merges the live interval of Reg into NewReg and renames Reg to NewReg 140 // everywhere that Reg appears. Requires Reg and NewReg to have non- 142 void MergeLIsAndRename(unsigned Reg, unsigned NewReg); 310 unsigned NewReg = RegRenamingMap[SrcColor]; local 311 if (!NewReg) { 312 NewReg = SrcReg; 315 MergeLIsAndRename(SrcReg, NewReg); 319 MergeLIsAndRename(DestReg, NewReg); 323 MergeLIsAndRename(SrcReg, NewReg); 342 unsigned NewReg = RegRenamingMap[DestColor]; local 797 MergeLIsAndRename(unsigned Reg, unsigned NewReg) argument [all...] |
H A D | TailDuplication.cpp | 84 void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, 369 void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, argument 373 LI->second.push_back(std::make_pair(BB, NewReg)); 376 Vals.push_back(std::make_pair(BB, NewReg)); 432 unsigned NewReg = MRI->createVirtualRegister(RC); local 433 MO.setReg(NewReg); 434 LocalVRMap.insert(std::make_pair(Reg, NewReg)); 436 AddSSAUpdateEntry(Reg, NewReg, PredBB);
|
H A D | TwoAddressInstructionPass.cpp | 666 unsigned NewReg = 0; local 669 NewReg, IsDstPhys)) { 679 VirtRegPairs.push_back(NewReg); 682 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second; 684 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!"); 685 VirtRegPairs.push_back(NewReg); 686 Reg = NewReg;
|
H A D | RegisterCoalescer.cpp | 616 unsigned NewReg = NewDstMO.getReg(); local 617 if (NewReg != IntB.reg || !LiveRangeQuery(IntB, AValNo->def).isKill()) 680 UseMO.setReg(NewReg); 689 if (TargetRegisterInfo::isPhysicalRegister(NewReg)) 690 UseMO.substPhysReg(NewReg, *TRI); 692 UseMO.setReg(NewReg);
|
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 258 MCOperand NewReg; local 263 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0, 265 NewMI.addOperand(NewReg);
|
/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineCXX.cpp | 386 const MemRegion *NewReg = symVal.castAs<loc::MemRegionVal>().getRegion(); local 389 getStoreManager().GetElementZeroRegion(NewReg, ObjTy);
|
/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 654 unsigned NewReg = optimizeSDPattern(MI); local 656 if (NewReg != 0) { 662 << PrintReg(NewReg) << "\n"); 663 (*I)->substVirtReg(NewReg, 0, *TRI); 666 Replacements[MI] = NewReg;
|
H A D | ARMBaseRegisterInfo.cpp | 246 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, argument 261 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
|
H A D | ARMBaseInstrInfo.cpp | 2375 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); local 2378 get(NewUseOpc), NewReg) 2382 UseMI->getOperand(1).setReg(NewReg);
|
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 575 unsigned NewReg = RegInfo.createVirtualRegister(TRC); local 576 return NewReg;
|
/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 597 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords()); local 598 Elts.insert(NewReg); 604 NewReg->addSuperClass(Supers[i], Ranges[i]); 611 if (NewReg->getValue(RV.getNameInit())) 635 NewReg->addValue(*Def->getValue(Field)); 644 NewReg->addValue(*DefRV); 649 NewReg->addValue(RV);
|
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5140 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, local 5144 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
|