/external/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 299 MachineOperand Op2 = MI->getOperand(S2); local 300 ChangeOpInto(MI->getOperand(S1), Op2);
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H A D | HexagonHardwareLoops.cpp | 524 const MachineOperand &Op2 = CondI->getOperand(2); local 528 if (Op2.isImm() || Op1.getReg() == IVReg) 529 EndValue = &Op2;
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 786 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local 791 Ops[4].getAsInteger(10, Op2); 792 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 818 uint32_t Op2 = Bits & 0x7; local 831 + "_c" + utostr(CRm) + "_" + utostr(Op2);
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/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument 265 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument 280 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 358 unsigned Op1, Op2; local 359 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 364 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 371 unsigned Op1, Op2; local 372 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 377 DecodeGRRegsRegisterClass(Inst, Op2, Addres 384 unsigned Op1, Op2; local 397 unsigned Op1, Op2; local 411 unsigned Op1, Op2; local 424 unsigned Op1, Op2; local 437 unsigned Op1, Op2; local 522 unsigned Op1, Op2; local 536 unsigned Op1, Op2; local 550 unsigned Op1, Op2, Op3; local 563 unsigned Op1, Op2, Op3; local 576 unsigned Op1, Op2, Op3; local 589 unsigned Op1, Op2, Op3; local 602 unsigned Op1, Op2, Op3; local 616 unsigned Op1, Op2, Op3; local 631 unsigned Op1, Op2, Op3; local 645 unsigned Op1, Op2, Op3; local 659 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 693 unsigned Op1, Op2, Op3, Op4, Op5; local 713 unsigned Op1, Op2, Op3; local 732 unsigned Op1, Op2, Op3; local [all...] |
/external/llvm/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 594 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 599 Ops.push_back(Op2); 612 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 617 Ops.push_back(Op2);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 581 SDValue Op2 = Op.getOperand(2); local 584 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 620 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 627 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); 628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 659 SDValue Op2 = Op.getOperand(2); local 687 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); [all...] |
H A D | FastISel.cpp | 1263 unsigned Op2, bool Op2IsKill) { 1271 .addReg(Op2, Op2IsKill * RegState::Kill); 1276 .addReg(Op2, Op2IsKill * RegState::Kill); 1259 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
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H A D | TargetLowering.cpp | 2443 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, argument 2445 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 2463 Op2 = DAG.getConstant(xn, Op1.getValueType()); 2464 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
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H A D | LegalizeIntegerTypes.cpp | 181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 185 Op2, N->getMemOperand(), N->getOrdering(), 194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 198 Op2, Op3, N->getMemOperand(), N->getOrdering(), 865 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 867 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), 1416 unsigned Op1, Op2; local 1419 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1421 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1430 SDValue Sh1 = DAG.getNode(Op2, d [all...] |
H A D | LegalizeVectorTypes.cpp | 138 SDValue Op2 = GetScalarizedVector(N->getOperand(2)); local 140 Op0.getValueType(), Op0, Op1, Op2);
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H A D | SelectionDAG.cpp | 271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 273 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 277 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 295 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 297 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 302 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 751 SDValue Op1, SDValue Op2, 756 SDValue Ops[] = { Op1, Op2 }; 4957 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { argument 4961 if (Op1 == N->getOperand(0) && Op2 750 FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, void *&InsertPos) argument 4986 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) argument 4992 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument 4999 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument 5069 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) argument 5077 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5127 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5135 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5144 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 5291 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument 5299 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5328 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5336 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5353 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument 5362 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument [all...] |
H A D | SelectionDAGBuilder.cpp | 2644 SDValue Op2 = getValue(I.getOperand(1)); local 2646 Op2.getValueType(), Op2)); 2655 SDValue Op2 = getValue(I.getOperand(1)); local 2657 Op1.getValueType(), Op1, Op2)); 2662 SDValue Op2 = getValue(I.getOperand(1)); local 2664 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType()); 2667 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2669 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2674 Op2 2694 SDValue Op2 = getValue(I.getOperand(1)); local 2716 SDValue Op2 = getValue(I.getOperand(1)); local 2730 SDValue Op2 = getValue(I.getOperand(1)); local 4490 SDValue Op2 = getValue(I.getArgOperand(1)); local 4508 SDValue Op2 = getValue(I.getArgOperand(1)); local 4527 SDValue Op2 = getValue(I.getArgOperand(1)); local 5148 SDValue Op2 = getValue(I.getArgOperand(1)); local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 526 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument 532 Ops.push_back(Op2); 765 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); 766 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 768 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 770 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 782 SDValue Op1, SDValue Op2); 784 SDValue Op1, SDValue Op2, SDValue Op3); 798 EVT VT2, SDValue Op1, SDValue Op2); 800 EVT VT2, SDValue Op1, SDValue Op2, SDValu [all...] |
/external/llvm/include/llvm/Support/ |
H A D | PatternMatch.h | 1101 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument 1102 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2)); 1107 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument 1108 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
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/external/llvm/lib/Bitcode/Reader/ |
H A D | BitcodeReader.cpp | 1413 Constant *Op2 = ValueList.getConstantFwdRef(Record[2], local 1415 V = ConstantExpr::getInsertElement(Op0, Op1, Op2); 1426 Constant *Op2 = ValueList.getConstantFwdRef(Record[2], ShufTy); local 1427 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2); 1440 Constant *Op2 = ValueList.getConstantFwdRef(Record[3], ShufTy); local 1441 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
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/external/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.cpp | 605 unsigned Op1, Op2, NewDstIdx; local 606 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 609 NewDstIdx = Op2; 610 else if (Op2 == UseOpIdx)
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/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 1688 const Value *Op2 = I.getArgOperand(1); local 1690 unsigned Reg2 = getRegForValue(Op2);
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H A D | X86ISelDAGToDAG.cpp | 2785 SDValue Op0, Op1, Op2, Op3, Op4; local 2791 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4)) 2798 OutOps.push_back(Op2);
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCompares.cpp | 2454 Value *Op1 = 0, *Op2 = 0; local 2458 Op2 = ConstantExpr::getICmp(I.getPredicate(), C, RHSC); 2466 if ((Op1 && Op2) || (LHSI->hasOneUse() && (Op1 || Op2))) { 2470 if (!Op2) 2471 Op2 = Builder->CreateICmp(I.getPredicate(), LHSI->getOperand(2), 2473 return SelectInst::Create(LHSI->getOperand(0), Op1, Op2); 3251 Value *Op1 = 0, *Op2 = 0; local 3257 Op2 = Builder->CreateFCmp(I.getPredicate(), 3261 Op2 [all...] |
/external/llvm/lib/IR/ |
H A D | Instructions.cpp | 62 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) { argument 63 if (Op1->getType() != Op2->getType())
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 118 unsigned Op2, bool Op2IsKill); 348 unsigned Op2, bool Op2IsKill) { 356 .addReg(Op2, Op2IsKill * RegState::Kill)); 361 .addReg(Op2, Op2IsKill * RegState::Kill)); 1847 unsigned Op2 = getRegForValue(I->getOperand(1)); local 1848 if (Op2 == 0) return false; 1853 .addReg(Op1).addReg(Op2)); 344 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
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H A D | ARMISelLowering.cpp | 6309 unsigned Op1, unsigned Op2, 6416 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), tmpRegHi) 6308 EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, unsigned Op1, unsigned Op2, bool NeedsCarry, bool IsCmpxchg, bool IsMinMax, ARMCC::CondCodes CC) const argument
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 152 ICToken Op2 = OperandStack.pop_back_val(); local 159 Val = Op1.second + Op2.second; 163 Val = Op1.second - Op2.second; 167 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 169 Val = Op1.second * Op2.second; 173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 175 assert (Op2.second != 0 && "Division by zero!"); 176 Val = Op1.second / Op2.second; 2017 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 2018 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) { 2030 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 2044 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 2057 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); local 2087 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); local [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5122 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]); local 5125 // Adjust only if Op1 and Op2 are GPRs. 5126 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) && 5127 MRC.contains(Op2->getReg())) { 5129 unsigned Reg2 = Op2->getReg(); 5135 Error(Op2->getStartLoc(), isLoad ? 5144 NewReg, Op1->getStartLoc(), Op2->getEndLoc())); 5146 delete Op2;
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