/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.h | 31 const TargetRegisterClass *RegClass; // E.g. GPR64RegClass member in struct:llvm::AArch64FrameLowering::LoadStoreMethod
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H A D | AArch64AsmPrinter.cpp | 35 const TargetRegisterClass &RegClass, 41 if (RegClass.contains(*AR)) { 53 const TargetRegisterClass &RegClass, 55 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x'; 67 if (RegClass.contains(*AR)) { 33 printModifiedFPRAsmOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI, const TargetRegisterClass &RegClass, raw_ostream &O) argument 51 printModifiedGPRAsmOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI, const TargetRegisterClass &RegClass, raw_ostream &O) argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 46 OwningArrayPtr<RCInfo> RegClass; member in class:llvm::RegisterClassInfo 72 const RCInfo &RCI = RegClass[RC->getID()];
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H A D | RegisterScavenging.h | 125 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const; 154 unsigned scavengeRegister(const TargetRegisterClass *RegClass, 156 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { argument 157 return scavengeRegister(RegClass, MBBI, SPAdj);
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 77 unsigned RegClass = Desc.OpInfo[OpNo].RegClass; local 78 return (AMDGPU::SSrc_32RegClassID == RegClass) || 79 (AMDGPU::SSrc_64RegClassID == RegClass) || 80 (AMDGPU::VSrc_32RegClassID == RegClass) || 81 (AMDGPU::VSrc_64RegClassID == RegClass);
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/external/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 101 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ argument 102 assert(RegClass && "Cannot create register without RegClass!"); 103 assert(RegClass->isAllocatable() && 104 "Virtual register RegClass must be allocatable."); 109 VRegInfo[Reg].first = RegClass;
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H A D | TargetInstrInfo.cpp | 45 short RegClass = MCID.OpInfo[OpNum].RegClass; local 47 return TRI->getPointerRegClass(MF, RegClass); 50 if (RegClass < 0) 54 return TRI->getRegClass(RegClass);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 432 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32); local 435 const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
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/external/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 59 /// RegClass - This specifies the register class enumeration of the operand 63 int16_t RegClass; member in class:llvm::MCOperandInfo
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/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 595 /// \brief Test if RegClass is one of the VSrc classes 596 static bool isVSrc(unsigned RegClass) { argument 597 return AMDGPU::VSrc_32RegClassID == RegClass || 598 AMDGPU::VSrc_64RegClassID == RegClass; 601 /// \brief Test if RegClass is one of the SSrc classes 602 static bool isSSrc(unsigned RegClass) { argument 603 return AMDGPU::SSrc_32RegClassID == RegClass || 604 AMDGPU::SSrc_64RegClassID == RegClass; 696 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass; 728 /// \brief Does "Op" fit into register class "RegClass" 740 ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand, unsigned RegClass, bool &ScalarSlotUsed) const argument 815 unsigned RegClass = Desc->OpInfo[Op].RegClass; local 852 unsigned RegClass = Desc->OpInfo[Op].RegClass; local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 278 unsigned &RegClass, unsigned &Cost, 291 RegClass = RC->getID(); 300 RegClass = RC->getID(); 308 RegClass = RC->getID(); 313 RegClass = TLI->getRepRegClassFor(VT)->getID(); 274 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 179 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass); 900 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { argument 905 return getReg(RegClass, RegNum);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1261 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i]; local 1262 if (!RegClass->Allocatable) 1265 const CodeGenRegister::Set &Regs = RegClass->getMembers(); 1527 // Create a RegUnitSet for each RegClass that contains all units in the class 1532 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any 1537 // Compute a unique RegUnitSet for each RegClass. 1725 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1580 SDValue RegClass = local 1584 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1591 SDValue RegClass = local 1595 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1602 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); local 1605 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1612 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); local 1615 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1623 SDValue RegClass = local 1629 const SDValue Ops[] = { RegClass, V 1638 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); local 1652 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32); local [all...] |