1//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Subclass of MipsDAGToDAGISel specialized for mips32/64. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mips-isel" 15#include "MipsSEISelDAGToDAG.h" 16#include "Mips.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "MipsAnalyzeImmediate.h" 19#include "MipsMachineFunction.h" 20#include "MipsRegisterInfo.h" 21#include "llvm/CodeGen/MachineConstantPool.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/IR/GlobalValue.h" 28#include "llvm/IR/Instructions.h" 29#include "llvm/IR/Intrinsics.h" 30#include "llvm/IR/Type.h" 31#include "llvm/Support/CFG.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetMachine.h" 36using namespace llvm; 37 38bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 39 if (Subtarget.inMips16Mode()) 40 return false; 41 return MipsDAGToDAGISel::runOnMachineFunction(MF); 42} 43 44void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, 45 MachineFunction &MF) { 46 MachineInstrBuilder MIB(MF, &MI); 47 unsigned Mask = MI.getOperand(1).getImm(); 48 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit; 49 50 if (Mask & 1) 51 MIB.addReg(Mips::DSPPos, Flag); 52 53 if (Mask & 2) 54 MIB.addReg(Mips::DSPSCount, Flag); 55 56 if (Mask & 4) 57 MIB.addReg(Mips::DSPCarry, Flag); 58 59 if (Mask & 8) 60 MIB.addReg(Mips::DSPOutFlag, Flag); 61 62 if (Mask & 16) 63 MIB.addReg(Mips::DSPCCond, Flag); 64 65 if (Mask & 32) 66 MIB.addReg(Mips::DSPEFI, Flag); 67} 68 69bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI, 70 const MachineInstr& MI) { 71 unsigned DstReg = 0, ZeroReg = 0; 72 73 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0". 74 if ((MI.getOpcode() == Mips::ADDiu) && 75 (MI.getOperand(1).getReg() == Mips::ZERO) && 76 (MI.getOperand(2).getImm() == 0)) { 77 DstReg = MI.getOperand(0).getReg(); 78 ZeroReg = Mips::ZERO; 79 } else if ((MI.getOpcode() == Mips::DADDiu) && 80 (MI.getOperand(1).getReg() == Mips::ZERO_64) && 81 (MI.getOperand(2).getImm() == 0)) { 82 DstReg = MI.getOperand(0).getReg(); 83 ZeroReg = Mips::ZERO_64; 84 } 85 86 if (!DstReg) 87 return false; 88 89 // Replace uses with ZeroReg. 90 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), 91 E = MRI->use_end(); U != E;) { 92 MachineOperand &MO = U.getOperand(); 93 unsigned OpNo = U.getOperandNo(); 94 MachineInstr *MI = MO.getParent(); 95 ++U; 96 97 // Do not replace if it is a phi's operand or is tied to def operand. 98 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo()) 99 continue; 100 101 MO.setReg(ZeroReg); 102 } 103 104 return true; 105} 106 107void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { 108 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 109 110 if (!MipsFI->globalBaseRegSet()) 111 return; 112 113 MachineBasicBlock &MBB = MF.front(); 114 MachineBasicBlock::iterator I = MBB.begin(); 115 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 116 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 117 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 118 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); 119 const TargetRegisterClass *RC; 120 121 if (Subtarget.isABI_N64()) 122 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass; 123 else 124 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass; 125 126 V0 = RegInfo.createVirtualRegister(RC); 127 V1 = RegInfo.createVirtualRegister(RC); 128 129 if (Subtarget.isABI_N64()) { 130 MF.getRegInfo().addLiveIn(Mips::T9_64); 131 MBB.addLiveIn(Mips::T9_64); 132 133 // lui $v0, %hi(%neg(%gp_rel(fname))) 134 // daddu $v1, $v0, $t9 135 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 136 const GlobalValue *FName = MF.getFunction(); 137 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) 138 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 139 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) 140 .addReg(Mips::T9_64); 141 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1) 142 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 143 return; 144 } 145 146 if (MF.getTarget().getRelocationModel() == Reloc::Static) { 147 // Set global register to __gnu_local_gp. 148 // 149 // lui $v0, %hi(__gnu_local_gp) 150 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp) 151 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 152 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI); 153 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) 154 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO); 155 return; 156 } 157 158 MF.getRegInfo().addLiveIn(Mips::T9); 159 MBB.addLiveIn(Mips::T9); 160 161 if (Subtarget.isABI_N32()) { 162 // lui $v0, %hi(%neg(%gp_rel(fname))) 163 // addu $v1, $v0, $t9 164 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 165 const GlobalValue *FName = MF.getFunction(); 166 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 167 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 168 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); 169 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 170 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 171 return; 172 } 173 174 assert(Subtarget.isABI_O32()); 175 176 // For O32 ABI, the following instruction sequence is emitted to initialize 177 // the global base register: 178 // 179 // 0. lui $2, %hi(_gp_disp) 180 // 1. addiu $2, $2, %lo(_gp_disp) 181 // 2. addu $globalbasereg, $2, $t9 182 // 183 // We emit only the last instruction here. 184 // 185 // GNU linker requires that the first two instructions appear at the beginning 186 // of a function and no instructions be inserted before or between them. 187 // The two instructions are emitted during lowering to MC layer in order to 188 // avoid any reordering. 189 // 190 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure 191 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu) 192 // reads it. 193 MF.getRegInfo().addLiveIn(Mips::V0); 194 MBB.addLiveIn(Mips::V0); 195 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg) 196 .addReg(Mips::V0).addReg(Mips::T9); 197} 198 199void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) { 200 initGlobalBaseReg(MF); 201 202 MachineRegisterInfo *MRI = &MF.getRegInfo(); 203 204 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE; 205 ++MFI) 206 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) { 207 if (I->getOpcode() == Mips::RDDSP) 208 addDSPCtrlRegOperands(false, *I, MF); 209 else if (I->getOpcode() == Mips::WRDSP) 210 addDSPCtrlRegOperands(true, *I, MF); 211 else 212 replaceUsesWithZeroReg(MRI, *I); 213 } 214} 215 216SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag, 217 SDValue CmpLHS, SDLoc DL, 218 SDNode *Node) const { 219 unsigned Opc = InFlag.getOpcode(); (void)Opc; 220 221 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || 222 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && 223 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); 224 225 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; 226 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1); 227 EVT VT = LHS.getValueType(); 228 229 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops); 230 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT, 231 SDValue(Carry, 0), RHS); 232 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, 233 SDValue(AddCarry, 0)); 234} 235 236/// ComplexPattern used on MipsInstrInfo 237/// Used on Mips Load/Store instructions 238bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, 239 SDValue &Offset) const { 240 EVT ValTy = Addr.getValueType(); 241 242 // if Address is FI, get the TargetFrameIndex. 243 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 244 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 245 Offset = CurDAG->getTargetConstant(0, ValTy); 246 return true; 247 } 248 249 // on PIC code Load GA 250 if (Addr.getOpcode() == MipsISD::Wrapper) { 251 Base = Addr.getOperand(0); 252 Offset = Addr.getOperand(1); 253 return true; 254 } 255 256 if (TM.getRelocationModel() != Reloc::PIC_) { 257 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || 258 Addr.getOpcode() == ISD::TargetGlobalAddress)) 259 return false; 260 } 261 262 // Addresses of the form FI+const or FI|const 263 if (CurDAG->isBaseWithConstantOffset(Addr)) { 264 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); 265 if (isInt<16>(CN->getSExtValue())) { 266 267 // If the first operand is a FI, get the TargetFI Node 268 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode> 269 (Addr.getOperand(0))) 270 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 271 else 272 Base = Addr.getOperand(0); 273 274 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); 275 return true; 276 } 277 } 278 279 // Operand is a result from an ADD. 280 if (Addr.getOpcode() == ISD::ADD) { 281 // When loading from constant pools, load the lower address part in 282 // the instruction itself. Example, instead of: 283 // lui $2, %hi($CPI1_0) 284 // addiu $2, $2, %lo($CPI1_0) 285 // lwc1 $f0, 0($2) 286 // Generate: 287 // lui $2, %hi($CPI1_0) 288 // lwc1 $f0, %lo($CPI1_0)($2) 289 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo || 290 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) { 291 SDValue Opnd0 = Addr.getOperand(1).getOperand(0); 292 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) || 293 isa<JumpTableSDNode>(Opnd0)) { 294 Base = Addr.getOperand(0); 295 Offset = Opnd0; 296 return true; 297 } 298 } 299 } 300 301 return false; 302} 303 304bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, 305 SDValue &Offset) const { 306 Base = Addr; 307 Offset = CurDAG->getTargetConstant(0, Addr.getValueType()); 308 return true; 309} 310 311bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, 312 SDValue &Offset) const { 313 return selectAddrRegImm(Addr, Base, Offset) || 314 selectAddrDefault(Addr, Base, Offset); 315} 316 317std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) { 318 unsigned Opcode = Node->getOpcode(); 319 SDLoc DL(Node); 320 321 /// 322 // Instruction Selection not handled by the auto-generated 323 // tablegen selection should be handled here. 324 /// 325 SDNode *Result; 326 327 switch(Opcode) { 328 default: break; 329 330 case ISD::SUBE: { 331 SDValue InFlag = Node->getOperand(2); 332 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node); 333 return std::make_pair(true, Result); 334 } 335 336 case ISD::ADDE: { 337 if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC. 338 break; 339 SDValue InFlag = Node->getOperand(2); 340 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node); 341 return std::make_pair(true, Result); 342 } 343 344 case ISD::ConstantFP: { 345 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node); 346 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { 347 if (Subtarget.hasMips64()) { 348 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 349 Mips::ZERO_64, MVT::i64); 350 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero); 351 } else { 352 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 353 Mips::ZERO, MVT::i32); 354 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero, 355 Zero); 356 } 357 358 return std::make_pair(true, Result); 359 } 360 break; 361 } 362 363 case ISD::Constant: { 364 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node); 365 unsigned Size = CN->getValueSizeInBits(0); 366 367 if (Size == 32) 368 break; 369 370 MipsAnalyzeImmediate AnalyzeImm; 371 int64_t Imm = CN->getSExtValue(); 372 373 const MipsAnalyzeImmediate::InstSeq &Seq = 374 AnalyzeImm.Analyze(Imm, Size, false); 375 376 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 377 SDLoc DL(CN); 378 SDNode *RegOpnd; 379 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 380 MVT::i64); 381 382 // The first instruction can be a LUi which is different from other 383 // instructions (ADDiu, ORI and SLL) in that it does not have a register 384 // operand. 385 if (Inst->Opc == Mips::LUi64) 386 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); 387 else 388 RegOpnd = 389 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 390 CurDAG->getRegister(Mips::ZERO_64, MVT::i64), 391 ImmOpnd); 392 393 // The remaining instructions in the sequence are handled here. 394 for (++Inst; Inst != Seq.end(); ++Inst) { 395 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 396 MVT::i64); 397 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 398 SDValue(RegOpnd, 0), ImmOpnd); 399 } 400 401 return std::make_pair(true, RegOpnd); 402 } 403 404 case MipsISD::ThreadPointer: { 405 EVT PtrVT = getTargetLowering()->getPointerTy(); 406 unsigned RdhwrOpc, SrcReg, DestReg; 407 408 if (PtrVT == MVT::i32) { 409 RdhwrOpc = Mips::RDHWR; 410 SrcReg = Mips::HWR29; 411 DestReg = Mips::V1; 412 } else { 413 RdhwrOpc = Mips::RDHWR64; 414 SrcReg = Mips::HWR29_64; 415 DestReg = Mips::V1_64; 416 } 417 418 SDNode *Rdhwr = 419 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node), 420 Node->getValueType(0), 421 CurDAG->getRegister(SrcReg, PtrVT)); 422 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg, 423 SDValue(Rdhwr, 0)); 424 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT); 425 ReplaceUses(SDValue(Node, 0), ResNode); 426 return std::make_pair(true, ResNode.getNode()); 427 } 428 429 case MipsISD::InsertLOHI: { 430 unsigned RCID = Subtarget.hasDSP() ? Mips::ACRegsDSPRegClassID : 431 Mips::ACRegsRegClassID; 432 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32); 433 SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32); 434 SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32); 435 const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx, 436 Node->getOperand(1), HiIdx }; 437 SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, 438 MVT::Untyped, Ops); 439 return std::make_pair(true, Res); 440 } 441 } 442 443 return std::make_pair(false, (SDNode*)NULL); 444} 445 446FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) { 447 return new MipsSEDAGToDAGISel(TM); 448} 449