| /external/llvm/lib/Target/R600/ |
| H A D | SIRegisterInfo.h | 32 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
38 virtual const TargetRegisterClass *
39 getISARegClass(const TargetRegisterClass *RC) const;
43 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
47 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
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| H A D | R600RegisterInfo.h | 36 virtual const TargetRegisterClass *getISARegClass(
37 const TargetRegisterClass *RC) const;
44 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
50 virtual const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const;
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| H A D | SIRegisterInfo.cpp | 31 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
36 const TargetRegisterClass *
37 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
45 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
53 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
56 const TargetRegisterClass *BaseClasses[] = {
66 sizeof(const TargetRegisterClass*); i != e; ++i) {
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| H A D | AMDGPURegisterInfo.h | 44 virtual const TargetRegisterClass * getISARegClass(
45 const TargetRegisterClass * RC) const {
49 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
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| H A D | SIInstrInfo.h | 49 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
58 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
61 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
75 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
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| H A D | R600RegisterInfo.cpp | 45 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
50 for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(),
67 const TargetRegisterClass *
68 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
81 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
100 const TargetRegisterClass *RC) const {
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| /external/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 74 virtual const TargetRegisterClass *
75 getMatchingSuperRegClass(const TargetRegisterClass *A,
76 const TargetRegisterClass *B, unsigned Idx) const;
78 virtual const TargetRegisterClass *
79 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
81 const TargetRegisterClass*
82 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
84 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
86 const TargetRegisterClass *
92 const TargetRegisterClass *
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | SIRegisterInfo.h | 39 virtual const TargetRegisterClass *
40 getISARegClass(const TargetRegisterClass * rc) const;
48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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| H A D | R600RegisterInfo.h | 36 virtual const TargetRegisterClass * getISARegClass(
37 const TargetRegisterClass * rc) const;
47 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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| H A D | SIRegisterInfo.cpp | 42 const TargetRegisterClass *
43 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
52 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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| H A D | AMDGPURegisterInfo.h | 44 virtual const TargetRegisterClass * getISARegClass(
45 const TargetRegisterClass * rc) const {
49 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | SIRegisterInfo.h | 39 virtual const TargetRegisterClass *
40 getISARegClass(const TargetRegisterClass * rc) const;
48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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| H A D | R600RegisterInfo.h | 36 virtual const TargetRegisterClass * getISARegClass(
37 const TargetRegisterClass * rc) const;
47 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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| H A D | SIRegisterInfo.cpp | 42 const TargetRegisterClass *
43 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
52 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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| H A D | AMDGPURegisterInfo.h | 44 virtual const TargetRegisterClass * getISARegClass(
45 const TargetRegisterClass * rc) const {
49 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 68 void compute(const TargetRegisterClass *RC) const;
71 const RCInfo &get(const TargetRegisterClass *RC) const {
87 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
94 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
104 bool isProperSubClass(const TargetRegisterClass *RC) const {
120 unsigned getMinCost(const TargetRegisterClass *RC) {
128 unsigned getLastCostChange(const TargetRegisterClass *RC) {
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| H A D | FastISel.h | 40 class TargetRegisterClass;
257 const TargetRegisterClass *RC);
262 const TargetRegisterClass *RC,
268 const TargetRegisterClass *RC,
275 const TargetRegisterClass *RC,
283 const TargetRegisterClass *RC,
289 const TargetRegisterClass *RC,
296 const TargetRegisterClass *RC,
303 const TargetRegisterClass *RC,
311 const TargetRegisterClass *R
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 36 const TargetRegisterClass *RC;
38 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
41 (const TargetRegisterClass*)&Mips::GPR64RegClass :
42 (const TargetRegisterClass*)&Mips::GPR32RegClass;
54 const TargetRegisterClass *RC;
55 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
62 const TargetRegisterClass *RC = ST.isABI_N64() ?
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| H A D | Mips16RegisterInfo.h | 35 const TargetRegisterClass *RC,
38 virtual const TargetRegisterClass *intRegClass(unsigned Size) const;
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 45 const TargetRegisterClass *
46 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
50 const TargetRegisterClass*
51 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
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| /external/llvm/lib/Target/ARM/ |
| H A D | Thumb1RegisterInfo.h | 30 const TargetRegisterClass*
31 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
33 const TargetRegisterClass*
57 const TargetRegisterClass *RC,
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| /external/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 78 const TargetRegisterClass *
79 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
89 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
102 const TargetRegisterClass *
108 const TargetRegisterClass* BestRC = 0;
110 const TargetRegisterClass* RC = *I;
123 const TargetRegisterClass *RC, BitVector &R){
131 const TargetRegisterClass *RC) const {
135 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
153 const TargetRegisterClass *firstCommonClas
[all...] |
| H A D | RegisterCoalescer.h | 22 class TargetRegisterClass;
59 const TargetRegisterClass *NewRC;
116 const TargetRegisterClass *getNewRC() const { return NewRC; }
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| /external/llvm/include/llvm/Target/ |
| H A D | TargetRegisterInfo.h | 36 class TargetRegisterClass { class in namespace:llvm
41 typedef const TargetRegisterClass* const * sc_iterator;
102 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
123 /// hasSubClass - return true if the specified TargetRegisterClass
124 /// is a proper sub-class of this TargetRegisterClass.
125 bool hasSubClass(const TargetRegisterClass *RC) const {
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
136 /// hasSuperClass - return true if the specified TargetRegisterClass is a
137 /// proper super-class of this TargetRegisterClass.
138 bool hasSuperClass(const TargetRegisterClass *R
[all...] |
| H A D | TargetSubtargetInfo.h | 26 class TargetRegisterClass;
45 typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector;
|