Searched refs:r600_write_context_reg (Results 1 - 10 of 10) sorted by relevance

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/
H A Dr600_state.c1770 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1780 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1872 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1874 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
2027 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
H A Dr600_state_common.c101 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
104 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
1266 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
H A Devergreen_state.c1947 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2029 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2031 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2156 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
H A Dr600_pipe.h842 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) function
H A Dr600_hw_context.c955 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_state.c1770 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1780 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1872 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1874 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
2027 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
H A Dr600_state_common.c101 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
104 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
1266 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
H A Devergreen_state.c1947 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2029 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2031 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2156 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
H A Dr600_pipe.h842 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) function
H A Dr600_hw_context.c955 r600_write_context_reg(cs, R_028350_SX_MISC, 0);

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