1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef R600INSTRUCTIONINFO_H_
16#define R600INSTRUCTIONINFO_H_
17
18#include "AMDGPUInstrInfo.h"
19#include "R600Defines.h"
20#include "R600RegisterInfo.h"
21#include <map>
22
23namespace llvm {
24
25  class AMDGPUTargetMachine;
26  class DFAPacketizer;
27  class ScheduleDAG;
28  class MachineFunction;
29  class MachineInstr;
30  class MachineInstrBuilder;
31
32  class R600InstrInfo : public AMDGPUInstrInfo {
33  private:
34  const R600RegisterInfo RI;
35  const AMDGPUSubtarget &ST;
36
37  int getBranchInstr(const MachineOperand &op) const;
38  std::vector<std::pair<int, unsigned> >
39  ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
40
41  public:
42  enum BankSwizzle {
43    ALU_VEC_012_SCL_210 = 0,
44    ALU_VEC_021_SCL_122,
45    ALU_VEC_120_SCL_212,
46    ALU_VEC_102_SCL_221,
47    ALU_VEC_201,
48    ALU_VEC_210
49  };
50
51  explicit R600InstrInfo(AMDGPUTargetMachine &tm);
52
53  const R600RegisterInfo &getRegisterInfo() const;
54  virtual void copyPhysReg(MachineBasicBlock &MBB,
55                           MachineBasicBlock::iterator MI, DebugLoc DL,
56                           unsigned DestReg, unsigned SrcReg,
57                           bool KillSrc) const;
58
59  bool isTrig(const MachineInstr &MI) const;
60  bool isPlaceHolderOpcode(unsigned opcode) const;
61  bool isReductionOp(unsigned opcode) const;
62  bool isCubeOp(unsigned opcode) const;
63
64  /// \returns true if this \p Opcode represents an ALU instruction.
65  bool isALUInstr(unsigned Opcode) const;
66  bool hasInstrModifiers(unsigned Opcode) const;
67  bool isLDSInstr(unsigned Opcode) const;
68
69  bool isTransOnly(unsigned Opcode) const;
70  bool isTransOnly(const MachineInstr *MI) const;
71
72  bool usesVertexCache(unsigned Opcode) const;
73  bool usesVertexCache(const MachineInstr *MI) const;
74  bool usesTextureCache(unsigned Opcode) const;
75  bool usesTextureCache(const MachineInstr *MI) const;
76
77  bool mustBeLastInClause(unsigned Opcode) const;
78
79  /// \returns The operand index for the given source number.  Legal values
80  /// for SrcNum are 0, 1, and 2.
81  int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
82  /// \returns The operand Index for the Sel operand given an index to one
83  /// of the instruction's src operands.
84  int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
85
86  /// \returns a pair for each src of an ALU instructions.
87  /// The first member of a pair is the register id.
88  /// If register is ALU_CONST, second member is SEL.
89  /// If register is ALU_LITERAL, second member is IMM.
90  /// Otherwise, second member value is undefined.
91  SmallVector<std::pair<MachineOperand *, int64_t>, 3>
92      getSrcs(MachineInstr *MI) const;
93
94  unsigned  isLegalUpTo(
95    const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
96    const std::vector<R600InstrInfo::BankSwizzle> &Swz,
97    const std::vector<std::pair<int, unsigned> > &TransSrcs,
98    R600InstrInfo::BankSwizzle TransSwz) const;
99
100  bool FindSwizzleForVectorSlot(
101    const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
102    std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
103    const std::vector<std::pair<int, unsigned> > &TransSrcs,
104    R600InstrInfo::BankSwizzle TransSwz) const;
105
106  /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
107  /// returns true and the first (in lexical order) BankSwizzle affectation
108  /// starting from the one already provided in the Instruction Group MIs that
109  /// fits Read Port limitations in BS if available. Otherwise returns false
110  /// and undefined content in BS.
111  /// isLastAluTrans should be set if the last Alu of MIs will be executed on
112  /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
113  /// apply to the last instruction.
114  /// PV holds GPR to PV registers in the Instruction Group MIs.
115  bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
116                               const DenseMap<unsigned, unsigned> &PV,
117                               std::vector<BankSwizzle> &BS,
118                               bool isLastAluTrans) const;
119
120  /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
121  /// from KCache bank on R700+. This function check if MI set in input meet
122  /// this limitations
123  bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
124  /// Same but using const index set instead of MI set.
125  bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
126
127  /// \breif Vector instructions are instructions that must fill all
128  /// instruction slots within an instruction group.
129  bool isVector(const MachineInstr &MI) const;
130
131  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
132                                        int64_t Imm) const;
133
134  virtual unsigned getIEQOpcode() const;
135  virtual bool isMov(unsigned Opcode) const;
136
137  DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
138                                           const ScheduleDAG *DAG) const;
139
140  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
141
142  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
143                     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
144
145  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
146
147  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
148
149  bool isPredicated(const MachineInstr *MI) const;
150
151  bool isPredicable(MachineInstr *MI) const;
152
153  bool
154   isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
155                             const BranchProbability &Probability) const;
156
157  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
158                           unsigned ExtraPredCycles,
159                           const BranchProbability &Probability) const ;
160
161  bool
162   isProfitableToIfCvt(MachineBasicBlock &TMBB,
163                       unsigned NumTCycles, unsigned ExtraTCycles,
164                       MachineBasicBlock &FMBB,
165                       unsigned NumFCycles, unsigned ExtraFCycles,
166                       const BranchProbability &Probability) const;
167
168  bool DefinesPredicate(MachineInstr *MI,
169                                  std::vector<MachineOperand> &Pred) const;
170
171  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
172                         const SmallVectorImpl<MachineOperand> &Pred2) const;
173
174  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
175                                          MachineBasicBlock &FMBB) const;
176
177  bool PredicateInstruction(MachineInstr *MI,
178                        const SmallVectorImpl<MachineOperand> &Pred) const;
179
180  unsigned int getInstrLatency(const InstrItineraryData *ItinData,
181                               const MachineInstr *MI,
182                               unsigned *PredCost = 0) const;
183
184  virtual int getInstrLatency(const InstrItineraryData *ItinData,
185                              SDNode *Node) const { return 1;}
186
187  /// \returns a list of all the registers that may be accesed using indirect
188  /// addressing.
189  std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
190
191  virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
192
193  virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
194
195
196  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
197                                            unsigned Channel) const;
198
199  virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
200                                                      unsigned SourceReg) const;
201
202  virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
203
204  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
205                                  MachineBasicBlock::iterator I,
206                                  unsigned ValueReg, unsigned Address,
207                                  unsigned OffsetReg) const;
208
209  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
210                                  MachineBasicBlock::iterator I,
211                                  unsigned ValueReg, unsigned Address,
212                                  unsigned OffsetReg) const;
213
214  virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
215
216  unsigned getMaxAlusPerClause() const;
217
218  ///buildDefaultInstruction - This function returns a MachineInstr with
219  /// all the instruction modifiers initialized to their default values.
220  /// You can use this function to avoid manually specifying each instruction
221  /// modifier operand when building a new instruction.
222  ///
223  /// \returns a MachineInstr with all the instruction modifiers initialized
224  /// to their default values.
225  MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
226                                              MachineBasicBlock::iterator I,
227                                              unsigned Opcode,
228                                              unsigned DstReg,
229                                              unsigned Src0Reg,
230                                              unsigned Src1Reg = 0) const;
231
232  MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
233                                             MachineInstr *MI,
234                                             unsigned Slot,
235                                             unsigned DstReg) const;
236
237  MachineInstr *buildMovImm(MachineBasicBlock &BB,
238                                  MachineBasicBlock::iterator I,
239                                  unsigned DstReg,
240                                  uint64_t Imm) const;
241
242  /// \brief Get the index of Op in the MachineInstr.
243  ///
244  /// \returns -1 if the Instruction does not contain the specified \p Op.
245  int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
246
247  /// \brief Get the index of \p Op for the given Opcode.
248  ///
249  /// \returns -1 if the Instruction does not contain the specified \p Op.
250  int getOperandIdx(unsigned Opcode, unsigned Op) const;
251
252  /// \brief Helper function for setting instruction flag values.
253  void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
254
255  /// \returns true if this instruction has an operand for storing target flags.
256  bool hasFlagOperand(const MachineInstr &MI) const;
257
258  ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
259  void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
260
261  ///\brief Determine if the specified \p Flag is set on this \p Operand.
262  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
263
264  /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
265  /// \param Flag The flag being set.
266  ///
267  /// \returns the operand containing the flags for this instruction.
268  MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
269                            unsigned Flag = 0) const;
270
271  /// \brief Clear the specified flag on the instruction.
272  void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
273};
274
275} // End llvm namespace
276
277#endif // R600INSTRINFO_H_
278