1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides pattern fragments useful for SIMD instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// MMX Pattern Fragments 16//===----------------------------------------------------------------------===// 17 18def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 19def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>; 20 21//===----------------------------------------------------------------------===// 22// SSE specific DAG Nodes. 23//===----------------------------------------------------------------------===// 24 25def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, 26 SDTCisFP<0>, SDTCisInt<2> ]>; 27def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 28 SDTCisFP<1>, SDTCisVT<3, i8>]>; 29 30def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>; 31def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>; 32def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>; 33def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>; 34 35def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 36def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 37 38// Commutative and Associative FMIN and FMAX. 39def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, 40 [SDNPCommutative, SDNPAssociative]>; 41def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, 42 [SDNPCommutative, SDNPAssociative]>; 43 44def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 49 [SDNPCommutative, SDNPAssociative]>; 50def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp, 51 [SDNPCommutative, SDNPAssociative]>; 52def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 53def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 54def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; 55def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; 56def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 57def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 58def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; 59def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; 60def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; 61def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; 62def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>; 63def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; 64def X86pshufb : SDNode<"X86ISD::PSHUFB", 65 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 66 SDTCisSameAs<0,2>]>>; 67def X86andnp : SDNode<"X86ISD::ANDNP", 68 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 69 SDTCisSameAs<0,2>]>>; 70def X86psign : SDNode<"X86ISD::PSIGN", 71 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 72 SDTCisSameAs<0,2>]>>; 73def X86pextrb : SDNode<"X86ISD::PEXTRB", 74 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 75def X86pextrw : SDNode<"X86ISD::PEXTRW", 76 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 77def X86pinsrb : SDNode<"X86ISD::PINSRB", 78 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 79 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 80def X86pinsrw : SDNode<"X86ISD::PINSRW", 81 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 82 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 83def X86insrtps : SDNode<"X86ISD::INSERTPS", 84 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 85 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>; 86def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 87 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 88 89def X86vzmovly : SDNode<"X86ISD::VZEXT_MOVL", 90 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 91 SDTCisOpSmallerThanOp<1, 0> ]>>; 92 93def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL", 94 SDTypeProfile<1, 1, 95 [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>; 96 97def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 98 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 99 100def X86vzext : SDNode<"X86ISD::VZEXT", 101 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 102 SDTCisInt<0>, SDTCisInt<1>]>>; 103 104def X86vsext : SDNode<"X86ISD::VSEXT", 105 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 106 SDTCisInt<0>, SDTCisInt<1>]>>; 107 108def X86vfpext : SDNode<"X86ISD::VFPEXT", 109 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 110 SDTCisFP<0>, SDTCisFP<1>]>>; 111def X86vfpround: SDNode<"X86ISD::VFPROUND", 112 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 113 SDTCisFP<0>, SDTCisFP<1>]>>; 114 115def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>; 116def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>; 117def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; 118def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; 119def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; 120 121def X86vshl : SDNode<"X86ISD::VSHL", 122 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 123 SDTCisVec<2>]>>; 124def X86vsrl : SDNode<"X86ISD::VSRL", 125 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 126 SDTCisVec<2>]>>; 127def X86vsra : SDNode<"X86ISD::VSRA", 128 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 129 SDTCisVec<2>]>>; 130 131def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>; 132def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>; 133def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>; 134 135def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 136 SDTCisVec<1>, 137 SDTCisSameAs<2, 1>]>; 138def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>; 139def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 140def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 141def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; 142def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>; 143 144def X86pmuludq : SDNode<"X86ISD::PMULUDQ", 145 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 146 SDTCisSameAs<1,2>]>>; 147 148// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 149// translated into one of the target nodes below during lowering. 150// Note: this is a work in progress... 151def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 152def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 153 SDTCisSameAs<0,2>]>; 154 155def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 156 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 157def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 158 SDTCisSameAs<0,2>, SDTCisInt<3>]>; 159 160def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 161def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>; 162 163def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 164 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>; 165 166def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>, 167 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 168 169def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>; 170 171def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 172def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 173def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 174 175def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; 176 177def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 178def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 179def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 180 181def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>; 182def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>; 183 184def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>; 185def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>; 186def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>; 187 188def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>; 189def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>; 190 191def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; 192def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; 193 194def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>; 195def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>; 196def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; 197 198def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; 199 200def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 201def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; 202 203def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; 204def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>; 205def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>; 206def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>; 207def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>; 208def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>; 209def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>; 210 211def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 212 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>, 213 SDTCisVT<4, i8>]>; 214def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 215 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>, 216 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>, 217 SDTCisVT<6, i8>]>; 218 219def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>; 220def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>; 221 222//===----------------------------------------------------------------------===// 223// SSE Complex Patterns 224//===----------------------------------------------------------------------===// 225 226// These are 'extloads' from a scalar to the low element of a vector, zeroing 227// the top elements. These are used for the SSE 'ss' and 'sd' instruction 228// forms. 229def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [], 230 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 231 SDNPWantRoot]>; 232def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [], 233 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 234 SDNPWantRoot]>; 235 236def ssmem : Operand<v4f32> { 237 let PrintMethod = "printf32mem"; 238 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 239 let ParserMatchClass = X86MemAsmOperand; 240 let OperandType = "OPERAND_MEMORY"; 241} 242def sdmem : Operand<v2f64> { 243 let PrintMethod = "printf64mem"; 244 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 245 let ParserMatchClass = X86MemAsmOperand; 246 let OperandType = "OPERAND_MEMORY"; 247} 248 249//===----------------------------------------------------------------------===// 250// SSE pattern fragments 251//===----------------------------------------------------------------------===// 252 253// 128-bit load pattern fragments 254// NOTE: all 128-bit integer vector loads are promoted to v2i64 255def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 256def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 257def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 258 259// 256-bit load pattern fragments 260// NOTE: all 256-bit integer vector loads are promoted to v4i64 261def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 262def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 263def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 264 265// 128-/256-bit extload pattern fragments 266def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>; 267def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>; 268 269// Like 'store', but always requires 128-bit vector alignment. 270def alignedstore : PatFrag<(ops node:$val, node:$ptr), 271 (store node:$val, node:$ptr), [{ 272 return cast<StoreSDNode>(N)->getAlignment() >= 16; 273}]>; 274 275// Like 'store', but always requires 256-bit vector alignment. 276def alignedstore256 : PatFrag<(ops node:$val, node:$ptr), 277 (store node:$val, node:$ptr), [{ 278 return cast<StoreSDNode>(N)->getAlignment() >= 32; 279}]>; 280 281// Like 'load', but always requires 128-bit vector alignment. 282def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 283 return cast<LoadSDNode>(N)->getAlignment() >= 16; 284}]>; 285 286// Like 'X86vzload', but always requires 128-bit vector alignment. 287def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{ 288 return cast<MemSDNode>(N)->getAlignment() >= 16; 289}]>; 290 291// Like 'load', but always requires 256-bit vector alignment. 292def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 293 return cast<LoadSDNode>(N)->getAlignment() >= 32; 294}]>; 295 296def alignedloadfsf32 : PatFrag<(ops node:$ptr), 297 (f32 (alignedload node:$ptr))>; 298def alignedloadfsf64 : PatFrag<(ops node:$ptr), 299 (f64 (alignedload node:$ptr))>; 300 301// 128-bit aligned load pattern fragments 302// NOTE: all 128-bit integer vector loads are promoted to v2i64 303def alignedloadv4f32 : PatFrag<(ops node:$ptr), 304 (v4f32 (alignedload node:$ptr))>; 305def alignedloadv2f64 : PatFrag<(ops node:$ptr), 306 (v2f64 (alignedload node:$ptr))>; 307def alignedloadv2i64 : PatFrag<(ops node:$ptr), 308 (v2i64 (alignedload node:$ptr))>; 309 310// 256-bit aligned load pattern fragments 311// NOTE: all 256-bit integer vector loads are promoted to v4i64 312def alignedloadv8f32 : PatFrag<(ops node:$ptr), 313 (v8f32 (alignedload256 node:$ptr))>; 314def alignedloadv4f64 : PatFrag<(ops node:$ptr), 315 (v4f64 (alignedload256 node:$ptr))>; 316def alignedloadv4i64 : PatFrag<(ops node:$ptr), 317 (v4i64 (alignedload256 node:$ptr))>; 318 319// Like 'load', but uses special alignment checks suitable for use in 320// memory operands in most SSE instructions, which are required to 321// be naturally aligned on some targets but not on others. If the subtarget 322// allows unaligned accesses, match any load, though this may require 323// setting a feature bit in the processor (on startup, for example). 324// Opteron 10h and later implement such a feature. 325def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 326 return Subtarget->hasVectorUAMem() 327 || cast<LoadSDNode>(N)->getAlignment() >= 16; 328}]>; 329 330def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>; 331def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>; 332 333// 128-bit memop pattern fragments 334// NOTE: all 128-bit integer vector loads are promoted to v2i64 335def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 336def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 337def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 338 339// 256-bit memop pattern fragments 340// NOTE: all 256-bit integer vector loads are promoted to v4i64 341def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>; 342def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>; 343def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>; 344 345// SSSE3 uses MMX registers for some instructions. They aren't aligned on a 346// 16-byte boundary. 347// FIXME: 8 byte alignment for mmx reads is not required 348def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 349 return cast<LoadSDNode>(N)->getAlignment() >= 8; 350}]>; 351 352def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>; 353 354// MOVNT Support 355// Like 'store', but requires the non-temporal bit to be set 356def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 357 (st node:$val, node:$ptr), [{ 358 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 359 return ST->isNonTemporal(); 360 return false; 361}]>; 362 363def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 364 (st node:$val, node:$ptr), [{ 365 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 366 return ST->isNonTemporal() && !ST->isTruncatingStore() && 367 ST->getAddressingMode() == ISD::UNINDEXED && 368 ST->getAlignment() >= 16; 369 return false; 370}]>; 371 372def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 373 (st node:$val, node:$ptr), [{ 374 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 375 return ST->isNonTemporal() && 376 ST->getAlignment() < 16; 377 return false; 378}]>; 379 380// 128-bit bitconvert pattern fragments 381def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 382def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 383def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 384def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 385def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 386def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 387 388// 256-bit bitconvert pattern fragments 389def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; 390def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; 391def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 392def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 393 394def vzmovl_v2i64 : PatFrag<(ops node:$src), 395 (bitconvert (v2i64 (X86vzmovl 396 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; 397def vzmovl_v4i32 : PatFrag<(ops node:$src), 398 (bitconvert (v4i32 (X86vzmovl 399 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; 400 401def vzload_v2i64 : PatFrag<(ops node:$src), 402 (bitconvert (v2i64 (X86vzload node:$src)))>; 403 404 405def fp32imm0 : PatLeaf<(f32 fpimm), [{ 406 return N->isExactlyValue(+0.0); 407}]>; 408 409// BYTE_imm - Transform bit immediates into byte immediates. 410def BYTE_imm : SDNodeXForm<imm, [{ 411 // Transformation function: imm >> 3 412 return getI32Imm(N->getZExtValue() >> 3); 413}]>; 414 415// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index 416// to VEXTRACTF128/VEXTRACTI128 imm. 417def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{ 418 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N)); 419}]>; 420 421// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to 422// VINSERTF128/VINSERTI128 imm. 423def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{ 424 return getI8Imm(X86::getInsertVINSERT128Immediate(N)); 425}]>; 426 427// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index 428// to VEXTRACTF64x4 imm. 429def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{ 430 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N)); 431}]>; 432 433// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to 434// VINSERTF64x4 imm. 435def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ 436 return getI8Imm(X86::getInsertVINSERT256Immediate(N)); 437}]>; 438 439def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), 440 (extract_subvector node:$bigvec, 441 node:$index), [{ 442 return X86::isVEXTRACT128Index(N); 443}], EXTRACT_get_vextract128_imm>; 444 445def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 446 node:$index), 447 (insert_subvector node:$bigvec, node:$smallvec, 448 node:$index), [{ 449 return X86::isVINSERT128Index(N); 450}], INSERT_get_vinsert128_imm>; 451 452 453def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), 454 (extract_subvector node:$bigvec, 455 node:$index), [{ 456 return X86::isVEXTRACT256Index(N); 457}], EXTRACT_get_vextract256_imm>; 458 459def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 460 node:$index), 461 (insert_subvector node:$bigvec, node:$smallvec, 462 node:$index), [{ 463 return X86::isVINSERT256Index(N); 464}], INSERT_get_vinsert256_imm>; 465 466