r600_pipe.h revision 428855eea3e99d94474df6df0cb8dfc4a8819702
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_shader.h" 32#include "r600_resource.h" 33 34#define R600_MAX_CONST_BUFFERS 2 35#define R600_MAX_CONST_BUFFER_SIZE 4096 36 37#ifdef PIPE_ARCH_BIG_ENDIAN 38#define R600_BIG_ENDIAN 1 39#else 40#define R600_BIG_ENDIAN 0 41#endif 42 43enum r600_atom_flags { 44 /* When set, atoms are added at the beginning of the dirty list 45 * instead of the end. */ 46 EMIT_EARLY = (1 << 0) 47}; 48 49/* This encapsulates a state or an operation which can emitted into the GPU 50 * command stream. It's not limited to states only, it can be used for anything 51 * that wants to write commands into the CS (e.g. cache flushes). */ 52struct r600_atom { 53 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 54 55 unsigned num_dw; 56 enum r600_atom_flags flags; 57 bool dirty; 58 59 struct list_head head; 60}; 61 62/* This is an atom containing GPU commands that never change. 63 * This is supposed to be copied directly into the CS. */ 64struct r600_command_buffer { 65 struct r600_atom atom; 66 uint32_t *buf; 67 unsigned max_num_dw; 68}; 69 70struct r600_surface_sync_cmd { 71 struct r600_atom atom; 72 unsigned flush_flags; /* CP_COHER_CNTL */ 73}; 74 75struct r600_db_misc_state { 76 struct r600_atom atom; 77 bool occlusion_query_enabled; 78 bool flush_depthstencil_enabled; 79}; 80 81enum r600_pipe_state_id { 82 R600_PIPE_STATE_BLEND = 0, 83 R600_PIPE_STATE_BLEND_COLOR, 84 R600_PIPE_STATE_CONFIG, 85 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 86 R600_PIPE_STATE_CLIP, 87 R600_PIPE_STATE_SCISSOR, 88 R600_PIPE_STATE_VIEWPORT, 89 R600_PIPE_STATE_RASTERIZER, 90 R600_PIPE_STATE_VGT, 91 R600_PIPE_STATE_FRAMEBUFFER, 92 R600_PIPE_STATE_DSA, 93 R600_PIPE_STATE_STENCIL_REF, 94 R600_PIPE_STATE_PS_SHADER, 95 R600_PIPE_STATE_VS_SHADER, 96 R600_PIPE_STATE_CONSTANT, 97 R600_PIPE_STATE_SAMPLER, 98 R600_PIPE_STATE_RESOURCE, 99 R600_PIPE_STATE_POLYGON_OFFSET, 100 R600_PIPE_STATE_FETCH_SHADER, 101 R600_PIPE_NSTATES 102}; 103 104struct r600_pipe_fences { 105 struct r600_resource *bo; 106 unsigned *data; 107 unsigned next_index; 108 /* linked list of preallocated blocks */ 109 struct list_head blocks; 110 /* linked list of freed fences */ 111 struct list_head pool; 112 pipe_mutex mutex; 113}; 114 115struct r600_screen { 116 struct pipe_screen screen; 117 struct radeon_winsys *ws; 118 unsigned family; 119 enum chip_class chip_class; 120 struct radeon_info info; 121 struct r600_tiling_info tiling_info; 122 struct util_slab_mempool pool_buffers; 123 struct r600_pipe_fences fences; 124 125 unsigned num_contexts; 126 bool use_surface_alloc; 127 int glsl_feature_level; 128 129 /* for thread-safe write accessing to num_contexts */ 130 pipe_mutex mutex_num_contexts; 131}; 132 133struct r600_pipe_sampler_view { 134 struct pipe_sampler_view base; 135 struct r600_pipe_resource_state state; 136}; 137 138struct r600_pipe_rasterizer { 139 struct r600_pipe_state rstate; 140 boolean flatshade; 141 boolean two_side; 142 unsigned sprite_coord_enable; 143 unsigned clip_plane_enable; 144 unsigned pa_sc_line_stipple; 145 unsigned pa_cl_clip_cntl; 146 float offset_units; 147 float offset_scale; 148 bool scissor_enable; 149}; 150 151struct r600_pipe_blend { 152 struct r600_pipe_state rstate; 153 unsigned cb_target_mask; 154 unsigned cb_color_control; 155 bool dual_src_blend; 156}; 157 158struct r600_pipe_dsa { 159 struct r600_pipe_state rstate; 160 unsigned alpha_ref; 161 ubyte valuemask[2]; 162 ubyte writemask[2]; 163 bool is_flush; 164}; 165 166struct r600_vertex_element 167{ 168 unsigned count; 169 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 170 struct r600_resource *fetch_shader; 171 unsigned fs_size; 172 struct r600_pipe_state rstate; 173}; 174 175struct r600_pipe_shader { 176 struct r600_shader shader; 177 struct r600_pipe_state rstate; 178 struct r600_resource *bo; 179 struct r600_resource *bo_fetch; 180 struct r600_vertex_element vertex_elements; 181 struct tgsi_token *tokens; 182 unsigned sprite_coord_enable; 183 unsigned flatshade; 184 unsigned pa_cl_vs_out_cntl; 185 unsigned ps_cb_shader_mask; 186 struct pipe_stream_output_info so; 187}; 188 189struct r600_pipe_sampler_state { 190 struct r600_pipe_state rstate; 191 boolean seamless_cube_map; 192}; 193 194/* needed for blitter save */ 195#define NUM_TEX_UNITS 16 196 197struct r600_textures_info { 198 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 199 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 200 unsigned n_views; 201 unsigned n_samplers; 202 bool samplers_dirty; 203 bool is_array_sampler[NUM_TEX_UNITS]; 204}; 205 206struct r600_fence { 207 struct pipe_reference reference; 208 unsigned index; /* in the shared bo */ 209 struct r600_resource *sleep_bo; 210 struct list_head head; 211}; 212 213#define FENCE_BLOCK_SIZE 16 214 215struct r600_fence_block { 216 struct r600_fence fences[FENCE_BLOCK_SIZE]; 217 struct list_head head; 218}; 219 220#define R600_CONSTANT_ARRAY_SIZE 256 221#define R600_RESOURCE_ARRAY_SIZE 160 222 223struct r600_stencil_ref 224{ 225 ubyte ref_value[2]; 226 ubyte valuemask[2]; 227 ubyte writemask[2]; 228}; 229 230struct r600_constant_buffer 231{ 232 struct pipe_resource *buffer; 233 unsigned buffer_offset; 234 unsigned buffer_size; 235}; 236 237struct r600_constbuf_state 238{ 239 struct r600_atom atom; 240 struct r600_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 241 uint32_t enabled_mask; 242 uint32_t dirty_mask; 243}; 244 245struct r600_context { 246 struct pipe_context context; 247 struct blitter_context *blitter; 248 enum radeon_family family; 249 enum chip_class chip_class; 250 boolean has_vertex_cache; 251 unsigned r6xx_num_clause_temp_gprs; 252 void *custom_dsa_flush; 253 struct r600_screen *screen; 254 struct radeon_winsys *ws; 255 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 256 struct r600_vertex_element *vertex_elements; 257 struct pipe_framebuffer_state framebuffer; 258 unsigned cb_target_mask; 259 unsigned fb_cb_shader_mask; 260 unsigned cb_shader_mask; 261 unsigned cb_color_control; 262 unsigned pa_sc_line_stipple; 263 unsigned pa_cl_clip_cntl; 264 /* for saving when using blitter */ 265 struct pipe_stencil_ref stencil_ref; 266 struct pipe_viewport_state viewport; 267 struct pipe_clip_state clip; 268 struct r600_pipe_shader *ps_shader; 269 struct r600_pipe_shader *vs_shader; 270 struct r600_pipe_rasterizer *rasterizer; 271 struct r600_pipe_state vgt; 272 struct r600_pipe_state spi; 273 struct pipe_query *current_render_cond; 274 unsigned current_render_cond_mode; 275 struct pipe_query *saved_render_cond; 276 unsigned saved_render_cond_mode; 277 /* shader information */ 278 boolean two_side; 279 unsigned sprite_coord_enable; 280 boolean export_16bpc; 281 unsigned alpha_ref; 282 boolean alpha_ref_dirty; 283 unsigned nr_cbufs; 284 struct r600_textures_info vs_samplers; 285 struct r600_textures_info ps_samplers; 286 287 struct u_vbuf *vbuf_mgr; 288 struct u_upload_mgr *uploader; 289 struct util_slab_mempool pool_transfers; 290 boolean have_depth_texture, have_depth_fb; 291 292 unsigned default_ps_gprs, default_vs_gprs; 293 294 /* States based on r600_atom. */ 295 struct list_head dirty_states; 296 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 297 struct r600_surface_sync_cmd surface_sync_cmd; 298 struct r600_atom r6xx_flush_and_inv_cmd; 299 struct r600_db_misc_state db_misc_state; 300 struct r600_atom vertex_buffer_state; 301 struct r600_constbuf_state vs_constbuf_state; 302 struct r600_constbuf_state ps_constbuf_state; 303 304 struct radeon_winsys_cs *cs; 305 306 struct r600_range *range; 307 unsigned nblocks; 308 struct r600_block **blocks; 309 struct list_head dirty; 310 struct list_head resource_dirty; 311 struct list_head enable_list; 312 unsigned pm4_dirty_cdwords; 313 unsigned ctx_pm4_ndwords; 314 315 /* The list of active queries. Only one query of each type can be active. */ 316 int num_occlusion_queries; 317 318 /* Manage queries in two separate groups: 319 * The timer ones and the others (streamout, occlusion). 320 * 321 * We do this because we should only suspend non-timer queries for u_blitter, 322 * and later if the non-timer queries are suspended, the context flush should 323 * only suspend and resume the timer queries. */ 324 struct list_head active_timer_queries; 325 unsigned num_cs_dw_timer_queries_suspend; 326 struct list_head active_nontimer_queries; 327 unsigned num_cs_dw_nontimer_queries_suspend; 328 329 unsigned num_cs_dw_streamout_end; 330 331 unsigned backend_mask; 332 unsigned max_db; /* for OQ */ 333 unsigned flags; 334 boolean predicate_drawing; 335 struct r600_range ps_resources; 336 struct r600_range vs_resources; 337 int num_ps_resources, num_vs_resources; 338 339 unsigned num_so_targets; 340 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 341 boolean streamout_start; 342 unsigned streamout_append_bitmask; 343 344 /* There is no scissor enable bit on r6xx, so we must use a workaround. 345 * These track the current scissor state. */ 346 bool scissor_enable; 347 struct pipe_scissor_state scissor_state; 348 349 /* With rasterizer discard, there doesn't have to be a pixel shader. 350 * In that case, we bind this one: */ 351 void *dummy_pixel_shader; 352 353 bool vertex_buffers_dirty; 354 boolean dual_src_blend; 355 unsigned color0_format; 356 357 struct pipe_index_buffer index_buffer; 358 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 359 unsigned nr_vertex_buffers; 360}; 361 362static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 363{ 364 atom->emit(rctx, atom); 365 atom->dirty = false; 366 if (atom->head.next && atom->head.prev) 367 LIST_DELINIT(&atom->head); 368} 369 370static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 371{ 372 if (!state->dirty) { 373 if (state->flags & EMIT_EARLY) { 374 LIST_ADD(&state->head, &rctx->dirty_states); 375 } else { 376 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 377 } 378 state->dirty = true; 379 } 380} 381 382/* evergreen_state.c */ 383void evergreen_init_state_functions(struct r600_context *rctx); 384void evergreen_init_atom_start_cs(struct r600_context *rctx); 385void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 386void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 387void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 388void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 389void evergreen_polygon_offset_update(struct r600_context *rctx); 390boolean evergreen_is_format_supported(struct pipe_screen *screen, 391 enum pipe_format format, 392 enum pipe_texture_target target, 393 unsigned sample_count, 394 unsigned usage); 395 396/* r600_blit.c */ 397void r600_init_blit_functions(struct r600_context *rctx); 398void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 399void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 400void r600_flush_depth_textures(struct r600_context *rctx); 401 402/* r600_buffer.c */ 403bool r600_init_resource(struct r600_screen *rscreen, 404 struct r600_resource *res, 405 unsigned size, unsigned alignment, 406 unsigned bind, unsigned usage); 407struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 408 const struct pipe_resource *templ); 409struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 410 void *ptr, unsigned bytes, 411 unsigned bind); 412 413/* r600_pipe.c */ 414void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 415 unsigned flags); 416 417/* r600_query.c */ 418void r600_init_query_functions(struct r600_context *rctx); 419void r600_suspend_nontimer_queries(struct r600_context *ctx); 420void r600_resume_nontimer_queries(struct r600_context *ctx); 421void r600_suspend_timer_queries(struct r600_context *ctx); 422void r600_resume_timer_queries(struct r600_context *ctx); 423 424/* r600_resource.c */ 425void r600_init_context_resource_functions(struct r600_context *r600); 426 427/* r600_shader.c */ 428int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 429void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 430int r600_find_vs_semantic_index(struct r600_shader *vs, 431 struct r600_shader *ps, int id); 432 433/* r600_state.c */ 434void r600_set_scissor_state(struct r600_context *rctx, 435 const struct pipe_scissor_state *state); 436void r600_update_sampler_states(struct r600_context *rctx); 437void r600_init_state_functions(struct r600_context *rctx); 438void r600_init_atom_start_cs(struct r600_context *rctx); 439void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 440void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 441void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 442void *r600_create_db_flush_dsa(struct r600_context *rctx); 443void r600_polygon_offset_update(struct r600_context *rctx); 444void r600_adjust_gprs(struct r600_context *rctx); 445boolean r600_is_format_supported(struct pipe_screen *screen, 446 enum pipe_format format, 447 enum pipe_texture_target target, 448 unsigned sample_count, 449 unsigned usage); 450 451/* r600_texture.c */ 452void r600_init_screen_texture_functions(struct pipe_screen *screen); 453void r600_init_surface_functions(struct r600_context *r600); 454uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 455 const unsigned char *swizzle_view, 456 uint32_t *word4_p, uint32_t *yuv_format_p); 457unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 458 unsigned level, unsigned layer); 459 460/* r600_translate.c */ 461void r600_translate_index_buffer(struct r600_context *r600, 462 struct pipe_index_buffer *ib, 463 unsigned count); 464 465/* r600_state_common.c */ 466void r600_init_atom(struct r600_atom *atom, 467 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 468 unsigned num_dw, enum r600_atom_flags flags); 469void r600_init_common_atoms(struct r600_context *rctx); 470unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 471void r600_texture_barrier(struct pipe_context *ctx); 472void r600_set_index_buffer(struct pipe_context *ctx, 473 const struct pipe_index_buffer *ib); 474void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 475 const struct pipe_vertex_buffer *buffers); 476void *r600_create_vertex_elements(struct pipe_context *ctx, 477 unsigned count, 478 const struct pipe_vertex_element *elements); 479void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 480void r600_bind_blend_state(struct pipe_context *ctx, void *state); 481void r600_set_blend_color(struct pipe_context *ctx, 482 const struct pipe_blend_color *state); 483void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 484void r600_set_max_scissor(struct r600_context *rctx); 485void r600_bind_rs_state(struct pipe_context *ctx, void *state); 486void r600_delete_rs_state(struct pipe_context *ctx, void *state); 487void r600_sampler_view_destroy(struct pipe_context *ctx, 488 struct pipe_sampler_view *state); 489void r600_delete_state(struct pipe_context *ctx, void *state); 490void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 491void *r600_create_shader_state(struct pipe_context *ctx, 492 const struct pipe_shader_state *state); 493void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 494void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 495void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 496void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 497void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 498void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 499 struct pipe_resource *buffer); 500struct pipe_stream_output_target * 501r600_create_so_target(struct pipe_context *ctx, 502 struct pipe_resource *buffer, 503 unsigned buffer_offset, 504 unsigned buffer_size); 505void r600_so_target_destroy(struct pipe_context *ctx, 506 struct pipe_stream_output_target *target); 507void r600_set_so_targets(struct pipe_context *ctx, 508 unsigned num_targets, 509 struct pipe_stream_output_target **targets, 510 unsigned append_bitmask); 511void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 512 const struct pipe_stencil_ref *state); 513void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 514uint32_t r600_translate_stencil_op(int s_op); 515uint32_t r600_translate_fill(uint32_t func); 516unsigned r600_tex_wrap(unsigned wrap); 517unsigned r600_tex_filter(unsigned filter); 518unsigned r600_tex_mipfilter(unsigned filter); 519unsigned r600_tex_compare(unsigned compare); 520 521/* 522 * Helpers for building command buffers 523 */ 524 525#define PKT3_SET_CONFIG_REG 0x68 526#define PKT3_SET_CONTEXT_REG 0x69 527#define PKT3_SET_CTL_CONST 0x6F 528#define PKT3_SET_LOOP_CONST 0x6C 529 530#define R600_CONFIG_REG_OFFSET 0x08000 531#define R600_CONTEXT_REG_OFFSET 0x28000 532#define R600_CTL_CONST_OFFSET 0x3CFF0 533#define R600_LOOP_CONST_OFFSET 0X0003E200 534#define EG_LOOP_CONST_OFFSET 0x0003A200 535 536#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 537#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 538#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 539#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 540#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 541 542static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 543{ 544 cb->buf[cb->atom.num_dw++] = value; 545} 546 547static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 548{ 549 assert(reg < R600_CONTEXT_REG_OFFSET); 550 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 551 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 552 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 553} 554 555static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 556{ 557 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 558 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 559 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 560 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 561} 562 563static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 564{ 565 assert(reg >= R600_CTL_CONST_OFFSET); 566 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 567 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 568 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 569} 570 571static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 572{ 573 assert(reg >= R600_LOOP_CONST_OFFSET); 574 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 575 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 576 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 577} 578 579static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 580{ 581 assert(reg >= EG_LOOP_CONST_OFFSET); 582 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 583 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 584 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 585} 586 587static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 588{ 589 r600_store_config_reg_seq(cb, reg, 1); 590 r600_store_value(cb, value); 591} 592 593static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 594{ 595 r600_store_context_reg_seq(cb, reg, 1); 596 r600_store_value(cb, value); 597} 598 599static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 600{ 601 r600_store_ctl_const_seq(cb, reg, 1); 602 r600_store_value(cb, value); 603} 604 605static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 606{ 607 r600_store_loop_const_seq(cb, reg, 1); 608 r600_store_value(cb, value); 609} 610 611static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 612{ 613 eg_store_loop_const_seq(cb, reg, 1); 614 r600_store_value(cb, value); 615} 616 617void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 618void r600_release_command_buffer(struct r600_command_buffer *cb); 619 620/* 621 * Helpers for emitting state into a command stream directly. 622 */ 623 624static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 625 enum radeon_bo_usage usage) 626{ 627 assert(usage); 628 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 629} 630 631static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 632{ 633 cs->buf[cs->cdw++] = value; 634} 635 636static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 637{ 638 assert(reg < R600_CONTEXT_REG_OFFSET); 639 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 640 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 641 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 642} 643 644static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 645{ 646 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 647 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 648 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 649 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 650} 651 652static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 653{ 654 assert(reg >= R600_CTL_CONST_OFFSET); 655 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 656 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 657 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 658} 659 660static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 661{ 662 r600_write_config_reg_seq(cs, reg, 1); 663 r600_write_value(cs, value); 664} 665 666static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 667{ 668 r600_write_context_reg_seq(cs, reg, 1); 669 r600_write_value(cs, value); 670} 671 672static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 673{ 674 r600_write_ctl_const_seq(cs, reg, 1); 675 r600_write_value(cs, value); 676} 677 678/* 679 * common helpers 680 */ 681static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 682{ 683 return value * (1 << frac_bits); 684} 685#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 686 687static inline unsigned r600_tex_aniso_filter(unsigned filter) 688{ 689 if (filter <= 1) return 0; 690 if (filter <= 2) return 1; 691 if (filter <= 4) return 2; 692 if (filter <= 8) return 3; 693 /* else */ return 4; 694} 695 696/* 12.4 fixed-point */ 697static INLINE unsigned r600_pack_float_12p4(float x) 698{ 699 return x <= 0 ? 0 : 700 x >= 4096 ? 0xffff : x * 16; 701} 702 703static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 704{ 705 struct r600_screen *rscreen = (struct r600_screen*)screen; 706 struct r600_resource *rresource = (struct r600_resource*)resource; 707 708 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 709} 710 711#endif 712