r600_pipe.h revision 507337864fa80caf9f26602324d2c28dd0a75d61
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_shader.h" 32#include "r600_resource.h" 33 34#define R600_MAX_CONST_BUFFERS 2 35#define R600_MAX_CONST_BUFFER_SIZE 4096 36 37#ifdef PIPE_ARCH_BIG_ENDIAN 38#define R600_BIG_ENDIAN 1 39#else 40#define R600_BIG_ENDIAN 0 41#endif 42 43enum r600_atom_flags { 44 /* When set, atoms are added at the beginning of the dirty list 45 * instead of the end. */ 46 EMIT_EARLY = (1 << 0) 47}; 48 49/* This encapsulates a state or an operation which can emitted into the GPU 50 * command stream. It's not limited to states only, it can be used for anything 51 * that wants to write commands into the CS (e.g. cache flushes). */ 52struct r600_atom { 53 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 54 55 unsigned num_dw; 56 enum r600_atom_flags flags; 57 bool dirty; 58 59 struct list_head head; 60}; 61 62/* This is an atom containing GPU commands that never change. 63 * This is supposed to be copied directly into the CS. */ 64struct r600_command_buffer { 65 struct r600_atom atom; 66 uint32_t *buf; 67 unsigned max_num_dw; 68}; 69 70struct r600_surface_sync_cmd { 71 struct r600_atom atom; 72 unsigned flush_flags; /* CP_COHER_CNTL */ 73}; 74 75struct r600_db_misc_state { 76 struct r600_atom atom; 77 bool occlusion_query_enabled; 78 bool flush_depthstencil_enabled; 79}; 80 81enum r600_pipe_state_id { 82 R600_PIPE_STATE_BLEND = 0, 83 R600_PIPE_STATE_BLEND_COLOR, 84 R600_PIPE_STATE_CONFIG, 85 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 86 R600_PIPE_STATE_CLIP, 87 R600_PIPE_STATE_SCISSOR, 88 R600_PIPE_STATE_VIEWPORT, 89 R600_PIPE_STATE_RASTERIZER, 90 R600_PIPE_STATE_VGT, 91 R600_PIPE_STATE_FRAMEBUFFER, 92 R600_PIPE_STATE_DSA, 93 R600_PIPE_STATE_STENCIL_REF, 94 R600_PIPE_STATE_PS_SHADER, 95 R600_PIPE_STATE_VS_SHADER, 96 R600_PIPE_STATE_CONSTANT, 97 R600_PIPE_STATE_SAMPLER, 98 R600_PIPE_STATE_RESOURCE, 99 R600_PIPE_STATE_POLYGON_OFFSET, 100 R600_PIPE_STATE_FETCH_SHADER, 101 R600_PIPE_NSTATES 102}; 103 104struct r600_pipe_fences { 105 struct r600_resource *bo; 106 unsigned *data; 107 unsigned next_index; 108 /* linked list of preallocated blocks */ 109 struct list_head blocks; 110 /* linked list of freed fences */ 111 struct list_head pool; 112 pipe_mutex mutex; 113}; 114 115struct r600_screen { 116 struct pipe_screen screen; 117 struct radeon_winsys *ws; 118 unsigned family; 119 enum chip_class chip_class; 120 struct radeon_info info; 121 struct r600_tiling_info tiling_info; 122 struct util_slab_mempool pool_buffers; 123 struct r600_pipe_fences fences; 124 125 unsigned num_contexts; 126 bool use_surface_alloc; 127 int glsl_feature_level; 128 129 /* for thread-safe write accessing to num_contexts */ 130 pipe_mutex mutex_num_contexts; 131}; 132 133struct r600_pipe_sampler_view { 134 struct pipe_sampler_view base; 135 struct r600_pipe_resource_state state; 136}; 137 138struct r600_pipe_rasterizer { 139 struct r600_pipe_state rstate; 140 boolean flatshade; 141 boolean two_side; 142 unsigned sprite_coord_enable; 143 unsigned clip_plane_enable; 144 unsigned pa_sc_line_stipple; 145 unsigned pa_cl_clip_cntl; 146 float offset_units; 147 float offset_scale; 148 bool scissor_enable; 149}; 150 151struct r600_pipe_blend { 152 struct r600_pipe_state rstate; 153 unsigned cb_target_mask; 154 unsigned cb_color_control; 155 bool dual_src_blend; 156}; 157 158struct r600_pipe_dsa { 159 struct r600_pipe_state rstate; 160 unsigned alpha_ref; 161 ubyte valuemask[2]; 162 ubyte writemask[2]; 163 bool is_flush; 164}; 165 166struct r600_vertex_element 167{ 168 unsigned count; 169 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 170 struct r600_resource *fetch_shader; 171 unsigned fs_size; 172 struct r600_pipe_state rstate; 173}; 174 175struct r600_pipe_shader { 176 struct r600_shader shader; 177 struct r600_pipe_state rstate; 178 struct r600_resource *bo; 179 struct r600_resource *bo_fetch; 180 struct r600_vertex_element vertex_elements; 181 struct tgsi_token *tokens; 182 unsigned sprite_coord_enable; 183 unsigned flatshade; 184 unsigned pa_cl_vs_out_cntl; 185 unsigned ps_cb_shader_mask; 186 struct pipe_stream_output_info so; 187}; 188 189struct r600_pipe_sampler_state { 190 struct r600_pipe_state rstate; 191 boolean seamless_cube_map; 192}; 193 194/* needed for blitter save */ 195#define NUM_TEX_UNITS 16 196 197struct r600_textures_info { 198 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 199 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 200 unsigned n_views; 201 unsigned n_samplers; 202 bool samplers_dirty; 203 bool is_array_sampler[NUM_TEX_UNITS]; 204}; 205 206struct r600_fence { 207 struct pipe_reference reference; 208 unsigned index; /* in the shared bo */ 209 struct r600_resource *sleep_bo; 210 struct list_head head; 211}; 212 213#define FENCE_BLOCK_SIZE 16 214 215struct r600_fence_block { 216 struct r600_fence fences[FENCE_BLOCK_SIZE]; 217 struct list_head head; 218}; 219 220#define R600_CONSTANT_ARRAY_SIZE 256 221#define R600_RESOURCE_ARRAY_SIZE 160 222 223struct r600_stencil_ref 224{ 225 ubyte ref_value[2]; 226 ubyte valuemask[2]; 227 ubyte writemask[2]; 228}; 229 230struct r600_constbuf_state 231{ 232 struct r600_atom atom; 233 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 234 uint32_t enabled_mask; 235 uint32_t dirty_mask; 236}; 237 238struct r600_context { 239 struct pipe_context context; 240 struct blitter_context *blitter; 241 enum radeon_family family; 242 enum chip_class chip_class; 243 boolean has_vertex_cache; 244 unsigned r6xx_num_clause_temp_gprs; 245 void *custom_dsa_flush; 246 struct r600_screen *screen; 247 struct radeon_winsys *ws; 248 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 249 struct r600_vertex_element *vertex_elements; 250 struct pipe_framebuffer_state framebuffer; 251 unsigned cb_target_mask; 252 unsigned fb_cb_shader_mask; 253 unsigned cb_shader_mask; 254 unsigned cb_color_control; 255 unsigned pa_sc_line_stipple; 256 unsigned pa_cl_clip_cntl; 257 /* for saving when using blitter */ 258 struct pipe_stencil_ref stencil_ref; 259 struct pipe_viewport_state viewport; 260 struct pipe_clip_state clip; 261 struct r600_pipe_shader *ps_shader; 262 struct r600_pipe_shader *vs_shader; 263 struct r600_pipe_rasterizer *rasterizer; 264 struct r600_pipe_state vgt; 265 struct r600_pipe_state spi; 266 struct pipe_query *current_render_cond; 267 unsigned current_render_cond_mode; 268 struct pipe_query *saved_render_cond; 269 unsigned saved_render_cond_mode; 270 /* shader information */ 271 boolean two_side; 272 unsigned sprite_coord_enable; 273 boolean export_16bpc; 274 unsigned alpha_ref; 275 boolean alpha_ref_dirty; 276 unsigned nr_cbufs; 277 struct r600_textures_info vs_samplers; 278 struct r600_textures_info ps_samplers; 279 280 struct u_upload_mgr *uploader; 281 struct util_slab_mempool pool_transfers; 282 boolean have_depth_texture, have_depth_fb; 283 284 unsigned default_ps_gprs, default_vs_gprs; 285 286 /* States based on r600_atom. */ 287 struct list_head dirty_states; 288 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 289 struct r600_surface_sync_cmd surface_sync_cmd; 290 struct r600_atom r6xx_flush_and_inv_cmd; 291 struct r600_db_misc_state db_misc_state; 292 struct r600_atom vertex_buffer_state; 293 struct r600_constbuf_state vs_constbuf_state; 294 struct r600_constbuf_state ps_constbuf_state; 295 296 struct radeon_winsys_cs *cs; 297 298 struct r600_range *range; 299 unsigned nblocks; 300 struct r600_block **blocks; 301 struct list_head dirty; 302 struct list_head resource_dirty; 303 struct list_head enable_list; 304 unsigned pm4_dirty_cdwords; 305 unsigned ctx_pm4_ndwords; 306 307 /* The list of active queries. Only one query of each type can be active. */ 308 int num_occlusion_queries; 309 310 /* Manage queries in two separate groups: 311 * The timer ones and the others (streamout, occlusion). 312 * 313 * We do this because we should only suspend non-timer queries for u_blitter, 314 * and later if the non-timer queries are suspended, the context flush should 315 * only suspend and resume the timer queries. */ 316 struct list_head active_timer_queries; 317 unsigned num_cs_dw_timer_queries_suspend; 318 struct list_head active_nontimer_queries; 319 unsigned num_cs_dw_nontimer_queries_suspend; 320 321 unsigned num_cs_dw_streamout_end; 322 323 unsigned backend_mask; 324 unsigned max_db; /* for OQ */ 325 unsigned flags; 326 boolean predicate_drawing; 327 struct r600_range ps_resources; 328 struct r600_range vs_resources; 329 int num_ps_resources, num_vs_resources; 330 331 unsigned num_so_targets; 332 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 333 boolean streamout_start; 334 unsigned streamout_append_bitmask; 335 336 /* There is no scissor enable bit on r6xx, so we must use a workaround. 337 * These track the current scissor state. */ 338 bool scissor_enable; 339 struct pipe_scissor_state scissor_state; 340 341 /* With rasterizer discard, there doesn't have to be a pixel shader. 342 * In that case, we bind this one: */ 343 void *dummy_pixel_shader; 344 345 boolean dual_src_blend; 346 unsigned color0_format; 347 348 /* Vertex and index buffers. */ 349 bool vertex_buffers_dirty; 350 struct pipe_index_buffer index_buffer; 351 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 352 unsigned nr_vertex_buffers; 353}; 354 355static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 356{ 357 atom->emit(rctx, atom); 358 atom->dirty = false; 359 if (atom->head.next && atom->head.prev) 360 LIST_DELINIT(&atom->head); 361} 362 363static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 364{ 365 if (!state->dirty) { 366 if (state->flags & EMIT_EARLY) { 367 LIST_ADD(&state->head, &rctx->dirty_states); 368 } else { 369 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 370 } 371 state->dirty = true; 372 } 373} 374 375/* evergreen_state.c */ 376void evergreen_init_state_functions(struct r600_context *rctx); 377void evergreen_init_atom_start_cs(struct r600_context *rctx); 378void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 379void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 380void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 381void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 382void evergreen_polygon_offset_update(struct r600_context *rctx); 383boolean evergreen_is_format_supported(struct pipe_screen *screen, 384 enum pipe_format format, 385 enum pipe_texture_target target, 386 unsigned sample_count, 387 unsigned usage); 388 389/* r600_blit.c */ 390void r600_init_blit_functions(struct r600_context *rctx); 391void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 392void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 393void r600_flush_depth_textures(struct r600_context *rctx); 394 395/* r600_buffer.c */ 396bool r600_init_resource(struct r600_screen *rscreen, 397 struct r600_resource *res, 398 unsigned size, unsigned alignment, 399 unsigned bind, unsigned usage); 400struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 401 const struct pipe_resource *templ); 402struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 403 void *ptr, unsigned bytes, 404 unsigned bind); 405 406/* r600_pipe.c */ 407void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 408 unsigned flags); 409 410/* r600_query.c */ 411void r600_init_query_functions(struct r600_context *rctx); 412void r600_suspend_nontimer_queries(struct r600_context *ctx); 413void r600_resume_nontimer_queries(struct r600_context *ctx); 414void r600_suspend_timer_queries(struct r600_context *ctx); 415void r600_resume_timer_queries(struct r600_context *ctx); 416 417/* r600_resource.c */ 418void r600_init_context_resource_functions(struct r600_context *r600); 419 420/* r600_shader.c */ 421int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 422void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 423int r600_find_vs_semantic_index(struct r600_shader *vs, 424 struct r600_shader *ps, int id); 425 426/* r600_state.c */ 427void r600_set_scissor_state(struct r600_context *rctx, 428 const struct pipe_scissor_state *state); 429void r600_update_sampler_states(struct r600_context *rctx); 430void r600_init_state_functions(struct r600_context *rctx); 431void r600_init_atom_start_cs(struct r600_context *rctx); 432void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 433void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 434void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 435void *r600_create_db_flush_dsa(struct r600_context *rctx); 436void r600_polygon_offset_update(struct r600_context *rctx); 437void r600_adjust_gprs(struct r600_context *rctx); 438boolean r600_is_format_supported(struct pipe_screen *screen, 439 enum pipe_format format, 440 enum pipe_texture_target target, 441 unsigned sample_count, 442 unsigned usage); 443 444/* r600_texture.c */ 445void r600_init_screen_texture_functions(struct pipe_screen *screen); 446void r600_init_surface_functions(struct r600_context *r600); 447uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 448 const unsigned char *swizzle_view, 449 uint32_t *word4_p, uint32_t *yuv_format_p); 450unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 451 unsigned level, unsigned layer); 452 453/* r600_translate.c */ 454void r600_translate_index_buffer(struct r600_context *r600, 455 struct pipe_index_buffer *ib, 456 unsigned count); 457 458/* r600_state_common.c */ 459void r600_init_atom(struct r600_atom *atom, 460 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 461 unsigned num_dw, enum r600_atom_flags flags); 462void r600_init_common_atoms(struct r600_context *rctx); 463unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 464void r600_texture_barrier(struct pipe_context *ctx); 465void r600_set_index_buffer(struct pipe_context *ctx, 466 const struct pipe_index_buffer *ib); 467void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 468 const struct pipe_vertex_buffer *buffers); 469void *r600_create_vertex_elements(struct pipe_context *ctx, 470 unsigned count, 471 const struct pipe_vertex_element *elements); 472void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 473void r600_bind_blend_state(struct pipe_context *ctx, void *state); 474void r600_set_blend_color(struct pipe_context *ctx, 475 const struct pipe_blend_color *state); 476void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 477void r600_set_max_scissor(struct r600_context *rctx); 478void r600_bind_rs_state(struct pipe_context *ctx, void *state); 479void r600_delete_rs_state(struct pipe_context *ctx, void *state); 480void r600_sampler_view_destroy(struct pipe_context *ctx, 481 struct pipe_sampler_view *state); 482void r600_delete_state(struct pipe_context *ctx, void *state); 483void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 484void *r600_create_shader_state(struct pipe_context *ctx, 485 const struct pipe_shader_state *state); 486void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 487void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 488void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 489void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 490void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 491void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 492 struct pipe_constant_buffer *cb); 493struct pipe_stream_output_target * 494r600_create_so_target(struct pipe_context *ctx, 495 struct pipe_resource *buffer, 496 unsigned buffer_offset, 497 unsigned buffer_size); 498void r600_so_target_destroy(struct pipe_context *ctx, 499 struct pipe_stream_output_target *target); 500void r600_set_so_targets(struct pipe_context *ctx, 501 unsigned num_targets, 502 struct pipe_stream_output_target **targets, 503 unsigned append_bitmask); 504void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 505 const struct pipe_stencil_ref *state); 506void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 507uint32_t r600_translate_stencil_op(int s_op); 508uint32_t r600_translate_fill(uint32_t func); 509unsigned r600_tex_wrap(unsigned wrap); 510unsigned r600_tex_filter(unsigned filter); 511unsigned r600_tex_mipfilter(unsigned filter); 512unsigned r600_tex_compare(unsigned compare); 513 514/* 515 * Helpers for building command buffers 516 */ 517 518#define PKT3_SET_CONFIG_REG 0x68 519#define PKT3_SET_CONTEXT_REG 0x69 520#define PKT3_SET_CTL_CONST 0x6F 521#define PKT3_SET_LOOP_CONST 0x6C 522 523#define R600_CONFIG_REG_OFFSET 0x08000 524#define R600_CONTEXT_REG_OFFSET 0x28000 525#define R600_CTL_CONST_OFFSET 0x3CFF0 526#define R600_LOOP_CONST_OFFSET 0X0003E200 527#define EG_LOOP_CONST_OFFSET 0x0003A200 528 529#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 530#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 531#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 532#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 533#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 534 535static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 536{ 537 cb->buf[cb->atom.num_dw++] = value; 538} 539 540static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 541{ 542 assert(reg < R600_CONTEXT_REG_OFFSET); 543 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 544 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 545 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 546} 547 548static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 549{ 550 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 551 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 552 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 553 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 554} 555 556static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 557{ 558 assert(reg >= R600_CTL_CONST_OFFSET); 559 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 560 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 561 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 562} 563 564static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 565{ 566 assert(reg >= R600_LOOP_CONST_OFFSET); 567 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 568 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 569 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 570} 571 572static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 573{ 574 assert(reg >= EG_LOOP_CONST_OFFSET); 575 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 576 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 577 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 578} 579 580static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 581{ 582 r600_store_config_reg_seq(cb, reg, 1); 583 r600_store_value(cb, value); 584} 585 586static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 587{ 588 r600_store_context_reg_seq(cb, reg, 1); 589 r600_store_value(cb, value); 590} 591 592static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 593{ 594 r600_store_ctl_const_seq(cb, reg, 1); 595 r600_store_value(cb, value); 596} 597 598static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 599{ 600 r600_store_loop_const_seq(cb, reg, 1); 601 r600_store_value(cb, value); 602} 603 604static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 605{ 606 eg_store_loop_const_seq(cb, reg, 1); 607 r600_store_value(cb, value); 608} 609 610void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 611void r600_release_command_buffer(struct r600_command_buffer *cb); 612 613/* 614 * Helpers for emitting state into a command stream directly. 615 */ 616 617static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 618 enum radeon_bo_usage usage) 619{ 620 assert(usage); 621 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 622} 623 624static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 625{ 626 cs->buf[cs->cdw++] = value; 627} 628 629static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 630{ 631 assert(reg < R600_CONTEXT_REG_OFFSET); 632 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 633 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 634 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 635} 636 637static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 638{ 639 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 640 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 641 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 642 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 643} 644 645static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 646{ 647 assert(reg >= R600_CTL_CONST_OFFSET); 648 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 649 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 650 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 651} 652 653static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 654{ 655 r600_write_config_reg_seq(cs, reg, 1); 656 r600_write_value(cs, value); 657} 658 659static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 660{ 661 r600_write_context_reg_seq(cs, reg, 1); 662 r600_write_value(cs, value); 663} 664 665static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 666{ 667 r600_write_ctl_const_seq(cs, reg, 1); 668 r600_write_value(cs, value); 669} 670 671/* 672 * common helpers 673 */ 674static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 675{ 676 return value * (1 << frac_bits); 677} 678#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 679 680static inline unsigned r600_tex_aniso_filter(unsigned filter) 681{ 682 if (filter <= 1) return 0; 683 if (filter <= 2) return 1; 684 if (filter <= 4) return 2; 685 if (filter <= 8) return 3; 686 /* else */ return 4; 687} 688 689/* 12.4 fixed-point */ 690static INLINE unsigned r600_pack_float_12p4(float x) 691{ 692 return x <= 0 ? 0 : 693 x >= 4096 ? 0xffff : x * 16; 694} 695 696static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 697{ 698 struct r600_screen *rscreen = (struct r600_screen*)screen; 699 struct r600_resource *rresource = (struct r600_resource*)resource; 700 701 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 702} 703 704#endif 705