r600_pipe.h revision a652cc40b9641d0b51e0a8533924a50073a50aae
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30 31#include "pipe/p_state.h" 32#include "pipe/p_screen.h" 33#include "pipe/p_context.h" 34#include "util/u_math.h" 35#include "util/u_slab.h" 36#include "util/u_vbuf.h" 37#include "r600.h" 38#include "r600_public.h" 39#include "r600_shader.h" 40#include "r600_resource.h" 41 42#define R600_MAX_CONST_BUFFERS 2 43#define R600_MAX_CONST_BUFFER_SIZE 4096 44 45#ifdef PIPE_ARCH_BIG_ENDIAN 46#define R600_BIG_ENDIAN 1 47#else 48#define R600_BIG_ENDIAN 0 49#endif 50 51enum r600_pipe_state_id { 52 R600_PIPE_STATE_BLEND = 0, 53 R600_PIPE_STATE_BLEND_COLOR, 54 R600_PIPE_STATE_CONFIG, 55 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 56 R600_PIPE_STATE_CLIP, 57 R600_PIPE_STATE_SCISSOR, 58 R600_PIPE_STATE_VIEWPORT, 59 R600_PIPE_STATE_RASTERIZER, 60 R600_PIPE_STATE_VGT, 61 R600_PIPE_STATE_FRAMEBUFFER, 62 R600_PIPE_STATE_DSA, 63 R600_PIPE_STATE_STENCIL_REF, 64 R600_PIPE_STATE_PS_SHADER, 65 R600_PIPE_STATE_VS_SHADER, 66 R600_PIPE_STATE_CONSTANT, 67 R600_PIPE_STATE_SAMPLER, 68 R600_PIPE_STATE_RESOURCE, 69 R600_PIPE_STATE_POLYGON_OFFSET, 70 R600_PIPE_STATE_FETCH_SHADER, 71 R600_PIPE_NSTATES 72}; 73 74struct r600_pipe_fences { 75 struct r600_resource *bo; 76 unsigned *data; 77 unsigned next_index; 78 /* linked list of preallocated blocks */ 79 struct list_head blocks; 80 /* linked list of freed fences */ 81 struct list_head pool; 82 pipe_mutex mutex; 83}; 84 85struct r600_screen { 86 struct pipe_screen screen; 87 struct radeon_winsys *ws; 88 unsigned family; 89 enum chip_class chip_class; 90 struct radeon_info info; 91 struct r600_tiling_info tiling_info; 92 struct util_slab_mempool pool_buffers; 93 struct r600_pipe_fences fences; 94 95 unsigned num_contexts; 96 97 /* for thread-safe write accessing to num_contexts */ 98 pipe_mutex mutex_num_contexts; 99}; 100 101struct r600_pipe_sampler_view { 102 struct pipe_sampler_view base; 103 struct r600_pipe_resource_state state; 104}; 105 106struct r600_pipe_rasterizer { 107 struct r600_pipe_state rstate; 108 boolean flatshade; 109 boolean two_side; 110 unsigned sprite_coord_enable; 111 unsigned clip_plane_enable; 112 unsigned pa_sc_line_stipple; 113 unsigned pa_su_sc_mode_cntl; 114 float offset_units; 115 float offset_scale; 116}; 117 118struct r600_pipe_blend { 119 struct r600_pipe_state rstate; 120 unsigned cb_target_mask; 121 unsigned cb_color_control; 122}; 123 124struct r600_pipe_dsa { 125 struct r600_pipe_state rstate; 126 unsigned alpha_ref; 127 ubyte valuemask[2]; 128 ubyte writemask[2]; 129}; 130 131struct r600_vertex_element 132{ 133 unsigned count; 134 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 135 struct u_vbuf_elements *vmgr_elements; 136 struct r600_resource *fetch_shader; 137 unsigned fs_size; 138 struct r600_pipe_state rstate; 139 /* if offset is to big for fetch instructio we need to alterate 140 * offset of vertex buffer, record here the offset need to add 141 */ 142 unsigned vbuffer_need_offset; 143 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; 144}; 145 146struct r600_pipe_shader { 147 struct r600_shader shader; 148 struct r600_pipe_state rstate; 149 struct r600_resource *bo; 150 struct r600_resource *bo_fetch; 151 struct r600_vertex_element vertex_elements; 152 struct tgsi_token *tokens; 153 unsigned sprite_coord_enable; 154 unsigned flatshade; 155 struct pipe_stream_output_info so; 156}; 157 158struct r600_pipe_sampler_state { 159 struct r600_pipe_state rstate; 160 boolean seamless_cube_map; 161}; 162 163/* needed for blitter save */ 164#define NUM_TEX_UNITS 16 165 166struct r600_textures_info { 167 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 168 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 169 unsigned n_views; 170 unsigned n_samplers; 171 bool samplers_dirty; 172 bool is_array_sampler[NUM_TEX_UNITS]; 173}; 174 175struct r600_fence { 176 struct pipe_reference reference; 177 unsigned index; /* in the shared bo */ 178 struct list_head head; 179}; 180 181#define FENCE_BLOCK_SIZE 16 182 183struct r600_fence_block { 184 struct r600_fence fences[FENCE_BLOCK_SIZE]; 185 struct list_head head; 186}; 187 188#define R600_CONSTANT_ARRAY_SIZE 256 189#define R600_RESOURCE_ARRAY_SIZE 160 190 191struct r600_stencil_ref 192{ 193 ubyte ref_value[2]; 194 ubyte valuemask[2]; 195 ubyte writemask[2]; 196}; 197 198struct r600_pipe_context { 199 struct pipe_context context; 200 struct blitter_context *blitter; 201 enum radeon_family family; 202 enum chip_class chip_class; 203 unsigned r6xx_num_clause_temp_gprs; 204 void *custom_dsa_flush; 205 struct r600_screen *screen; 206 struct radeon_winsys *ws; 207 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 208 struct r600_context ctx; 209 struct r600_vertex_element *vertex_elements; 210 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; 211 struct pipe_framebuffer_state framebuffer; 212 unsigned cb_target_mask; 213 unsigned cb_color_control; 214 unsigned pa_sc_line_stipple; 215 unsigned pa_su_sc_mode_cntl; 216 /* for saving when using blitter */ 217 struct pipe_stencil_ref stencil_ref; 218 struct pipe_viewport_state viewport; 219 struct pipe_clip_state clip; 220 struct r600_pipe_state config; 221 struct r600_pipe_shader *ps_shader; 222 struct r600_pipe_shader *vs_shader; 223 struct r600_pipe_state vs_const_buffer; 224 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 225 struct r600_pipe_state ps_const_buffer; 226 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 227 struct r600_pipe_rasterizer *rasterizer; 228 struct r600_pipe_state vgt; 229 struct r600_pipe_state spi; 230 struct pipe_query *current_render_cond; 231 unsigned current_render_cond_mode; 232 struct pipe_query *saved_render_cond; 233 unsigned saved_render_cond_mode; 234 /* shader information */ 235 boolean two_side; 236 unsigned user_clip_plane_enable; 237 unsigned clip_dist_enable; 238 unsigned sprite_coord_enable; 239 boolean export_16bpc; 240 unsigned alpha_ref; 241 boolean alpha_ref_dirty; 242 unsigned nr_cbufs; 243 struct r600_textures_info vs_samplers; 244 struct r600_textures_info ps_samplers; 245 246 struct u_vbuf *vbuf_mgr; 247 struct util_slab_mempool pool_transfers; 248 boolean have_depth_texture, have_depth_fb; 249 250 unsigned default_ps_gprs, default_vs_gprs; 251}; 252 253/* evergreen_state.c */ 254void evergreen_init_state_functions(struct r600_pipe_context *rctx); 255void evergreen_init_config(struct r600_pipe_context *rctx); 256void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 257void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 258void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 259void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx); 260void evergreen_polygon_offset_update(struct r600_pipe_context *rctx); 261void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx, 262 struct r600_pipe_resource_state *rstate); 263void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, 264 struct r600_pipe_resource_state *rstate, 265 struct r600_resource *rbuffer, 266 unsigned offset, unsigned stride, 267 enum radeon_bo_usage usage); 268boolean evergreen_is_format_supported(struct pipe_screen *screen, 269 enum pipe_format format, 270 enum pipe_texture_target target, 271 unsigned sample_count, 272 unsigned usage); 273 274/* r600_blit.c */ 275void r600_init_blit_functions(struct r600_pipe_context *rctx); 276void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 277void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 278void r600_flush_depth_textures(struct r600_pipe_context *rctx); 279 280/* r600_buffer.c */ 281bool r600_init_resource(struct r600_screen *rscreen, 282 struct r600_resource *res, 283 unsigned size, unsigned alignment, 284 unsigned bind, unsigned usage); 285struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 286 const struct pipe_resource *templ); 287struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 288 void *ptr, unsigned bytes, 289 unsigned bind); 290void r600_upload_index_buffer(struct r600_pipe_context *rctx, 291 struct pipe_index_buffer *ib, unsigned count); 292 293 294/* r600_pipe.c */ 295void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 296 unsigned flags); 297 298/* r600_query.c */ 299void r600_init_query_functions(struct r600_pipe_context *rctx); 300 301/* r600_resource.c */ 302void r600_init_context_resource_functions(struct r600_pipe_context *r600); 303 304/* r600_shader.c */ 305int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 306void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 307int r600_find_vs_semantic_index(struct r600_shader *vs, 308 struct r600_shader *ps, int id); 309 310/* r600_state.c */ 311void r600_update_sampler_states(struct r600_pipe_context *rctx); 312void r600_init_state_functions(struct r600_pipe_context *rctx); 313void r600_init_config(struct r600_pipe_context *rctx); 314void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 315void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 316void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 317void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx); 318void r600_polygon_offset_update(struct r600_pipe_context *rctx); 319void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx, 320 struct r600_pipe_resource_state *rstate); 321void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 322 struct r600_resource *rbuffer, 323 unsigned offset, unsigned stride, 324 enum radeon_bo_usage usage); 325void r600_adjust_gprs(struct r600_pipe_context *rctx); 326boolean r600_is_format_supported(struct pipe_screen *screen, 327 enum pipe_format format, 328 enum pipe_texture_target target, 329 unsigned sample_count, 330 unsigned usage); 331 332/* r600_texture.c */ 333void r600_init_screen_texture_functions(struct pipe_screen *screen); 334void r600_init_surface_functions(struct r600_pipe_context *r600); 335uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 336 const unsigned char *swizzle_view, 337 uint32_t *word4_p, uint32_t *yuv_format_p); 338unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 339 unsigned level, unsigned layer); 340 341/* r600_translate.c */ 342void r600_translate_index_buffer(struct r600_pipe_context *r600, 343 struct pipe_index_buffer *ib, 344 unsigned count); 345 346/* r600_state_common.c */ 347void r600_set_index_buffer(struct pipe_context *ctx, 348 const struct pipe_index_buffer *ib); 349void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 350 const struct pipe_vertex_buffer *buffers); 351void *r600_create_vertex_elements(struct pipe_context *ctx, 352 unsigned count, 353 const struct pipe_vertex_element *elements); 354void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 355void r600_bind_blend_state(struct pipe_context *ctx, void *state); 356void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 357void r600_bind_rs_state(struct pipe_context *ctx, void *state); 358void r600_delete_rs_state(struct pipe_context *ctx, void *state); 359void r600_sampler_view_destroy(struct pipe_context *ctx, 360 struct pipe_sampler_view *state); 361void r600_delete_state(struct pipe_context *ctx, void *state); 362void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 363void *r600_create_shader_state(struct pipe_context *ctx, 364 const struct pipe_shader_state *state); 365void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 366void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 367void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 368void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 369void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 370 struct pipe_resource *buffer); 371struct pipe_stream_output_target * 372r600_create_so_target(struct pipe_context *ctx, 373 struct pipe_resource *buffer, 374 unsigned buffer_offset, 375 unsigned buffer_size); 376void r600_so_target_destroy(struct pipe_context *ctx, 377 struct pipe_stream_output_target *target); 378void r600_set_so_targets(struct pipe_context *ctx, 379 unsigned num_targets, 380 struct pipe_stream_output_target **targets, 381 unsigned append_bitmask); 382void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 383 const struct pipe_stencil_ref *state); 384void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 385 386/* 387 * common helpers 388 */ 389static INLINE u32 S_FIXED(float value, u32 frac_bits) 390{ 391 return value * (1 << frac_bits); 392} 393#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 394 395static inline unsigned r600_tex_aniso_filter(unsigned filter) 396{ 397 if (filter <= 1) return 0; 398 if (filter <= 2) return 1; 399 if (filter <= 4) return 2; 400 if (filter <= 8) return 3; 401 /* else */ return 4; 402} 403 404/* 12.4 fixed-point */ 405static INLINE unsigned r600_pack_float_12p4(float x) 406{ 407 return x <= 0 ? 0 : 408 x >= 4096 ? 0xffff : x * 16; 409} 410 411#endif 412