History log of /dalvik/vm/mterp/armv5te/OP_IPUT_WIDE.S
Revision Date Author Comments
4185972e211b0c84b9fe7d90c56b28cc15e474fa 27-Sep-2011 buzbee <buzbee@google.com> Fix memory barriers (Issue 3338450)

Add extra memory barrier on volatile stores.

Change-Id: Id4a4750cdfc910eda2f0b44ead0af2a569b5735e
9f601a917c8878204482c37aec7005054b6776fa 12-Feb-2011 buzbee <buzbee@google.com> Interpreter restructuring: eliminate InterpState

The key datastructure for the interpreter is InterpState.
This change eliminates it, merging its data with the Thread structure.

Here's why:

In principio creavit Fadden Thread et InterpState. And it was good.

Thread holds thread-private state, while InterpState captures data
associated with a Dalvik interpreter activation. Because JNI calls
can result in nested interpreter invocations, we can have more than one
InterpState for each actual thread. InterpState was relatively small,
and it all worked well. It was used enough that in the Arm version
a register (rGLUE) was dedicated to it.

Then, along came the JIT guys, who saw InterpState as a convenient place
to dump all sorts of useful data that they wanted quick access to through
that dedicated register. InterpState grew and grew. In terms of
space, this wasn't a big problem - but it did mean that the initialization
cost of each interpreter activation grew as well. For applications
that do a lot of callbacks from native code into Dalvik, this is
measurable. It's also mostly useless cost because much of the JIT-related
InterpState initialization was setting up useful constants - things that
don't need to be saved and restored all the time.

The biggest problem, though, deals with thread control. When something
interesting is happening that needs all threads to be stopped (such as
GC and debugger attach), we have access to all of the Thread structures,
but we don't have access to all of the InterpState structures (which
may be buried/nested on the native stack). As a result, polling for
thread suspension is done via a one-indirection pointer chase. InterpState
itself can't hold the stop bits because we can't always find it, so
instead it holds a pointer to the global or thread-specific stop control.

Yuck.

With this change, we eliminate InterpState and merge all needed data
into Thread. Further, we replace the decidated rGLUE register with a
pointer to the Thread structure (rSELF). The small subset of state
data that needs to be saved and restored across nested interpreter
activations is collected into a record that is saved to the interpreter
frame, and restored on exit. Further, these small records are linked
together to allow tracebacks to show nested activations. Old InterpState
variables that simply contain useful constants are initialized once at
thread creation time.

This CL is large enough by itself that the new ability to streamline
suspend checks is not done here - that will happen in a future CL. Here
we just focus on consolidation.

Change-Id: Ide6b2fb85716fea454ac113f5611263a96687356
c35a2ef53d0cccd6f924eeba36633220ec67c32e 17-Jun-2010 Andy McFadden <fadden@android.com> Add opcodes for volatile field accesses

This adds instructions for {i,s}{get,put}{,-object}-volatile, for a
total of eight new instructions.

On SMP systems, these instructions will be substituted in for existing
field access instructions, either by dexopt or during just-in-time
verification. Unlike the wide-volatile instructions, these will not be
used at all when the VM is not built for SMP.

(Ideally we'd omit the volatile instruction implementations entirely on
non-SMP builds, but that requires a little work in gen-mterp.py.)

The change defines and implements the opcodes and support methods, but
does not cause them to be used.

Also, changed dvmQuasiAtomicRead64's argument to be const.

Change-Id: I9e44fe881e87f27aa41f6c6e898ec4402cb5493e
6e10b9aaa72425a4825a25f0043533d0c6fdbba4 15-Jun-2010 Andy McFadden <fadden@android.com> Atomic op cleanup.

Replaced VM-local macros for barrier and CAS calls with the actual
versions provided by cutils.

ATOMIC_CMP_SWAP(addr,old,new) --> android_atomic_release_cas(old,new,addr)

MEM_BARRIER --> ANDROID_MEMBAR_FULL

Renamed android_quasiatomic* to dvmQuasiAtomic*.

Didn't change how anything works, just the names.

Change-Id: I8c68f28e1f7c9cb832183e0918d097dfe6a2cac8
7365493ad8d360c1dcf9cd8b6eee62747af01cae 09-Jun-2010 Carl Shapiro <cshapiro@google.com> Remove repeated newlines at the end of files.

Change-Id: I1e3d103a7b932ef21acedb6438c0f26b315df28f
fbdcfb9ea9e2a78f295834424c3f24986ea45dac 29-May-2010 Brian Carlstrom <bdc@google.com> Merge remote branch 'goog/dalvik-dev' into dalvik-dev-to-master

Change-Id: I0c0edb3ebf0d5e040d6bbbf60269fab0deb70ef9
861b33855aff080278ea5125e4372a2d4bf8aef5 06-Mar-2010 Andy McFadden <fadden@android.com> Make wide-volatile loads and stores atomic.

This implements the four wide-volatile instructions added in a previous
change, and modifies the verifier to substitute the opcodes into the
instruction stream when appropriate.

For mterp, the ARM wide get/put instructions now have conditional code
that replaces ldrd/strd with a call to the quasiatomic functions. The
C version does essentially the same thing. ARMv4T lacks ldrd/stdrd, and
uses separate implementations for the wide field accesses, so those were
updated as well. x86 will just use stubs.

The JIT should punt these to the interpreter.

Change-Id: Ife88559ed1a698c3267d43c454896f6b12081c0f
Also:
- We don't seem to be using the negative widths in the instruction
table. Not sure they're useful anymore.
- Tabs -> spaces in x86-atom throw-verification-error impl.
f6c387128427e121477c1b32ad35cdcaa5101ba3 04-Mar-2009 The Android Open Source Project <initial-contribution@android.com> auto import from //depot/cupcake/@135843
f72d5de56a522ac3be03873bdde26f23a5eeeb3c 04-Mar-2009 The Android Open Source Project <initial-contribution@android.com> auto import from //depot/cupcake/@135843
89c1feb0a69a7707b271086e749975b3f7acacf7 18-Dec-2008 The Android Open Source Project <initial-contribution@android.com> Code drop from //branches/cupcake/...@124589