| a7d59bbafea5430fe81fc21ba94ddf6f6a63b0b3 |
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24-Feb-2011 |
buzbee <buzbee@google.com> |
New interpreter breakout mechanism
Introduce parallel handler entry points for mterp interpreters as a step
towards fully supporting debug, profile and JIT within mterp (instead of
bailing out to the portable debug interpreter).
This CL contains most of the structural changes that need to happen,
but does not yet enable the new switch mode. In short, within the
mterp assembly interpreter register rIBASE points to an array of handlers
for Dalvik opcodes. Instead of periodically checking for suspend,
debug, profiling and JIT trace selection breakouts, rIBASE may simply
be altered to point to the parallel breakout handlers when control needs
to be rerouted. This will enable us to eliminate the separate portable
debug interpreter and the entire mechanism of switching between the fast
and portable interpreters.
The x86 implementation required a large number of changes because of the
need to dedicate a register to holding the table base. It will now use %edx
(which was previously scratch).
Changes include:
o Support for two styles of mterp assembly code generation: computed goto
and jump table (ARM uses computed goto, x86 uses jump table)
o New mterp config operators to trigger generation of alternate entry points.
o Alternate entries route execution through new dvmCheckInst(). That's
where the checking code will go.
o For x86, reserved register edx as dedicated rIBASE.
o For jump-table mterps, ignore "%break" operator and allow variable-sized
handlers with no "sister" region.
Note that the x86-atom implementation will need substantial changes
to function in this new model.
Change-Id: I3a22048adb7dcfdeba4f94fbb977b26c3ab2fcb3
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| f3e177289ac078f18401cfd8eebafe584dd0d01f |
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12-Sep-2010 |
buzbee <buzbee@google.com> |
x86 mterp: reduce x86/x86-atom differences
To ease future x86 development, elminate unnecessary differences
between x86 and x86-atom targets.
1. Macros instead of defines (cosmetic change)
2. Register naming convention (cosmetic change)
3. Register usage convention
- Drop rIBASE, freeing %edx for general usage
- use %edi for rPC (callee-save) & eliminate spills
4. Spill & temp frame layout
5. rGLUE usage 0(%ebp) instead of -24(%ebp)
6. Jump table transition between instruction interpretations
instead of computed goto.
7. Change entry convention for instruction handlers:
Previously:
%bl contains 8-bit Dalvik opcode
%bh contains 2nd half of 16-bit Dalvik insn (usually AA or BA)
upper 16 bits of %ebx are zero
Now:
%bl contains 2nd half of 16-bit Dalvik insn (usually AA or BA)
upper 24 bits of %ebx are zero
8. Include copies of x86-atom macros and defines into x86 build. This
allows the x86 build to mix-and-match x86 and x86-atom handlers
via the normal config mechanism. [Note - only for non-control-flow
instructions. There are still some conflicts in the footer.S
main loop re-entry points].
Change-Id: Ib9d549b56f7ffd7420f9dbf97b2169f65603ee83
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| f6c387128427e121477c1b32ad35cdcaa5101ba3 |
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04-Mar-2009 |
The Android Open Source Project <initial-contribution@android.com> |
auto import from //depot/cupcake/@135843
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| f72d5de56a522ac3be03873bdde26f23a5eeeb3c |
|
04-Mar-2009 |
The Android Open Source Project <initial-contribution@android.com> |
auto import from //depot/cupcake/@135843
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| 89c1feb0a69a7707b271086e749975b3f7acacf7 |
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18-Dec-2008 |
The Android Open Source Project <initial-contribution@android.com> |
Code drop from //branches/cupcake/...@124589
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