| af2ea2a4fb785652ec79dbe179c499823ea45f63 |
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31-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 3f1de26cb5cc0543a6a1d71259a7a39d97139051 |
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31-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Use SchedModel enum for is{Trans,Vector}Only functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 58d3335cb9d2a40bd15c29a12ba045163295190e |
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23-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()
This increases the number of opportunites we have for folding. With the
previous implementation we were unable to fold into any instructions
other than the first when multiple instructions were selected from a
single SDNode.
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 8f9fbd67c3f803f7397843fdf4b2a7b7ca10189e |
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29-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Support schedule and packetization of trans-only inst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 7d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8 |
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29-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Bank Swizzle now display SCL equivalent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| e3d4cbc7d25061441adafa47450a31571c87bf85 |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| cedcfee405a22b245e869abe8609f094df34085a |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for GROUP_BARRIER instruction
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0 |
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25-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Use new getNamedOperandIdx function generated by TableGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 3ff0abfaabc2c7f604d490be587b9c27e7c91ac0 |
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07-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Rework subtarget info and remove AMDILDevice classes
This should simplify the subtarget definitions and make it easier to
add new ones.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| e67a4afb5da59c02338622eea68e096ba143113f |
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05-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Const/Neg/Abs can be folded to dot4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 4ed9917147b1d1f2616f7c941bbe6999b979f510 |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Relax some vector constraints on Dot4.
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 25c209e9a262b623deca60fb6b886907e22c941b |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Some factorization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| abcde265b1f8f8d29a4542bfd87ee6f8fb1537a0 |
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30-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 631591e6f3e5119d8a8b1c853279bc4ac7ace4a0 |
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30-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| dae2a20a56b28b4685249982a80a0043b7673e09 |
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03-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Factorize maximum alu per clause in a single location
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 3ab0ba3cd8a499ebcc7eda3d7585c5ab4e7f0711 |
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14-Mar-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Factorize code handling Const Read Port limitation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8 |
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06-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Support for indirect addressing v4
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| 58a2cbef4aac9ee7d530dfb690c78d6fc11a2371 |
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02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.
Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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| f98f2ce29e6e2996fa58f38979143eceaa818335 |
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11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrInfo.h
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