| 3406d882c02a6cd1e16f4636351c23dcb68d785f |
|
07-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add more special cases for opcodes to ensureSRegLimit()
Also factor out the register class lookup to its own function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 8cd70d3a5bbc5c2b02d288337748a4fd5ddc9f54 |
|
01-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Custom lower i64 ZERO_EXTEND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 73e44d8ae4c227af92b8f96f447e4a7ed38f6de5 |
|
25-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Report unaligned memory accesses as legal for > 32-bit types
In reality, some unaligned memory accesses are legal for 32-bit types and
smaller too, but it all depends on the address space. Allowing
unaligned loads/stores for > 32-bit types is mainly to prevent the
legalizer from splitting one load into multiple loads of smaller types.
https://bugs.freedesktop.org/show_bug.cgi?id=65873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| b5632b5b456db647b42239cbd4d8b58c82290c4e |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| e5fcc0dee4b41658986047f346201ad98757e7d5 |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for work item and work group intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| e86f9d70ca29429ea83bc2361cf908dc566783af |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Custom lower i64 sign_extend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 17e8ad67f0ba5e81e53ce21cd260fe3368d6231d |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Adjust some instructions' out register class after ISel
This is necessary to avoid generating VGPR to SGPR copies in some
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 4956bc61e1c86e781fd8abe14431c121d960d65b |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Rework MUBUF store instructions
The lowering of stores is now mostly handled in the tablegen files. No
more BUFFER_STORE nodes I generated during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 9bf4590aaa26ebb5afdbec079daeee8e0b268b47 |
|
20-May-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Make fitsRegClass() operands const
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 4d0e8a8a3e2e5b98f598acad4d57452b99d52e74 |
|
10-Apr-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: dynamical figure out the reg class of MIMG
Depending on the number of bits set in the writemask.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 84a775d8e3d5a3765e01db4b454f849ed8be99be |
|
10-Apr-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: adjust writemask to only the used components
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 17ea10cb792832c99677afa13b9b866098bc4679 |
|
06-Apr-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for buffer stores v2
v2:
- Use the ADDR64 bit
Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 03cd75eedb8d26847464e4fdb815e4ca2a556676 |
|
26-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: replace WQM intrinsic
Just enable WQM when we see an LDS interpolation instruction.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| b87082228bb5151598addcf0eb3756cf0f906ab6 |
|
18-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add shl pattern
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| cc22640c4c8f0bc5d1e37b4ddcdf9e7c873e4383 |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: rework input interpolation v2
v2: update CMakeLists.txt as well
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| ff408c07282309a8a3d4daca7c7e127d2fce01ed |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: remove SGPR address space v2
v2: fix R600 regressions
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 90c64cbaa124e0e8541680efeaa56f0e6eb78d9a |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add proper formal parameter handling for SI
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| d3b5509b8099b72104bd8a0d9a998a69eb56ab2a |
|
26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add post ISel folding for SI v2
Include immediate folding and SGPR limit handling for VOP3 instructions.
v2: remove leftover hasExtraSrcRegAllocReq
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| c018ecac2f2f475b6e1023e90d0e48fcf9bd6e1d |
|
26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add folding helper
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 1fbb3b3ce5629b22129a47c83bc84e2d783dde57 |
|
21-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: replace SI_V_CNDLT with a pattern
It actually fixes quite a bunch of piglit tests.
This is a candidate for the mesa-stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| e9ba1830df2efef3da113a740909195e839ebd36 |
|
16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
v3: revert setting special classes as not allocateable
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 01115b1f5032b848659669b161af1bdd9e646208 |
|
14-Feb-2013 |
Michel Danzer <michel.daenzer@amd.com> |
R600/SI: Fix int_SI_fs_interp_constant
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter
slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and
add a special operand class for the parameter slots for type checking and
pretty printing.
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 82d3d4524f2595b2dce617e963b6d67876b4f9ba |
|
18-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Proper insert S_WAITCNT instructions
Some instructions like memory reads/writes are executed
asynchronously, so we need to insert S_WAITCNT instructions
to block before accessing their results. Previously we have
just inserted S_WAITCNT instructions after each async
instruction, this patch fixes this and adds a prober
insertion pass.
Patch by: Christian König
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 935a91540b7aa8f29ea48fe2df657db0ce5b7d5d |
|
18-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Optimize and cleanup KILL on SI
We shouldn't insert KILL optimization if we don't have a
kill instruction at all.
Patch by: Christian König
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| 6b7d99d47321ebb478b22afd2e317fe89d2149db |
|
19-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
R600: New control flow for SI v2
This patch replaces the control flow handling with a new
pass which structurize the graph before transforming it to
machine instruction. This has a couple of different advantages
and currently fixes 20 piglit tests without a single regression.
It is now a general purpose transformation that could be not
only be used for SI/R6xx, but also for other hardware
implementations that use a form of structurized control flow.
v2: further cleanup, fixes and documentation
Patch by: Christian König
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|
| f98f2ce29e6e2996fa58f38979143eceaa818335 |
|
11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.h
|