| fab2daa4a1127ecb217abe2b07c1769122b6fee1 |
|
08-Aug-2013 |
Stephen Hines <srhines@google.com> |
Merge commit '10251753b6897adcd22cc981c0cc42f348c109de' into merge-20130807
Conflicts:
lib/Archive/ArchiveReader.cpp
lib/Support/Unix/PathV2.inc
Change-Id: I29d8c1e321a4a380b6013f00bac6a8e4b593cc4e
|
| 207600d2cfa2b06bfeb0c1670f198f1aa1a1aa58 |
|
07-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512 set: Added BROADCAST instructions
with lowering logic and a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b19982c42b119ffc269e4913cbf9b047629fb72f |
|
07-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Simplify code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d113448c1dd5f40522c3c02db96e87a9eb59eaf4 |
|
06-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:
define i64 @test1(i64 %val) {
%in = trunc i64 %val to i32
tail call i32 @ret32(i32 returned %in)
ret i64 %val
}
define i64 @test2(i64 %val) {
tail call i32 @ret32(i32 returned undef)
ret i32 42
}
should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.
For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
call.
Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).
This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.
Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5923547e2a143292c252adf9c9f23786eb25539a |
|
06-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Simplify vector lane handling math a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 57bc5a0b5bb7dbfd461e630370d2c18fbbfbaad4 |
|
06-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Simplify math a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aa0f420567240fda76a57c25cdfd8d49376c0e76 |
|
06-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Replace EVT with MVT in isHorizontalBinOp as it is only called with legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 20b46b0733e0eaac5ae3c9ac5e5c36cd9f52ffdf |
|
06-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Simplify code slightly. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a37c7e9e6059f7b5cfffce8917a49c0810d5a18 |
|
05-Aug-2013 |
Aaron Ballman <aaron@aaronballman.com> |
Silencing an MSVC11 type conversion warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 13e6e9171f79a481d7f814aad958460dfd867c71 |
|
05-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.
Added intrinsics and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 75311b7b4dbb284e7539c0c62331387f3c4cd1ec |
|
04-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Turn fp selects into mask operations.
double test(double a, double b, double c, double d) { return a<b ? c : d; }
before:
_test:
ucomisd %xmm0, %xmm1
ja LBB0_2
movaps %xmm3, %xmm2
LBB0_2:
movaps %xmm2, %xmm0
after:
_test:
cmpltsd %xmm1, %xmm0
andpd %xmm0, %xmm2
andnpd %xmm3, %xmm0
orpd %xmm2, %xmm0
Small speedup on Benchmarks/SmallPT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a54b66277e5d4bdd55825eb9378f07334692020c |
|
04-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
X86: correct tail return address calculation
Due to the weird and wondeful usual arithmetic conversions, some
calculations involving negative values were getting performed in
uint32_t and then promoted to int64_t, which is really not a good
idea.
Patch by Katsuhiro Ueno.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0780179d532d20b6b01ba0f1434c93f81b7faea8 |
|
01-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
EVEX and compressed displacement encoding for AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 093043ce11edcf516fd6de468bafc0d9f9ac0ea0 |
|
31-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Fixed assertion in Extract128BitVector()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8395251c0a1f16531e7f4d11a766a4a1e3d25520 |
|
31-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added INSERT and EXTRACT intructions from AVX-512 ISA.
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 944061c4e152e9f66ffaaca5905253ba8012a4fa |
|
29-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Proper va_arg/va_copy lowering on win64
Win64 uses CharPtrBuiltinVaList instead of X86_64ABIBuiltinVaList like
other 64-bit targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 320185fa5f5838b3892962f6e91083e9729cd946 |
|
26-Jul-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
Add a target legalize hook for SplitVectorOperand (again)
CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.
This also adds a test case for NVPTX that depends on this custom
legalization.
Differential Revision: http://llvm-reviews.chandlerc.com/D1195
Attempt to fix the buildbots by making the X86 test I just added platform independent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c735c1c2aed2cbaeb61296f4269535b5d13d8b0a |
|
26-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "Add a target legalize hook for SplitVectorOperand"
This reverts commit 187198. It broke the bots.
The soft float test probably needs a -triple because of name differences.
On the hard float test I am getting a "roundss $1, %xmm0, %xmm0", instead of
"vroundss $1, %xmm0, %xmm0, %xmm0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5a24ed951b7f5e553a7e4e1415da5be247db443e |
|
26-Jul-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
Add a target legalize hook for SplitVectorOperand
CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.
This also adds a test case for NVPTX that depends on this custom
legalization.
Differential Revision: http://llvm-reviews.chandlerc.com/D1195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e3809eed34f000581a464689596eefde2a6d1f24 |
|
24-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
I'm starting to commit KNL backend. I'll push patches one-by-one. This patch includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31.
The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b95e0f6f2f43d2c9ae8dd9407f9216d02fa4c833 |
|
16-Jul-2013 |
Juergen Ributzka <juergen@apple.com> |
[X86] Use min/max to optimze unsigend vector comparison on X86
Use PMIN/PMAX for UGE/ULE vector comparions to reduce the number of required
instructions. This trick also works for UGT/ULT, but there is no advantage in
doing so. It wouldn't reduce the number of instructions and it would actually
reduce performance.
Reviewer: Ben
radar:5972691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da129a2eb3c248384aa60eb2d59f14b2e877e098 |
|
15-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Add 'static' keyword to some const arrays for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
|
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fff967358b56c4e191089f668b75ae415b5bd992 |
|
12-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when possible
Patch by Andrea Di Biagio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ac226bbf457f6b5e5210a4a82b1ce678298b2d89 |
|
12-Jul-2013 |
Charles Davis <cdavis5x@gmail.com> |
Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.
Summary:
This patch adds explicit calling convention types for the Win64 and
System V/x86-64 ABIs. This allows code to override the default, and use
the Win64 convention on a target that wants to use SysV (and
vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU
attributes.
Reviewers:
CC:
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e54885af9b54bfc7436a928a48d3db1ef88a2a70 |
|
09-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4010110ccf21be0517034b6ccf9493628afaad77 |
|
08-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Reuse %rax after calling __chkstk on win64
Reapply this as I reverted the wrong commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 63e7778b53a1c8c190d5c67a9e8871c2acb00b26 |
|
08-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Revert "Proper va_arg/va_copy lowering on win64"
This reverts commit 2b52880592a525cfe04d8f9008a35da8c2ea94c3.
Needs review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d56e7e198d858439c884dbd909ee58d15742d5be |
|
08-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Revert "Reuse %rax after calling __chkstk on win64"
This reverts commit 01f8d579f7672872324208ac5bc4ac311e81b22e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 01f8d579f7672872324208ac5bc4ac311e81b22e |
|
07-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Reuse %rax after calling __chkstk on win64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2b52880592a525cfe04d8f9008a35da8c2ea94c3 |
|
06-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Proper va_arg/va_copy lowering on win64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 365ef0b197d7c841f8e501da64296df65be4ca23 |
|
03-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87070fe1073b1e95748d987af0810d02aac43603 |
|
26-Jun-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
|
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1878f9a7874b1ff569d745c0269f49d3daf7203d |
|
12-Jun-2013 |
Stephen Hines <srhines@google.com> |
Merge commit '100fbdd06be7590b23c4707a98cd605bdb519498' into merge_20130612
|
| a5e5ba611f787f518fd3f7349343f8c4ae863fc2 |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 |
|
30-May-2013 |
Andrew Trick <atrick@apple.com> |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
|
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 23d1d5eb566dbd10a81d9ce2dc67ad1548110b08 |
|
22-May-2013 |
Nadav Rotem <nrotem@apple.com> |
X86: Fix a bug in EltsFromConsecutiveLoads. We can't generate new loads without chains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 60ef6c9295844038406c6083b67ea24b3646f2dd |
|
22-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned.
Take #2 on fixing PR15977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f106d8bad6ba3759e512e1a1e6cc09ce832bd74e |
|
21-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type.
Otherwise we'll get a mix of signed and unsigned compares.
Fixes PR15977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a0de26ce34877fac86ef6d939d56bbebb3b4e14c |
|
17-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Make shuffle -> shift conversion more aggressive about undefs.
Shuffles that only move an element into position 0 of the vector are common in
the output of the loop vectorizer and often generate suboptimal code when SSSE3
is not available. Lower them to vector shifts if possible.
We still prefer palignr over psrldq because it has higher throughput on
sandybridge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 526f3ed7da88aa02bed42fe2238a60e3be64446b |
|
05-May-2013 |
David Majnemer <david.majnemer@gmail.com> |
Remove a recently redundant transform from X86ISelLowering.
X86ISelLowering has support to treat:
(icmp ne (and (xor %flags, -1), (shl 1, flag)), 0)
as if it were actually:
(icmp eq (and %flags, (shl 1, flag)), 0)
However, r179386 has code at the InstCombine level to handle this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0fb6523eae0ad24c1bb60f19c2008656d807e51a |
|
05-May-2013 |
Nadav Rotem <nrotem@apple.com> |
Fix an odd comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 38578c4919ea18ceb27e29988b2d857afe6215bf |
|
03-May-2013 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/master' into merge-20130502
Conflicts:
lib/Support/Unix/Signals.inc
unittests/Transforms/Utils/Cloning.cpp
Change-Id: I027581a4390ec3ce4cd8d33da8b5f4c0c7d372c8
|
| 299eb2e6e15f0df73ce6202849fd2b4f0713cc1f |
|
02-May-2013 |
Michael Liao <michael.liao@intel.com> |
80-col fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| db7da200a40e9496809b4981443150dd481e1814 |
|
02-May-2013 |
Michael Liao <michael.liao@intel.com> |
Avoid duplicating logic on frame register selecting when lowering eh_return
No functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b9cca1306303cc267ee629662e6352797590d731 |
|
02-May-2013 |
Michael Liao <michael.liao@intel.com> |
Avoid duplicating logic on frame register selecting when lowering frameaddr
No functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180912 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8b71994fde0f0fcdf7a8260dc773fb7376b1231f |
|
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused ShouldFoldAtomicFences flag.
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6265d5c91a18b2fb6499eb581c488315880c044d |
|
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 |
|
20-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0ee17006b1b65204ab95360b98d04304bf206c59 |
|
19-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
Use 'array_lengthof' as possible to avoid magic numbers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fcba22decb8f44ff9aa8807f275ca3a32589fba0 |
|
18-Apr-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't available.
This pattern started popping up in vectorized min/max reductions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf53841cfe3c341ebc0fca102d641c2018855254 |
|
11-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
Optimize vector select from all 0s or all 1s
As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane,
vector select could be simplified to AND/OR or removed if one or both values
being selected is all 0s or all 1s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 959ddbb5e0e088f4d5c3f8c015de3caf0baa6e6c |
|
11-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
Enhance bool simplifcation in X86 to handle more cases
This patch is revised based on patch from Victor Umansky
<victor.umansky@intel.com>. More cases are handled in X86's bool
simplification, i.e.
- SETCC_CARRY
- value is truncated to i1 with AND
As a by-product, PR5443 is also fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3a6b7d38a7c41189b75f0d40a92700aa42cc6a91 |
|
10-Apr-2013 |
Evan Cheng <evan.cheng@apple.com> |
__sincosf_stret returns sinf / cosf in bits 0:31 and 32:63 of xmm0, not in
xmm0 / xmm1.
rdar://13599493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 13bbe1f52e8d57151e2730db49094e1c62a4c793 |
|
05-Apr-2013 |
Bill Wendling <isanbard@gmail.com> |
Use the target options specified on a function to reset the back-end.
During LTO, the target options on functions within the same Module may
change. This would necessitate resetting some of the back-end. Do this for X86,
because it's a Friday afternoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b8f0d89d0584e37e205c04ed5753f57a23365403 |
|
31-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.
A vector sext + sitofp is a lot cheaper than 8 scalar conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 74a4533a4290b7c6f1fe04a30ca13ec25c529e0a |
|
29-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c26392aa5d9c2dbca2909d6874d181455f8aeb8f |
|
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 258d9b7bc021ebc78f5a3aef3907e225e632edfa |
|
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Enhance boolean simplification to handle 16-/64-bit RDRAND
- RDRAND always clears the destination value when a random value is not
available (i.e. CF == 0). This value is truncated or zero-extended as
the false boolean value to be returned. Boolean simplification needs
to skip this 'zext' or 'trunc' node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 816f6d0ac76c0ffb2ea9ecb72349d5d7d0fa8d1a |
|
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Skip moving call address loading into callseq when targets prefer register indirect call.
To enable a load of a call address to be folded with that call, this
load is moved from outside of callseq into callseq. Such a moving
adds a non-glued node (that load) into a glued sequence. This non-glue
load is only removed when DAG selection folds them into a memory form
call instruction. When such instruction selection is disabled, it breaks
DAG schedule.
To prevent that, such moving is disabled when target favors register
indirect call.
Previous workaround disabling CALL32m/CALL64m insn selection is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a46f82dbf94e970f6e61b56a7da8bb19d217f31a |
|
28-Mar-2013 |
Timur Iskhodzhanov <timurrrr@google.com> |
Make Win32 put the SRet address into EAX, fixes PR15556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1edadea42f6f5c393b4fdb9d7ce1cf7eb9c24ab4 |
|
27-Mar-2013 |
Preston Gurd <preston.gurd@intel.com> |
For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.
This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.
Patch by Sriram Murali.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e915047fed99221afb8c540d8a7e81038a6483f1 |
|
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix typo (common to both X86 and PPC)
Thanks to Bill Schmidt for pointing this out during code review!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f8fd883fd368316ad3738dad6c15b1b8f3850f88 |
|
26-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add XTEST codegen support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d4584c9e5658887ec50c43760c988d04eaa13e34 |
|
26-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Revise alignment checking/calculation on 256-bit unaligned memory access
- It's still considered aligned when the specified alignment is larger
than the natural alignment;
- The new alignment for the high 128-bit vector should be min(16,
alignment) as the pointer is advanced by 16, a power-of-2 offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 42317ccb5fed9de14118e1c48417b814d94e3d28 |
|
20-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR15296
- Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering
to support extended 256-bit integer in AVX but not AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5c5f1908f0abd187620d3fc660bf74fe6a8c531b |
|
20-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Mark all variable shifts needing customizing
- Prepare moving logic from DAG combining into DAG lowering. There's no
functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4b7ab12d93f5677d7ee8d4f6955bcfe52c22daca |
|
20-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Move scalar immediate shift lowering into a dedicated func
- no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b05130e1b20ed17ae9d5ab3351933babd27213e1 |
|
19-Mar-2013 |
Nadav Rotem <nrotem@apple.com> |
Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.
Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2d4629c5d7dcc6582fa7b85a517744f1a3654eba |
|
19-Mar-2013 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge_2013_03_18
|
| 2ee4e428ccf2bfc5bc4cd14b8f344350d95f4cda |
|
18-Mar-2013 |
Anton Korobeynikov <asl@math.spbu.ru> |
TLS support for MinGW targets.
MinGW is almost completely compatible to MSVC, with the exception of the _tls_array global not being available.
Patch by David Nadlinger!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f8c6852a08df9d41f4e0242624ec744cd7e0d2f |
|
14-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR15309
- Fix the typo on type checking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ef5383b3537a420c5e2ab3e657c378e5185549d |
|
08-Mar-2013 |
Tom Stellard <thomas.stellard@amd.com> |
DAGCombiner: Use correct value type for checking legality of BR_CC v3
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.
v2:
- Expand more BR_CC value types for NVPTX
v3:
- Expand correct BR_CC value types for Hexagon, Mips, and XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 02c2ecf9f166522cc1c58dd484668c1cbacc0c6e |
|
07-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.
That can usually be lowered efficiently and is common in sandybridge code.
It would be nice to do this in DAGCombiner but we can't insert arbitrary
BUILD_VECTORs this late.
Fixes PR15462.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fe9dbe0066ba4a35cb68fb281e6f6649ffa85ae9 |
|
07-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix two remaining issue after fixing PR15355 when CMOV is not available
- Phi nodes should be replaced/updated after lowering CMOV into branch
because 'mainMBB' updating operand in Phi node is changed.
- Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as
we will reuse the EFLAGS generated before the 1st lowered CMOV, which
won't clobber EFLAGS. However, we need explicitly specify that.
- '-attr=-cmov' test case are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5adb136be579e8fff3734461580cb34d1d2983b8 |
|
06-Mar-2013 |
Stephen Hines <srhines@google.com> |
Merge commit 'b3201c5cf1e183d840f7c99ff779d57f1549d8e5' into merge_20130226
Conflicts:
include/llvm/Support/ELF.h
lib/Support/DeltaAlgorithm.cpp
Change-Id: I24a4fbce62eb39d924efee3c687b55e1e17b30cd
|
| c537f79dcd9d91577b8e0a41c11f68b628d73af4 |
|
06-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR15355
- Clear 'mayStore' flag when loading from the atomic variable before the
spin loop
- Clear kill flag from one use to multiple use in registers forming the
address to that atomic variable
- don't use a physical register as live-in register in BB (neither entry
nor landing pad.) by copying it into virtual register
(patch by Cameron Zwarich)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9a2cfffdb6340c54ff553c1b81364d0f17fa8f45 |
|
04-Mar-2013 |
Preston Gurd <preston.gurd@intel.com> |
Bypass Slow Divides
* Only apply divide bypass optimization when not optimizing for size.
* Fixed bug caused by constant for 0 value of type Int32,
used dividend type to generate the constant instead.
* For atom x86-64 apply the divide bypass to use 16-bit divides instead of
64-bit divides when operand values are small enough.
* Added lit tests for 64-bit divide bypass.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a6b20ced765b67a85d9219d0c8547fc9c133e14f |
|
01-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
but TLI.getShiftAmountTy() so far only return scalar type. As a
result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
return target-specificed scalar type or the same vector type as the
1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d09318f9013aad79d7872de2ba490734b597f4d4 |
|
26-Feb-2013 |
Michael Liao <michael.liao@intel.com> |
Refine fix to PR10499, no functionality change
- Put expensive checking after simple one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5e6e15caa79c30e155665e58b81540ec15e52051 |
|
26-Feb-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR10499
- Check whether SSE is available before lowering all 1s vector building with
PCMPEQD, which is only available from SSE2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f8db4478f80ef63cf51518affc7b97c9d310bc23 |
|
24-Feb-2013 |
Nadav Rotem <nrotem@apple.com> |
Revert r169638 because it broke Mesa llvmpipe tests.
Fix PR15239.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3450f800aa65c91f0496816ba6061a422a74c1fe |
|
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52981c4b6016d9f0e295e0771ec0a50dd073b4b3 |
|
20-Feb-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
I optimized the following patterns:
sext <4 x i1> to <4 x i64>
sext <4 x i8> to <4 x i64>
sext <4 x i16> to <4 x i64>
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.
I also added a cost of this operations to the AVX costs table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ff3139fe53fdc391972bb0ff4d7bde6ced2f5d5a |
|
19-Feb-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix capitalization in comment to match function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 56f58ad0e415fcc390cdd4f891e6bf936f0dcf53 |
|
19-Feb-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Use array_pod_sort instead of std::sort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 30fcfc39e2abdb7765c282e8c9d4c63c3d4f83b1 |
|
16-Feb-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Minor cleanups. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b39a5529496a9824831c78e9e7249c062a4b754a |
|
14-Feb-2013 |
Nadav Rotem <nrotem@apple.com> |
80-col
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 60b3e18d674489364b6448d376ff6666f106c1fc |
|
14-Feb-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 48aaf5fd02bbdcde0935929f0c5bf08b1f8f20b8 |
|
13-Feb-2013 |
Nick Lewycky <nicholas@mxc.ca> |
Don't build tail calls to functions with three inreg arguments on x86-32 PIC.
Fixes PR15250!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 23571f4f2c895d60c9ed23b831f988b49a55478e |
|
13-Feb-2013 |
Eric Christopher <echristo@gmail.com> |
Check i1 as well as i8 variables for 8 bit registers for x86 inline
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c3afc760e1a49f29634b7442a3d38bc88a1f113e |
|
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move MRI liveouts to X86 return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a220aeb58f30a6b3fc991883e8107d5e1198c53b |
|
04-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Open up some opportunities for constant folding by postponing shift lowering.
Fixes PR15141.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9fa9251bbad191feb52273b0f3d44531a5fd78a0 |
|
04-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174326 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e187e259963466cc106b8a23c0d5b4d44fdd15a6 |
|
31-Jan-2013 |
Eric Christopher <echristo@gmail.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a9bd4b4647694f1384a8e1c891931ba7bdff364f |
|
31-Jan-2013 |
Eric Christopher <echristo@gmail.com> |
Check and allow floating point registers to select the size of the
register for inline asm. This conforms to how gcc allows for effective
casting of inputs into gprs (fprs is already handled).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a66f40a8cc685b2869e7f8d988f9a17439875ece |
|
30-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Restrict sin/cos optimization to 64-bit only for now. 32-bit is a bit messy and less critical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b5a14d59d827166d1fea5368060c7462d8f1db1 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4aee1bb2223e59efb814a694edaecd07a3418da0 |
|
28-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 200b306f2006533a0e7a0ca75cb3103620e7aa84 |
|
26-Jan-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Decode PALIGN operands so I don't have to do it in my head.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 11f2bf7f15a7d3b3df500f3f3e76355c888c23c7 |
|
26-Jan-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Do splat promotion later, so the optimizer can chew on it first.
This catches many cases where we can emit a more efficient shuffle for a
specific mask or when the mask contains undefs. Once the splat is lowered to
unpacks we can't do that anymore.
There is a possibility of moving the promotion after pshufb matching, but I'm
not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so
I avoided that for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a5597f0eaf1f93c6d0bc641a0cc54ecffb33955a |
|
25-Jan-2013 |
Eli Bendersky <eliben@google.com> |
In this patch, we teach X86_64TargetMachine that it has a ILP32
(defined by the x32 ABI) mode, in which case its pointers are 32-bits
in size. This knowledge is also added to X86RegisterInfo that now
returns the appropriate registers in getPointerRegClass.
There are many outcomes to this change. In order to keep the patches
separate and manageable, we start by focusing on some simple testable
cases. The patch adds a test with passing a pointer to a function -
focusing on the difference between the two data models for x86-64.
Another test is added for handling of 'sret' arguments (and
functionality is added in X86ISelLowering to make it work).
A note on naming: the "x32 ABI" document refers to the AMD64
architecture (in LLVM it's distinguished by being is64Bits() in the
x86 subtarget) with two variations: the LP64 (default) data model, and
the ILP32 data model. This patch adds predicates to the subtarget
which are consistent with this naming scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 13d08bf4159d8ffb780bb2e29a03763c17543001 |
|
22-Jan-2013 |
Michael Liao <michael.liao@intel.com> |
Fix an issue of pseudo atomic instruction DAG schedule
- Add list of physical registers clobbered in pseudo atomic insts
Physical registers are clobbered when pseudo atomic instructions are
expanded. Add them in clobber list to prevent DAG scheduler to
mis-schedule them after these insns are declared side-effect free.
- Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0a29cb045444c13160e90fe7942a9d7c720185ed |
|
22-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Make APFloat constructor require explicit semantics.
Previously we tried to infer it from the bit width size, with an added
IsIEEE argument for the PPC/IEEE 128-bit case, which had a default
value. This default value allowed bugs to creep in, where it was
inappropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 059800f9e3fee2852672f846d91a2da14da7783a |
|
21-Jan-2013 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/master' into merge-llvm
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/MC/MCAssembler.cpp
lib/Support/Atomic.cpp
lib/Support/Memory.cpp
lib/Target/ARM/ARMJITInfo.cpp
Change-Id: Ib339baf88df5b04870c8df1bedcfe1f877ccab8d
|
| 04f74a149d16ff92722c3c333ab36b130fd8cae7 |
|
21-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Use <0 checks in place of ==-1 because it results in simpler code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bbf9d3e4936d21c0089d2fa51da7e10910a1fb36 |
|
21-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Use MVT instead of EVT in LowerVECTOR_SHUFFLEtoBlend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b33ef7c67267d1444bf250a54053bd821b773a0 |
|
21-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b99bafe36d0c63b9febc7c620cde3663f9f7792f |
|
21-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix some 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b84b4236343727ab1cd9c1cb4e3e3a43fa69c6c2 |
|
21-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Make helper method static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a080daf5c6d9f62d021efe7c6c608a71d591dc44 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Convert more EVT's to MVT's in the lowering methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d713c0f7f1556f1ff74b3e953be5d35b614cc081 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Capitalize lowerTRUNCATE so that it matches the other lower functions in this file despite it not matching coding standards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 26827f3dc5fc2e614fb2409e5371de6132eaa8a7 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Make LowerVSETCC a static function and use MVT instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0c8607ba6a21578996a7532b9390afba13bd2087 |
|
20-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
Revert 172708.
The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends.
This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical.
Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume
that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f84b7500ce489d2e4039348ed30bf584f0b61973 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Make some helper methods static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3b2aba09e2534a23ab6c50d9f60d1d7d9ff59eb0 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove DebugLoc argument from static function. It can easily be obtained from the SVOp passed in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 45e1c758338b0b2747d76d1e47bdce7c4d75dd56 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Use MVT instead of EVT in more instruction lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 657a99c608c98bb0cad655681c1da35ddd7b1418 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Use MVT instead of EVT in more of the shuffle lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 00a312c478771941bc3e98cfbe6728465c769807 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Capitalize LowerVectorIntExtend to be consistent with all the other lower functions in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ba9586544164e69754039a25cb0ef7907d27382d |
|
19-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
On Sandybridge split unaligned 256bit stores into two xmm-sized stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cfcab21e4d0e4d7444b147898d6aed1348df3043 |
|
19-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Use MVT instead of EVT when computing shuffle immediates since they can only be for legal types. Keeps compiler from generating unneeded checks and handling for extended types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 48177ac90fb940833b9deea1a6716092348cfe82 |
|
19-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
On Sandybridge loading unaligned 256bits using two XMM loads (vmovups and vinsertf128) is faster than using a single vmovups instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5141d97d3ee9afca936bc870e67c53e1ed05f790 |
|
18-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Calculate vector element size more directly for VINSERTF128/VEXTRACTF128 immediate handling. Also use MVT since this only called on legal types during pattern matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e6d8fa7d0b4352902886930debe459b9f477303e |
|
18-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Minor formatting fix. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0a38861364c30c73b64ae8d8ef326f655d22fefd |
|
18-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Spelling fix: extened->extended. Trailing whitespace in same function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172793 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5a529e4f86bc3c76ba086662d7c4ef2d1f85ce6f |
|
18-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Make more use of is128BitVector/is256BitVector in place of getSizeInBits() == 128/256.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6c327f92a562d9d280bdbc3bde3c0ce269a4c65c |
|
17-Jan-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Optimization for the following SIGN_EXTEND pairs:
v8i8 -> v8i64,
v8i8 -> v8i32,
v4i8 -> v4i64,
v4i16 -> v4i64
for AVX and AVX2.
Bug 14865.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 13f8cf55d43980e73d6cbb8f4894607709daa311 |
|
09-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
Efficient lowering of vector sdiv when the divisor is a splatted power of two constant.
PR 14848. The lowered sequence is based on the existing sequence the target-independent
DAG Combiner creates for the scalar case.
Patch by Zvi Rackover.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aeef83c6afa1e18d1cf9d359cc678ca0ad556175 |
|
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e503319874f57ab4a0354521b03a71cf8e07b866 |
|
04-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
LoopVectorizer:
1. Add code to estimate register pressure.
2. Add code to select the unroll factor based on register pressure.
3. Add bits to TargetTransformInfo to provide the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e12bf1875481b02d07b6ce9c153ec3410068e234 |
|
04-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
Revert revision: 171467. This transformation is incorrect and makes some tests fail. Original message:
Simplified TRUNCATE operation that comes after SETCC. It is possible since SETCC result is 0 or -1.
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab7032090871abf6aeed86b2c4b836e97771d234 |
|
03-Jan-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Simplified TRUNCATE operation that comes after SETCC. It is possible since SETCC result is 0 or -1.
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 82860f63e1678077fe665c21179b9df47fd313bb |
|
03-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a subtype parameter to VTTI::getShuffleCost
In order to cost subvector insertion and extraction, we need to know
the type of the subvector being extracted.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e3b2489f4f3f28d65c0bc491a7d9e3d295f35723 |
|
02-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
AVX: Fix a bug in WidenMaskArithmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 94e94b350652d3a71993bbc7d44afbe3b304605e |
|
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Use the predicate methods off of AttributeSet instead of Attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 831737d329a727f53a1fb0572f7b7a8127208881 |
|
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 22d8f0d68519240b0936983322cfdb9c84a4ed0c |
|
29-Dec-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f57f39e4ac767c84b25973a2f517fde3d37a8dd |
|
29-Dec-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge similar functionality using a nested switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6d183e400720b703dc9dbe6c8a28b615441601a2 |
|
29-Dec-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c20323a7588bc5ad327155fe09c2b51435c3ada2 |
|
29-Dec-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Simplify code, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ae34b4280ebde6217706902e8a27bb858765a61c |
|
28-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
CostModel: initial checkin for code that estimates the cost of special shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 40ef8b75487ad9f98a93b1dbf283a25658ef8a1e |
|
28-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
wrap 80-col lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0509db27386f5cafffd364618365ecda741cf0bd |
|
28-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 587fb1dd30b73afb3c83a1e88d9ea101a0b28ab2 |
|
28-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Reverse the 'if' condition and reduce the indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a330af3b54aada0b2028cf6793d90c9e2974567 |
|
27-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d6fb53adb19ccfbfb1eedec11c899aaa8401d036 |
|
27-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.
PR14657.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3c22a444001ac3f7a89c9888d60aec69352d0e58 |
|
27-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook.
The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a05f7cbbded2a2605acfd3cd05211e6006409da0 |
|
26-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Reformat the docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 99f78061e05833e815cb7a27e6c17eadcd028ce2 |
|
25-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 382ed78d3fef9f6c582e3cdcfb30f8c6fa3d0d79 |
|
25-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.
pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71f30bffcf158ffac8c75bb67872e275b7f87e47 |
|
24-Dec-2012 |
Nick Lewycky <nicholas@mxc.ca> |
Quiet gcc's -Wparenthesis warning. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 40b04a481d4a1b53a549c99edc730e06b0b14fb4 |
|
23-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d54fed27865dcbc69932e1e6c372bb5a932e662a |
|
23-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Loop Vectorizer: Update the cost model of scatter/gather operations and make
them more expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f8a6cdfa3bc0bfa4532da89e574666c5251cdb5 |
|
22-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available.
pmuludq is slow, but it turns out that all the unpacking and packing of the
scalarized mul is even slower. 10% speedup on loop-vectorized paq8p.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 17347912b46213658074416133396caffd034e0c |
|
22-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Emit vector sext as shuffle + sra if vpmovsx is not available.
Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better
than scalarized loads. Fixes PR14590.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2556c6b4b67c4a45ad90b256d4913f2048d2fba6 |
|
21-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Match pmin/pmax as a target specific dag combine. This occurs during vectorization.
Part of PR14667.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 739c7a83e16e7daaf22cfa4ae84e8d1cc0260941 |
|
21-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics
This is very mechanical, no functionality change. Preparation for PR14667.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f5637c399711e37287e01f9d9ca9ce7cd2f3d14f |
|
21-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Improve the X86 cost model for loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e5c65911a659e49320d214bf0702793ad37b5ed5 |
|
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0340557fb830e3669c4c48a2cd99d7703bdda452 |
|
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 16537418f4309ba0ab89f6b0dbadc77014ca671f |
|
19-Dec-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4b977312c7a9c078211de83771b40a1561deb047 |
|
19-Dec-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Optimized load + SIGN_EXTEND patterns in the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 034b94b17006f51722886b0f2283fb6fb19aca1f |
|
19-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 270bfbd3d1fb42000b23e5747ac7957b0e9fcab8 |
|
18-Dec-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Reverse order of checking SSE level when calculating compare cost, so we check
AVX2 before AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b926afcc5b99030fecf496d15cffdd1315fd0ead |
|
17-Dec-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also add ANDN to isDefConvertible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 388fc6a988b56a50efff57893a4df14b4d04e1cd |
|
15-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Add a couple of target-specific dag combines that turn VSELECTS into psubus if possible.
We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases
if y is a constant. DAGCombiner canonicalizes those so we first have to undo the
canonicalization for those cases. The pattern occurs in gzip when the loop
vectorizer is enabled. Part of PR14613.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0a1e914f8f276cd854e23f7c4d21620f2dbe533c |
|
14-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
TypeLegalizer: Do not generate target specific nodes with illegal types, because we cant type-legalize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d34267df63e23be1957f738de783c145febb7af |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 61f4dfe3693bf68b20748d82ac4dd9bf2f356699 |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using lossy load / stores for memcpy / memset expansion. e.g.
f64 load / store on non-SSE2 x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 47fd10f2fc45d280308b77ed4eda16f3c9c88248 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.
Accordingly, add bitsLT (and similar) to MVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bade0345d190427a08b2b947bc94f4d8ca5d7717 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 376642ed620ecae05b68c7bc81f79aeb2065abe0 |
|
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5518a1355b8b09bf92419b65ea4e4854734b0ebc |
|
09-Dec-2012 |
Shuxin Yang <shuxin.llvm@gmail.com> |
- Re-enable population count loop idiom recognization
- fix a bug which cause sigfault.
- add two testing cases which was causing crash
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7065a2bcec3b775da12cf8fbcd6fa972d5f2afeb |
|
08-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the patches adding a popcount loop idiom recognition pass.
There are still bugs in this pass, as well as other issues that are
being worked on, but the bugs are crashers that occur pretty easily in
the wild. Test cases have been sent to the original commit's review
thread.
This reverts the commits:
r169671: Fix a logic error.
r169604: Move the popcnt tests to an X86 subdirectory.
r168931: Initial commit adding the pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 99faa3b4ec6d03ac7808fe4ff3fbf3d04e375502 |
|
08-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
s/AttrListPtr/AttributeSet/g to better label what this class is going to be in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af59e9adbd4c972d480d58260b03768c85eb2067 |
|
07-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
When we use the BLEND instruction that uses the MSB as a mask, we can remove
the VSRI instruction before it since it does not affect the MSB.
Thanks Craig Topper for suggesting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e4ccfef809a1a47f1386bb2767b8c77e64644435 |
|
07-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
X86: Prefer using VPSHUFD over VPERMIL because it has better throughput.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2766a47310b05228e9bbc536d9f3a593fc31cd12 |
|
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Replace r169459 with something safer. Rather than having computeMaskedBits to
understand target implementation of any_extend / extload, just generate
zero_extend in place of any_extend for liveouts when the target knows the
zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz).
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d3a056392b2a3e4abecaf304f9e452be6584b259 |
|
06-Dec-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Remove unneeded function, since PR8156 was fixed over a year ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169534 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b2af3a095b218700c3912574d2f1100207c0ae2c |
|
06-Dec-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a7186dbc2df4879f511b2ae6f2bce25ad37d965 |
|
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Let targets provide hooks that compute known zero and ones for any_extend
and extload's. If they are implemented as zero-extend, or implicitly
zero-extend, then this can enable more demanded bits optimizations. e.g.
define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
%tmp2 = load i16* %ptr, align 2
br label %bb2
bb2:
%tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
%cmp = icmp ult i16 %tmp3, 24
br i1 %cmp, label %bb3, label %exit
bb3:
call void @bar() nounwind
br label %exit
exit:
ret void
}
This compiles to the followings before:
push {lr}
mov r2, #0
cmp r1, #99
bhi LBB0_2
@ BB#1: @ %bb1
ldrh r2, [r0]
LBB0_2: @ %bb2
uxth r0, r2
cmp r0, #23
bhi LBB0_4
@ BB#3: @ %bb3
bl _bar
LBB0_4: @ %exit
pop {lr}
bx lr
The uxth is not needed since ldrh implicitly zero-extend the high bits. With
this change it's eliminated.
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 226e0e6264dc15ea8f26261a813eae3c17987b3b |
|
05-Dec-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Simplified BLEND pattern matching for shuffles.
Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4e5448053163e0d9c2107b240ccdb5a95c107b07 |
|
05-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Add x86 isel lowering logic to form bit test with inverted condition. e.g.
x ^ -1.
Patch by David Majnemer.
rdar://12755626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 84fca61ca5fba5c33a799d9133750b6832ddef7e |
|
29-Nov-2012 |
Shuxin Yang <shuxin.llvm@gmail.com> |
rdar://12100355 (part 1)
This revision attempts to recognize following population-count pattern:
while(a) { c++; ... ; a &= a - 1; ... },
where <c> and <a>could be used multiple times in the loop body.
TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent
instruction sequence, which need to be improved in the following commits.
Reviewed by Nadav, really appreciate!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8564dc67b5840da1633e29bade33185f4a36bb2d |
|
29-Nov-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in X86IselLowering.cpp.
The logic was not changed, only names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d642baf4be7cfed68fb8e7f326970f5797a2bdd4 |
|
26-Nov-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Normalize splat 256bit vectors with 8 elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3dcefc864ed818d8bda294694dfd26016ce8d997 |
|
21-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Mark ISD::FMA as Legal instead of custom for x86 with FMA3/FMA4. Needed so that llvm.muladd can be converted to ISD::FMA for fp_contract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dc7f174b5e049172f085ff5957f58998bdc446a4 |
|
16-Nov-2012 |
Duncan Sands <baldrick@free.fr> |
Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d577552c668b744a995c41ff0b73c68eb30d7b93 |
|
16-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 490104720db9e1e0eb9cc27e88e2d7288ac27ff0 |
|
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2dbe929685da37e904d6bb0c5a3504e1bafe348f |
|
14-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Enable SSE memory intrinsics even when stack alignment is less than 16 bytes.
The stack realignment code was fixed to work when there is stack realignment and
a dynamic alloca is present so this shouldn't cause correctness issues anymore.
Note that this also enables generation of AVX instructions for memset
under the assumptions:
- Unaligned loads/stores are always fast on CPUs supporting AVX
- AVX is not slower than SSE
We may need some tweaked heuristics if one of those assumptions turns out not to
be true.
Effectively reverts r58317. Part of PR2962.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 55de339dad047583cc426299438ac0d93f1683c3 |
|
14-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Factor out an overly replicated typecast. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2adc503f291d69763c5fc59a8e35d318ee22b77a |
|
13-Nov-2012 |
Manman Ren <mren@apple.com> |
X86: when constructing VZEXT_LOAD from other loads, makes sure its output
chain is correctly setup.
As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.
rdar://12684358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd3383fd09b93a1b2d0cebb57f22e5aaf3eaa740 |
|
12-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR14314
- Fix operand order for atomic sub, where the minuend is the value
loaded from memory and the subtrahend is the parameter specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2da3691d6d025221c901fe6d9e7e2e77f3c9c2e0 |
|
11-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Move some helper methods to being static functions in the implementation file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52ea24508368167b2ba8eb62fadcb1dcf54a0da2 |
|
10-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary subtraction and addition by 1 around a couple for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8cb8c8119af0f9e909f21e7c5743d0fb72e94e41 |
|
10-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up spacing. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8aae8ddb929cf2b528fb755ed5206d69c0d34e08 |
|
10-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify custom emitter code for pcmp(e/i)str(i/m) and make the helper functions static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9c7ae01f390b3d7c0fab562e69aba253d28a6dfb |
|
10-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b14a5f5f951bb327c28e61198e8ff7193ce3b599 |
|
09-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
indent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| be02a90de17f857ba65bbd8a11653ca1bad30adc |
|
08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dccd7f9187ca4b693358e65a5bd560688c91cc73 |
|
07-Nov-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d8eae8ba05c53f966f6d9801c3f5305a8dfbf1dd |
|
07-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Make the helper functions static. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a6fb97a49a2e6070c71d44a54c8c0c117b62255a |
|
06-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
CostModel: add another known vector trunc optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b042868c01925dae3a1032890f591f1da78b19d3 |
|
06-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Cost Model: add tables for some avx type-conversion hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 887c1fe7010d6f487ce246df6e2fc18eeb4eaa05 |
|
06-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Refactor the getTypeLegalizationCost interface. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7ae3bcca4502f79fdadbfbbb0e68c5e14cc699fa |
|
06-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
CostModel: Add tables for the common x86 compares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e010eb3041c03fb9bbdc16f036ff69a3bbad6dfa |
|
05-Nov-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Suppress signed/unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a4ab5290e6808c54aff178d465d533e4eba53feb |
|
05-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Cost Model: Normalize the insert/extract index when splitting types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e623702c22e7cee4e02332b245a417a88ae6ffff |
|
05-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Implement the cost of abnormal x86 instruction lowering as a table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b4b04c3fa0a5da15424de7818e9f72811495c65b |
|
03-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
X86 CostModel: Add support for a some of the common arithmetic instructions for SSE4, AVX and AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 426c2bf5cdd2173e4a33aea8cb92cf684a724f4b |
|
01-Nov-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the majority of the next patch in the address space series:
r165941: Resubmit the changes to llvm core to update the functions to
support different pointer sizes on a per address space basis.
Despite this commit log, this change primarily changed stuff outside of
VMCore, and those changes do not carry any tests for correctness (or
even plausibility), and we have consistently found questionable or flat
out incorrect cases in these changes. Most of them are probably correct,
but we need to devise a system that makes it more clear when we have
handled the address space concerns correctly, and ideally each pass that
gets updated would receive an accompanying test case that exercises that
pass specificaly w.r.t. alternate address spaces.
However, from this commit, I have retained the new C API entry points.
Those were an orthogonal change that probably should have been split
apart, but they seem entirely good.
In several places the changes were very obvious cleanups with no actual
multiple address space code added; these I have not reverted when
I spotted them.
In a few other places there were merge conflicts due to a cleaner
solution being implemented later, often not using address spaces at all.
In those cases, I've preserved the new code which isn't address space
dependent.
This is part of my ongoing effort to clean out the partial address space
code which carries high risk and low test coverage, and not likely to be
finished before the 3.2 release looms closer. Duncan and I would both
like to see the above issues addressed before we return to these
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a5526a9bffbd62a14d576f583c206a8a781cc2f1 |
|
01-Nov-2012 |
Shuxin Yang <shuxin.llvm@gmail.com> |
(For X86) Enhancement to add-carray/sub-borrow (adc/sbb) optimization.
The adc/sbb optimization is to able to convert following expression
into a single adc/sbb instruction:
(ult) ... = x + 1 // where the ult is unsigned-less-than comparison
(ult) ... = x - 1
This change is to flip the "x >u y" (i.e. ugt comparison) in order
to expose the adc/sbb opportunity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c5c970ee852e345ded08cdfc33c4621ca76211b1 |
|
31-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Clean up redundant SP register maintained in X86 TLI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c74a956b2621bb7bb1df0b2f7571060eb095464 |
|
30-Oct-2012 |
Manman Ren <mren@apple.com> |
X86 MMX: optimize transfer from mmx to i32
We used to generate a store (movq) + a load.
Now we use movd.
rdar://9946746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a24262a0f5c54f59e3362dd8a050589c508c9923 |
|
30-Oct-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Re-commit r166971. I reverted it to quickly, when buildbots didn't have a chance
to test it with chapni's fix (-mattr=+avx).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c1ed096b6b34c5f9af1a856aef5978144b20f31e |
|
30-Oct-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Revert r166971. It causes buildbot failure. To be investigated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eb90295cbaf38869eae8ffe1217cb5229796bc9a |
|
29-Oct-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 96df437a03d840fc0eff509b3b79b4cace64a915 |
|
29-Oct-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6d317824a5e8b4c5d8dc18e9e2ec365e5a1b515e |
|
29-Oct-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Allow to fold vector load if there is more than one bitcast, so in the case:
%0 = load <8 x i16>* %dest
%1 = shufflevector <8 x i16> %0, <8 x i16> %in,
<8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
store <8 x i16> %1, <8 x i16>* %dest
We get:
vmovlpd (%eax), %xmm0, %xmm0
instead of:
vmovaps (%eax), %xmm1
vmovsd %xmm1, %xmm0, %xmm0
No extra test-case is added. I just fixed the existing one
(also it uses FileCheck now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 34739054ec9e192f38cd342bd75046f5227d0165 |
|
29-Oct-2012 |
Duncan Sands <baldrick@free.fr> |
Silence a GCC warning about comparing signed and unsigned types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aa3c2c09d9d5bc67c6ca2fbc6697257b15476684 |
|
25-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Clean up where SlotSize should be used instead of pointer size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 991b6a22b6592b56ae890f30c478f835480e7cf5 |
|
24-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add custom conversion from v2u32 to v2f32 in 32-bit mode
- As there's no 64-bit GPRs in 32-bit mode, a custom conversion from v2u32 to
v2f32 is added to improve the efficiency of the code generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0787274b70e718af737bd3c0f427574acd829810 |
|
23-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR14161
- Check index being extracted to be constant 0 before simplfiying.
Otherwise, retain the original sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a999de00e71aea196974f32a94999e8349970499 |
|
23-Oct-2012 |
Matt Beaumont-Gay <matthewbg@google.com> |
Silence -Wsign-compare
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a7554630e9e8967104f4183be3dfebf79ba0b1e5 |
|
23-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add custom UINT_TO_FP from v4i8/v4i16/v8i8/v8i16 to v4f32/v8f32
- Replace v4i8/v8i8 -> v8f32 DAG combine with custom lowering to reduce
DAG combine overhead.
- Extend the support to v4i16/v8i16 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d9d09600ee7ffa5e8fcaf13fa5b37c144831e6c6 |
|
23-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Enable lowering ZERO_EXTEND/ANY_EXTEND to PMOVZX from SSE4.1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 970755e5197afb42a76a24a74cd6dc17721daf50 |
|
19-Oct-2012 |
Shuxin Yang <shuxin.llvm@gmail.com> |
This patch is to fix radar://8426430. It is about llvm support of __builtin_debugtrap()
which is supposed to consistently raise SIGTRAP across all systems. In contrast,
__builtin_trap() behave differently on different systems. e.g. it raises SIGTRAP on ARM, and
SIGILL on X86. The purpose of __builtin_debugtrap() is to consistently provide "trap"
functionality, in the mean time preserve the compatibility with on gcc on __builtin_trap().
The X86 backend is already able to handle debugtrap(). This patch is to:
1) make front-end recognize "__builtin_debugtrap()" (emboddied in the one-line change to Clang).
2) In DAG legalization phase, by default, "debugtrap" will be replaced with "trap", which
make the __builtin_debugtrap() "available" to all existing ports without the hassle of
changing their code.
3) If trap-function is specified (via -trap-func=xyz to llc), both __builtin_debugtrap() and
__builtin_trap() will be expanded into the function call of the specified trap function.
This behavior may need change in the future.
The provided testing-case is to make sure 2) and 3) are working for ARM port, and we
already have a testing case for x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| facace808cc5f83067a05c4c319f98fd75336f47 |
|
19-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Lower BUILD_VECTOR to SHUFFLE + INSERT_VECTOR_ELT for X86
- If INSERT_VECTOR_ELT is supported (above SSE2, either by custom
sequence of legal insn), transform BUILD_VECTOR into SHUFFLE +
INSERT_VECTOR_ELT if most of elements could be built from SHUFFLE with few
(so far 1) elements being inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 35a5640254d38fcdf73b22a839980aaacd437092 |
|
17-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Check SSSE3 instead of SSE4.1
- All shuffle insns required, especially PSHUB, are added in SSSE3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 281ae5abf57a4d318d308c0dd1326ff65d540b78 |
|
17-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Fix setjmp on models with non-Small code model nor non-Static relocation model
- MBB address is only valid as an immediate value in Small & Static
code/relocation models. On other models, LEA is needed to load IP address of
the restore MBB.
- A minor fix of MBB in MC lowering is added as well to enable target
relocation flag being propagated into MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bedcbd433dbbba303df0ced76bec02b01b7b8f4d |
|
16-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Support v8f32 to v8i8/vi816 conversion through custom lowering
- Add custom FP_TO_SINT on v8i16 (and v8i8 which is legalized as v8i16 due to
vector element-wise widening) to reduce DAG combiner and its overhead added
in X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e26874556b04c86bc7faee342ce69b3ec496460b |
|
16-Oct-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Reapply r165661, Patch by Shuxin Yang <shuxin.llvm@gmail.com>.
Original message:
The attached is the fix to radar://11663049. The optimization can be outlined by following rules:
(select (x != c), e, c) -> select (x != c), e, x),
(select (x == c), c, e) -> select (x == c), x, e)
where the <c> is an integer constant.
The reason for this change is that : on x86, conditional-move-from-constant needs two instructions;
however, conditional-move-from-register need only one instruction.
While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase.
The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource".
Original message since r165661:
My previous change has a bug: I negated the condition code of a CMOV, and go ahead creating a new CMOV using the *ORIGINAL* condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6c0e04c823cf4034214b050e338c99a401edd2ac |
|
16-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add __builtin_setjmp/_longjmp supprt in X86 backend
- Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also
used as a light-weight replacement of setjmp/longjmp which are used to
implementation continuation, user-level threading, and etc. The support added
in this patch ONLY addresses this usage and is NOT intended to support SjLj
exception handling as zero-cost DWARF exception handling is used by default
in X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c39b15073db81d93bb629303915b7d7e5d088dc |
|
15-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f8b65aaf39d84e5576c0579c19ba9998ebb634d2 |
|
13-Oct-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Fix accidentally swapped operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 444dccecfc6c6d0dad4f400141a12f9ca76943d8 |
|
13-Oct-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Promote i8 cmov when both operands are coming from truncates of the same width.
X86 doesn't have i8 cmovs so isel would emit a branch. Emitting branches at this
level is often not a good idea because it's too late for many optimizations to
kick in. This solution doesn't add any extensions (truncs are free) and tries
to avoid introducing partial register stalls by filtering direct copyfromregs.
I'm seeing a ~10% speedup on reading a random .png file with libpng15 via
graphicsmagick on x86_64/westmere, but YMMV depending on the microarchitecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fb384d61c78b60787ed65475d8403aee65023962 |
|
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Revert 165732 for further review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f3840d2c16a4ec4c879a8ded402835746de380f8 |
|
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in the first iteration of support for llvm/clang/lldb to allow variable per address space pointer sizes to be optimized correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e0297196edbe6539e7d3269fa19f84e04dd0a9cd |
|
11-Oct-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."
It broke stage2 clang and test-suite/MultiSource/Benchmarks/mediabench/g721/g721encode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a395f4df5b6d9c2feb661091ca75be2500d07cb0 |
|
11-Oct-2012 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstrBuilder::addDisp to copy over target flags by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87255a431bc6c29ebbb606c8119597cc63981951 |
|
10-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Patch by Shuxin Yang <shuxin.llvm@gmail.com>.
Original message:
The attached is the fix to radar://11663049. The optimization can be outlined by following rules:
(select (x != c), e, c) -> select (x != c), e, x),
(select (x == c), c, e) -> select (x == c), x, e)
where the <c> is an integer constant.
The reason for this change is that : on x86, conditional-move-from-constant needs two instructions;
however, conditional-move-from-register need only one instruction.
While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase.
The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 44c2d61b6703469a95fcd2d5397c5d09a67e75c1 |
|
10-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add support for FP_ROUND from v2f64 to v2f32
- Due to the current matching vector elements constraints in
ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from
v2f32) is scalarized. Add a customized v2f32 widening to convert it
into a target-specific X86ISD::VFPROUND to work around this
constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9d796db3e746c31dbdb605510c53b3da98d71b38 |
|
10-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add alternative support for FP_ROUND from v2f32 to v2f64
- Due to the current matching vector elements constraints in ISD::FP_EXTEND,
rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening
to convert it into a target-specific X86ISD::VFPEXT to work around this
constraints. This patch also reverts a previous attempt to fix this issue by
recovering the scalarized ISD::FP_EXTEND pattern and thus significantly
reduces the overhead of supporting non-power-2 vector FP extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e61e516a51f1211c1385a3043523552f4e56003d |
|
10-Oct-2012 |
Evan Cheng <evan.cheng@apple.com> |
When expanding atomic load arith instructions, do not lose target flags. rdar://12453106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165568 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6765834754cbb3cb0f15b4b15e98c5e73fa50066 |
|
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
|
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8d662b59f075da67e663ed142ecdd58e381eee98 |
|
04-Oct-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch corrects commit 165126 by using an integer bit width instead of
a pointer to a type, in order to remove the uses of getGlobalContext().
Patch by Tyler Nowicki.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7abf67a092c0a75d6d1631766d6a8ef14e38d526 |
|
04-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add register encoding support in X86 backend
- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8f00ae6a3f8d392ce0f42a81223e479f97876d7f |
|
04-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Use new accessor methods to query for attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 471b917b265c7c657233d9b8632af344a7d6a43a |
|
04-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Clean up tailing whitespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f4d25a2c461f7a64fcc643a6ea2541e87067d036 |
|
30-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Change getX86SubSuperRegister to take an MVT::SimpleValueType rather than an EVT and add llvm_unreachable to the switches. Helps it compile to dramatically better code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c189061184925c6a8ecbb5a19e648b230a41c0e |
|
26-Sep-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the `hasFnAttr' method from Function.
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e5e8f7656a3b37c4c0c7936f78fa2586f06fbb9a |
|
25-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Add missing i64 max/min/umax/umin on 32-bit target
- Turn on atomic6432.ll and add specific test case as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b1cacc74232164a9d80ee65d20e0095b25eb74d8 |
|
25-Sep-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix an illegal tailcall opt where the callee returns a double via xmm while caller returns x86_fp80 via st0. rdar://12229511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fe87c302aa600fdac6d80349cde21e06337f8bfe |
|
21-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Add missing i8 max/min/umax/umin support
- Fix PR5145 and turn on test 8-bit atomic ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0838249a6a327ad0e1a909d1d4e2077b23b4a272 |
|
21-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Revise td of X86 atomic instructions
- Rewirte most atomic instructions in templates for both better
maintenance and future extensions, such as HLE in TSX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b118a073d7434727a4ea5a5762f54e54e72bef4f |
|
20-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Re-work X86 code generation of atomic ops with spin-loop
- Rewrite/merge pseudo-atomic instruction emitters to address the
following issue:
* Reduce one unnecessary load in spin-loop
previously the spin-loop looks like
thisMBB:
newMBB:
ld t1 = [bitinstr.addr]
op t2 = t1, [bitinstr.val]
not t3 = t2 (if Invert)
mov EAX = t1
lcs dest = [bitinstr.addr], t3 [EAX is implicit]
bz newMBB
fallthrough -->nextMBB
the 'ld' at the beginning of newMBB should be lift out of the loop
as lcs (or CMPXCHG on x86) will load the current memory value into
EAX. This loop is refined as:
thisMBB:
EAX = LOAD [MI.addr]
mainMBB:
t1 = OP [MI.val], EAX
LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
JNE mainMBB
sinkMBB:
* Remove immopc as, so far, all pseudo-atomic instructions has
all-register form only, there is no immedidate operand.
* Remove unnecessary attributes/modifiers in pseudo-atomic instruction
td
* Fix issues in PR13458
- Add comprehensive tests on atomic ops on various data types.
NOTE: Some of them are turned off due to missing functionality.
- Revise tests due to the new spin-loop generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 562b240fc5f461e536e58cde31a8204b1cfbebf4 |
|
15-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math.
This was only an issue if sse is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9aba7ea472c8a888ff11963caf0cdea0f7ba2d33 |
|
13-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Fix comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f966e4e5b344e02ddd026a628db7079b62df60e6 |
|
13-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Add wider vector/integer support for PR12312
- Enhance the fix to PR12312 to support wider integer, such as 256-bit
integer. If more than 1 fully evaluated vectors are found, POR them
first followed by the final PTEST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6c7ccaa3fd1d6e96d0bf922554b09d2b17c3b0e3 |
|
12-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
support BA + offset addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7c02284774905cc589302d32bbba2be833f261e9 |
|
12-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Indentation fixes. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 55b24054843e611e1b364e8175c7dedba8d11c86 |
|
11-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Make a bunch of lowering helper functions static instead of member functions. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1c4ad5ef4fab105f0c8af7edd026e00502fb6279 |
|
11-Sep-2012 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge-2012_09_10
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/Support/DynamicLibrary.cpp
lib/Support/LockFileManager.cpp
Change-Id: I91e94c3a7a76e19c688307c5a480a640a3bd2b7e
|
| 2de0572caec55e3779857cae0bbcd962af2e495d |
|
10-Sep-2012 |
Dmitri Gribenko <gribozavr@gmail.com> |
Remove redundant semicolons which are null statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b8150d852399f61f3fe7f6fd66edb99173de884c |
|
10-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Enhance PR11334 fix to support extload from v2f32/v4f32
- Fix an remaining issue of PR11674 as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7fdc66bf73150a33c4e7558be89126a30a63f3b6 |
|
10-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Add boolean simplification support from CMOV
- If a boolean value is generated from CMOV and tested as boolean value,
simplify the use of test result by referencing the original condition.
RDRAND intrinisc is one of such cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8100d244ff1e29c5e4cc864152c2e210dc6c4275 |
|
10-Sep-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
The VPSHUFB 256-bit instruction may be generated when one of input vector is undefined or zeroinitializer.
I've added the "zeroinitializer" case in this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 12fb5c667fea5339228e7cc184ffd3b3bcb532ea |
|
08-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163473 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cacd9d6f7974dd54e8b7a758c1fc3b69ec7c5d4b |
|
08-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163463 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4362067d7c89291efe1cbe7d08e316d9ac4ca1c7 |
|
08-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for lowering FABS of vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a1fb1d2ed7342c7e6b491a78af073b5320bc9867 |
|
08-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Set operation action for FFLOOR to Expand for all vector types for X86. Set FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4178946afba97a9a432a33ab1596f49a1ac090e7 |
|
06-Sep-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX2 optimization.
Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7859f438e198fe441abef3d2c95c1cb9517f575b |
|
06-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Remove duplicated helper function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b8d9da13fa5c1d418b66add88866a1e8fc0ecd87 |
|
06-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Use iPTR instead of i32 for extract_subvector/insert_subvector index in lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 59324297650c12a8dccf1a7ad650a9e895fdc17e |
|
06-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Stop casting away const qualifier needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2e2efd960056bbb7e4bbd843c8de55116d52aa7d |
|
04-Sep-2012 |
Preston Gurd <preston.gurd@intel.com> |
Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder, or both.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 32510207382720a97c682e098d45cb1371c48639 |
|
04-Sep-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
This patch optimizes shuffle instruction - generates 2 instructions instead of 4.
Since this specific shuffle is widely used in many workloads we have ~10% performance on them.
shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
vmovaps (%rdx), %ymm0
vshufps $8, %ymm0, %ymm0, %ymm0
vmovaps (%rcx), %ymm1
vshufps $8, %ymm0, %ymm1, %ymm1
vunpcklps %ymm0, %ymm1, %ymm0
vmovaps (%rcx), %ymm0
vmovsldup (%rdx), %ymm1
vblendps $85, %ymm0, %ymm1, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8365e9bcc2627d365d6c7b39e8b5df6e8307c510 |
|
01-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2b7a2e8833c00a484bd9d54db77959cfe31dfc8d |
|
01-Sep-2012 |
Manman Ren <mren@apple.com> |
SelectionDAG: when constructing VZEXT_LOAD from other loads, make sure its
output chain is correctly setup.
As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.
rdar://11457792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 265bcb1e5b106a7c5db2bfcfb13cceffe0c413be |
|
31-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR12359
- In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as
well as PSHUFB will zero elements with negative indices.
Patch by Sriram Murali <sriram.murali@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf4043768c6726db523f99460645842e5024fc7f |
|
31-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for converting llvm.fma to fma4 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b1bdd7d8186c738b7463756867be79a1f664b1d3 |
|
30-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Only perform DAG combine on FMAs of legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fd49821c3598e254735e7d08469fb7e9905498c6 |
|
29-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert FMA4 patterns to use target specific nodes instead of intrinsics to align with FMA3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 95c22a354df0cc860009ce1f559816a73fec9774 |
|
29-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
Add comments on the literal value used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8e48e0b1201bc80af9b43b2742529d976dbfafb0 |
|
28-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
Explicitly update the number of nodes to be traversed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dbf8b5be977b79a7abd6bbdc38561b3a5164d195 |
|
28-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR12312
- Add a target-specific DAG optimization to recognize a pattern PTEST-able.
Such a pattern is a OR'd tree with X86ISD::OR as the root node. When
X86ISD::OR node has only its flag result being used as a boolean value and
all its leaves are extracted from the same vector, it could be folded into an
X86ISD::PTEST node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1d90bbba147e6746977b63a9c533ebdb8a93d798 |
|
27-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove MMX shift intrinsic handling code that also exists in SelectionDAGBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0e292376d09223d791ed2ccc8935e98cbd36f1f8 |
|
24-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Custom lower FMA intrinsics to target specific nodes and remove the patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162534 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 31675153bd2d7617db8cb6aeb58054934c7b9f73 |
|
24-Aug-2012 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge_2
Conflicts:
lib/Target/ARM/ARMCodeEmitter.cpp
Change-Id: I6702d340c733e9721499b5d85b13b96ad9c14eb5
|
| 24438b83595dd243e4562912750ef15438787a42 |
|
20-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
fix a case where all operands of BUILD_VECTOR are undefined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d60cb11afd709b9f84c58d8335cbc08ad912b236 |
|
19-Aug-2012 |
Nadav Rotem <nrotem@apple.com> |
When unsafe math is used, we can use commutative FMAX and FMIN. In some cases
this allows for better code generation.
Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and
FMINC, which are commutative.
For example:
movaps %xmm0, %xmm1
movsd LC(%rip), %xmm0
minsd %xmm1, %xmm0
becomes:
minsd LC(%rip), %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b9d6b8449d245ee1607f6f197b29befbf8c41a1e |
|
18-Aug-2012 |
Nadav Rotem <nrotem@apple.com> |
Reapply r162160 with a fix: Optimize Arith->Trunc->SETCC sequence to allow better compare/branch code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| acaaa6fae659be7a064ef832775d1a73357dd7b4 |
|
18-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Refactor code a bit to reduce number of calls in the final compiled code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d5c66a0b1ff3cffc2c1dee7301bd36961af54efa |
|
18-Aug-2012 |
Nadav Rotem <nrotem@apple.com> |
Revert r162160 because it made a few buildbots fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b5838689c6e204af3677df0ae10167f6070aba00 |
|
18-Aug-2012 |
Nadav Rotem <nrotem@apple.com> |
The X86 backend has a number of optimizations for SETCC nodes which use
arithmetic instructions. However, when small data types are used, a truncate
node appears between the SETCC node and the arithmetic operation. This patch
adds support for this pattern.
Before:
xorl %esi, %edi
testb %dil, %dil
setne %al
ret
After:
xorb %dil, %sil
setne %al
ret
rdar://12081007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 63a99ff53ad859534b0c8161c2819692b5372b52 |
|
17-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Use nested switch to select arguments to reduce calls to EmitPCMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c087870c470b033a190aa08269095441816963e4 |
|
17-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to reduce to only a single call to it thus allowing it to be inlined by the compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b7bf7266fe0a1e84039d9240d1480b3cc9c33aba |
|
15-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
minor fix of X86ISD::VSEXT_MOVL dump
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7091b2451d46ae7e85188d1c5d7a43d775346ee0 |
|
14-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
fix PR11334
- FP_EXTEND only support extending from vectors with matching elements.
This results in the scalarization of extending to v2f64 from v2f32,
which will be legalized to v4f32 not matching with v2f64.
- add X86-specific VFPEXT supproting extending from v4f32 to v2f64.
- add BUILD_VECTOR lowering helper to recover back the original
extending from v4f32 to v2f64.
- test case is enhanced to include different vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cacafd410bb4a612f36bed5a260793e7d56503c8 |
|
14-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Factor duplicate calls to getUNDEF in several functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161860 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6d6881532cc2824408652080fc05af8f522c317a |
|
14-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Re-factor intrinsic lowering to combine common parts of similar intrinsics. Reduces compiled code size a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f1b2ec1e7188a9bddb6495d60812c26fdb544c2 |
|
13-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and putting an a couple if conditions in a better order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 523908d1bebd2d5d011ce58336dd086830773315 |
|
13-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Refactor code a bit to share commonalities. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ec6593cf8439146f5ae539363bf5cdd679d8195c |
|
13-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix an unused variable warning from r161742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bccc8ce9b8f3bd5403a034e75ba2d1c80a5a89fa |
|
13-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove the LowerMMXCONCAT_VECTORS function. It could never execute because there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c63d5e8c23cc60859130ead8e3b203d3cdda346 |
|
12-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove call to setOperationAction for SETCC of v4f32. SETCC returns an integer type not an FP type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b151a646188fa180f31529b4c15a910a577d1041 |
|
12-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary call to setOperationAction for SETCC of v2i64 under SSE42. It was already called for the same under SSE2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7a9a28b2c92a2f22a4d816c2d364edf7618882d7 |
|
12-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Make replace many calls to getSizeInBits() with is128BitVector/is256BitVector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0d1f176b3fa4b68fe55b76473b96ec5948794d7d |
|
12-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation actions. Compiles to smaller code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9eac20ac88b82d39aaac9838631f268f3ef69d2c |
|
12-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
fix PR13577, an issue introduced by r161687
- FCMOV only supports a subset of X86 conditions. Skip boolean
simplification if X86 condition is not valid for FCMOV.
- add a minimal test case for PR13577.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161732 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 880ef45a144a54398bcce8939972c8972c8830ec |
|
12-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop since all 256-bit types are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a33cec66a5d1b755e2bb045bdac1690fdcff19e |
|
10-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
add X86-specific DAG optimization to simplify boolean test
- if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value
generated from X86ISD::SETCC, try to simplify the boolean value
generation and checking by reusing the original EFLAGS with proper
condition code
- add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places
consuming EFLAGS
part of patches fixing PR12312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f6c24eef626a0675c907f28cd8dea9b666c69d09 |
|
10-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
remove tailing whitespaces and test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 78cab947cf8f81fc3cadbedd90c20fbe6e5eb1ee |
|
10-Aug-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Add some missing includes for the build against stdcxx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 39ad568c62f5120faec29f69d3d614303a1f992d |
|
08-Aug-2012 |
Manman Ren <mren@apple.com> |
X86: enable CSE between CMP and SUB
We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SUB back to CMP if possible at peephole.
Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled
by peephole now.
rdar://11873276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b64dd5f2b5a9989a8b1006d0aa82428455da039a |
|
08-Aug-2012 |
Evan Cheng <evan.cheng@apple.com> |
X86 cmp lowering is looking past truncate on the condition node. It should only
do so when the high bits are known zero. This caused a subtle miscompilation.
rdar://12027825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4feb647283db0ea4660941d3ac4202947b1ce196 |
|
06-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cc915951eb6f10002665879fae62d05c41d01d33 |
|
05-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove custom inserter for MWAIT. It doesn't do anything that couldn't be represented in a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 638aa687d4ad7b2384144de93518aaebfef9e38d |
|
05-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Use a COPY node instead of an explicit MOVA opcode in the custom insterter for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7744acd1ab73b3eec6f1449f47083abe3fb1b527 |
|
03-Aug-2012 |
Shih-wei Liao <sliao@google.com> |
Merge with LLVM upstream r160668 (Jul 24th 2012)
Conflicts:
include/llvm/Support/ELF.h
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/Support/Memory.cpp
lib/Transforms/Instrumentation/AddressSanitizer.cpp
Change-Id: Iddd658cf2eadc7165b2805b446d31af2c5c9917f
|
| d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3 |
|
03-Aug-2012 |
Bob Wilson <bob.wilson@apple.com> |
Fall back to selection DAG isel for calls to builtin functions.
Fast isel doesn't currently have support for translating builtin function
calls to target instructions. For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization. Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel. <rdar://problem/12008746>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a20e1e7ef596842127794372244fd5c646f71296 |
|
01-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1503aba4a036f5394c7983417bc1e64613b2fc77 |
|
01-Aug-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added FMA functionality to X86 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1cee71099c0477c6bf0e8ff76a55b8873ce146b4 |
|
25-Jul-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
When a return struct pointer is passed in registers, the called has nothing
to pop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c8e41c591741b3da1077f7000274ad040bef8002 |
|
23-Jul-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo (the the => the)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a9e13ba3c8230073dd1157e4a17ef52906ac6cb8 |
|
17-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
Back out r160101 and instead implement a dag combine to recover from instcombine transformation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160387 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f5c0539092996771824893309f311378e719e32e |
|
17-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
Implement r160312 as target indepedenet dag combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 70e10d3fe4c5df189348f64fce56254a5a32b51c |
|
17-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
This is another case where instcombine demanded bits optimization created
large immediates. Add dag combine logic to recover in case the large
immediates doesn't fit in cmp immediate operand field.
int foo(unsigned long l) {
return (l>> 47) == 1;
}
we produce
%shr.mask = and i64 %l, -140737488355328
%cmp = icmp eq i64 %shr.mask, 140737488355328
%conv = zext i1 %cmp to i32
ret i32 %conv
which codegens to
movq $0xffff800000000000,%rax
andq %rdi,%rax
movq $0x0000800000000000,%rcx
cmpq %rcx,%rax
sete %al
movzbl %al,%eax
ret
TargetLowering::SimplifySetCC would transform
(X & -256) == 256 -> (X >> 8) == 1
if the immediate fails the isLegalICmpImmediate() test. For x86,
that's immediates which are not a signed 32-bit immediate.
Based on a patch by Eli Friedman.
PR10328
rdar://9758774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 98819c9d1e3b929e9ebab0e8cd3edb31aad21bd8 |
|
16-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
For something like
uint32_t hi(uint64_t res)
{
uint_32t hi = res >> 32;
return !hi;
}
llvm IR looks like this:
define i32 @hi(i64 %res) nounwind uwtable ssp {
entry:
%lnot = icmp ult i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
}
The optimizer has optimize away the right shift and truncate but the resulting
constant is too large to fit in the 32-bit immediate field. The resulting x86
code is worse as a result:
movabsq $4294967296, %rax ## imm = 0x100000000
cmpq %rax, %rdi
sbbl %eax, %eax
andl $1, %eax
This patch teaches the x86 lowering code to handle ult against a large immediate
with trailing zeros. It will issue a right shift and a truncate followed by
a comparison against a shifted immediate.
shrq $32, %rdi
testl %edi, %edi
sete %al
movzbl %al, %eax
It also handles a ugt comparison against a large immediate with trailing bits
set. i.e. X > 0x0ffffffff -> (X >> 32) >= 1
rdar://11866926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d896e242993fd04c013dda8987c232cdcab63dd4 |
|
15-Jul-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Teach getTargetVShiftNode about TargetConstant nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 65f489fd7d876c3e624938cd46d2475c7f365a8a |
|
15-Jul-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit vector with the same element type as the input vector.
This is needed because of the patterns we have for the VP[SLL/SRA/SRL][W/D/Q] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| feae00a68e819e661ff6fddd15be703670247c10 |
|
12-Jul-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and MachineLICM don't touch it.
I already had the necessary things in place for IR-level passes but missed the machine passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b9bee0499553358e64c34cfcbd32380ac7fb452e |
|
12-Jul-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add intrinsics for Ivy Bridge's rdrand instruction.
The rdrand/cmov sequence is the same that is emitted by both
GCC and ICC.
Fixes PR13284.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5cd95e1478ddb8f3f1efde56a1cd2db47b312d72 |
|
11-Jul-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, allow loads/stores of 64bit values from xmm registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2dd83eb1ab3b7d7cdef2e244317caefd78be8a45 |
|
10-Jul-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Improve the loading of load-anyext vectors by allowing the codegen to load
multiple scalars and insert them into a vector. Next, we shuffle the elements
into the correct places, as before.
Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the
migration of bitcasts happened too late in the SelectionDAG process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 85dccf18ea0e0b7258d1c5f186b616e022dbebf1 |
|
05-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make X86 call and return instructions non-variadic.
Function argument and return value registers aren't part of the
encoding, so they should be implicit operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b8720787015dc73d8a050b063366be6c3ad01946 |
|
04-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Ensure CopyToReg nodes are always glued to the call instruction.
The CopyToReg nodes that set up the argument registers before a call
must be glued to the call instruction. Otherwise, the scheduler may emit
the physreg copies long before the call, causing long live ranges for
the fixed registers.
Besides disabling good register allocation, that can also expose
problems when EmitInstrWithCustomInserter() splits a basic block during
the live range of a physreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8f40f7b8676ae7931baaecb1046a21f09471384b |
|
01-Jul-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Optimization of shuffle node that can fit to the register form of VBROADCAST instruction on AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 94e3b388e561ce980c861e092bf378bf40202268 |
|
29-Jun-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
In the initial exec mode we always do a load to find the address of a variable.
Before this patch in pic 32 bit code we would add the global base register
and not load from that address. This is a really old bug, but before the
introduction of the tls attributes we would never select initial exec for
pic code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fcb09468334ab9f1d50e75e07615479d2e398802 |
|
26-Jun-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Removed unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a44489d5b5687e98c39947b7b64187a3ad5faf0e |
|
26-Jun-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename to match other X86_64* names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1596373671e4df54e53e79dc613545d5cf9d83bb |
|
26-Jun-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Shuffle optimization for AVX/AVX2.
The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction.
Before:
vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3]
vpermilps $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3]
vextractf128 $1, %ymm1, %xmm1
vextractf128 $1, %ymm0, %xmm0
vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3]
vpermilps $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3]
vinsertf128 $1, %xmm0, %ymm2, %ymm0
After:
vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4]
vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4]
vunpcklps %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52d418df5d67ffdf4c9782c5fa8d3fdbd2478631 |
|
26-Jun-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Make some ugly hacks for inline asm operands which name a specific register a bit more thorough. PR13196.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 82d58b147f25f97b522f8916a47b40f2d81bfa56 |
|
24-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
%RCX is not a function live-out in eh.return functions.
The function live-out registers must be live at all function returns,
and %RCX is only used by eh.return. When a function also has a normal
return, only %RAX holds a return value.
This fixes PR13188.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6e2db65266c238368f744bbc42b8f4239fd1e76e |
|
24-Jun-2012 |
Pete Cooper <peter_cooper@apple.com> |
Remove code i'd been testing with but didn't mean to commit. Oops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b49998d76cb4e414d13d60116adf13b085d85dc1 |
|
24-Jun-2012 |
Pete Cooper <peter_cooper@apple.com> |
DAG legalisation can now handle illegal fma vector types by scalarisation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ce0a5cda8aa547d5219da70a68bef40d5ed8392c |
|
23-Jun-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle aliases to tls variables in all architectures, not just x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 703c38bf584b39275ba517982677491607f46d20 |
|
20-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Don't insert 128-bit UNDEF into 256-bit vectors. Just keep the 256-bit vector. Original patch by Elena Demikhovsky. Tweaked by me to allow possibility of covering more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d6b43a317e71246380db55a50b799b062b53cdce |
|
19-Jun-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the support for using .init_array from ARM to the generic
TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM,
on X86 it is not easy to find out if .init_array should be used or not, so
the decision is made via TargetOptions and defaults to off.
Add a command line option to llc that enables it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a5dc43bd97487ea33a1af4e686661ad90f192ad |
|
09-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c29106b36f97d0f2dc806d1e8bf8d44fc466b9d3 |
|
09-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as an argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 45d53b866e63dd4899c2ea691e3539da8dbb3909 |
|
08-Jun-2012 |
Manman Ren <mren@apple.com> |
Enable optimization for integer ABS on X86 if Subtarget has CMOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9236362a64ce1609222512fe3f17eeb886a3ddea |
|
08-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: optimize generated code for integer ABS
This patch will generate the following for integer ABS:
movl %edi, %eax
negl %eax
cmovll %edi, %eax
INSTEAD OF
movl %edi, %ecx
sarl $31, %ecx
leal (%rdi,%rcx), %eax
xorl %ecx, %eax
There exists a target-independent DAG combine for integer ABS, which converts
integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov.
This is implemented in PerformXorCombine.
rdar://10695237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bdcae3825633082774ec702fd05cc556ed683ca6 |
|
07-Jun-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Do not optimize the used bits of the x86 vselect condition operand, when the condition operand is a vector of 1-bit predicates.
This may happen on MIC devices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e6fc9d40b37495056fa9fcd2fea188cb98726035 |
|
07-Jun-2012 |
Manman Ren <mren@apple.com> |
PR13046: we can't replace usage of SUB with CMP in the lowering phase.
It will cause assertion failure later on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87253c2ebdae320ee24a2cbf10f8de9b3acba763 |
|
07-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: replace SUB with CMP if possible
This patch will optimize the following
movq %rdi, %rax
subq %rsi, %rax
cmovsq %rsi, %rdi
movq %rdi, %rax
to
cmpq %rsi, %rdi
cmovsq %rsi, %rdi
movq %rdi, %rax
Perform this optimization if the actual result of SUB is not used.
rdar: 11540023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d9b0b025612992a0b724eeca8bdf10b1d7a5c355 |
|
02-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix typos found by http://github.com/lyda/misspell-check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f0234fcbc9be9798c10dedc3e3c134b7afbc6511 |
|
01-Jun-2012 |
Hans Wennborg <hans@hanshq.net> |
Implement the local-dynamic TLS model for x86 (PR3985)
This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ee66b417efcf4469dcd9f9ab3f503d27ec66f804 |
|
31-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add support for return value promotion in X86 calling conventions.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
|
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 85b9e56bac85b30ede70e46ef9f60e4dec3b88f3 |
|
22-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix constant used for pshufb mask when lowering v16i8 shuffles. Bug introduced in r157043. Fixes PR12908.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8ae97baef204508272b60f63da0ccf97ecf09b01 |
|
21-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Allow 256-bit shuffles to still be split even if only half of the shuffle comes from two 128-bit pieces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87d35e8c715f5116b072ef8fd742c0cfb6fb5ce4 |
|
19-May-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
On Haswell, perfer storing YMM registers using a single instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4fc8a5de44c2fc3ce82d5467bd96dfe25aa3a0e9 |
|
19-May-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Add support for additional in-reg vbroadcast patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| be97ae9e89ac45981ccd3faf5d47a14279b2f604 |
|
18-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify code a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b82b5abf78549119a88a106e161f32bcf04a2d41 |
|
18-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify handling of v16i8 shuffles and fix a missed optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 228756c744a1f877f7150c8fc91e074ff58c9d66 |
|
11-May-2012 |
Hans Wennborg <hans@hanshq.net> |
Implement initial-exec TLS model for 32-bit PIC x86
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b88e8dd31d1364d288d970f9187342a33b8de149 |
|
10-May-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix merge-typo and cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b210651654e64bec5eb14214a61da52c451a4044 |
|
10-May-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
AVX2: Add an additional broadcast idiom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156540 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5fc2187a025bb77b9023239edf12868d833630fe |
|
10-May-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in the program.
Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users.
Fix PR11900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 42726835e38dd1b41c587187ddd04f5c9276ff08 |
|
07-May-2012 |
Chad Rosier <mcrosier@apple.com> |
Fix a regression from r147481. This combine should only happen if there is a
single use.
rdar://11360370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed57984483b9268c30c71031fca07e71b985f169 |
|
07-May-2012 |
Manman Ren <mren@apple.com> |
X86: optimization for -(x != 0)
This patch will optimize -(x != 0) on X86
FROM
cmpl $0x01,%edi
sbbl %eax,%eax
notl %eax
TO
negl %edi
sbbl %eax %eax
In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td:
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
rdar: 10961709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d978c54e607fbcf426db20727d5fed71e1def2f6 |
|
06-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bdcbcb3ae7c035459a2c6adad7e95dc377f22f22 |
|
06-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aaf723dd2bccc052d2dd28e3cc4db76f2a3e2fb0 |
|
05-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a new target hook "predictableSelectIsExpensive".
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.
Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.
I'm not entirely happy with the name of this flag, suggestions welcome ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 31a207a3b748261e3556328bd8a80a75ffbb698d |
|
04-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix some loops to match coding standards. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6643d9c1800df550c071baad9ad770a59d4dd903 |
|
04-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix up some spacing. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5da8a803779810578a896d44bfde28fd7567b2d4 |
|
04-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify broadcast lowering code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f3640d7ec1373f964fb998138e54d81cc21c7a22 |
|
04-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 11ac1f81a8d3cb9c58ec93e424429df9dccffe36 |
|
04-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify shuffle narrowing code a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b607264550b6d992cb299b0a9c832a6ed49d483c |
|
03-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Use 'unsigned' instead of 'int' in a few places dealing with counts of vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b28d356c56d656e8e4d23c71de80162bb2eba5e |
|
03-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c0f0a93936a23a0935aa946a65095388b50c087f |
|
03-May-2012 |
Preston Gurd <preston.gurd@intel.com> |
For Intel Atom, use ILP scheduling always, instead of ILP for 64 bit
and Hybrid for 32 bit, since benchmarks show ILP scheduling is better
most of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e2849851b29c0ac02d4428cd006163966dbf1bbf |
|
02-May-2012 |
Manman Ren <mren@apple.com> |
Revert r155853
The commit is intended to fix rdar://10961709.
But it is the root cause of PR12720.
Revert it for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a9a568a79dbaf7315db863b4808d31ad9f5f91dc |
|
02-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support for AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 769ea2f93fa7fdd73f8388e863cf4dc9689d2e38 |
|
01-May-2012 |
Manman Ren <mren@apple.com> |
X86: optimization for max-like struct
This patch will optimize the following cases on X86
(a > b) ? (a-b) : 0
(a >= b) ? (a-b) : 0
(b < a) ? (a-b) : 0
(b <= a) ? (a-b) : 0
FROM
movl %edi, %ecx
subl %esi, %ecx
cmpl %edi, %esi
movl $0, %eax
cmovll %ecx, %eax
TO
xorl %eax, %eax
subl %esi, %edi
cmovll %eax, %edi
movl %edi, %eax
rdar: 10734411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 16a76519a5aa0e3a351cfde8e7236119ffd8b7fb |
|
01-May-2012 |
Manman Ren <mren@apple.com> |
X86: optimization for -(x != 0)
This patch will optimize -(x != 0) on X86
FROM
cmpl $0x01,%edi
sbbl %eax,%eax
notl %eax
TO
negl %edi
sbbl %eax %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 238ae31aa3409dd498e7f9f79d42b0b2fbc8144c |
|
30-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
Tidy up. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d1e3dcf71406eec040cff90a38917a4ec5c87cf |
|
30-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
No need to normalize index before calling Extract128BitVector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6610b1db55bedaa9e96bf9ff49a19b1a91bd5370 |
|
29-Apr-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Remove unneeded casts. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d77d2feb7a5cb63f6ea55cd4695d38fc3b7c8560 |
|
29-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify code a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 66ddd153f6c3481cc4e1a771526157f41a9832b5 |
|
28-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Use 'unsigned' instead of 'int' in several places when retrieving number of vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a73b6fc51126d40e4b8830a13a9a4e9322c282a2 |
|
28-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
Add x86-specific DAG combine to simplify:
x == -y --> x+y == 0
x != -y --> x+y != 0
On x86, the generated code goes from
negl %esi
cmpl %esi, %edi
je .LBB0_2
to
addl %esi, %edi
je .L4
This case is correctly handled for ARM with "cmn".
Patch by Manman Ren.
rdar://11245199
PR12545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b4a8aef96df2440a41a8e49ce40e43030bd66f29 |
|
27-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 17c836c4b51a14f07a5d5442cf2e984474a8f57d |
|
27-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 88cf47e98471077cc69f9ba5462507eb20891499 |
|
25-Apr-2012 |
Shih-wei Liao <sliao@google.com> |
Fix sdk_x86-sdk build. Add <cctype> for tolower().
Change-Id: If3be5e195a8ee00abef055b7e98577b9981866eb
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c16f851569eff1c2296e6addf341c9797e386f01 |
|
25-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Use vector_shuffles instead of target specific unpack nodes for AVX ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87ffdbcb7b93db35d8ff87dfb84d6ae623a5f49f |
|
24-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8
immediate. We can't use it here because the shuffle code does not check that
the lower part of the word is identical to the upper part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ef43cf3a2d7fd933f9f9b2960df9426b054d32a |
|
24-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove dangling spaces. Fix some other formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7fd5e16d3bc24a8ec54c7b48f68b5fed53bfd2e6 |
|
24-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify code a bit and make it compile better. Remove unused parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a35407705da45effd3401fb42395355adaa6e0c2 |
|
23-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Optimize the vector UINT_TO_FP, SINT_TO_FP and FP_TO_SINT operations where the integer type is i8 (commonly used in graphics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 708e44fc9678085d35ce522aaf5995494901d312 |
|
23-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Use MVT instead of EVT through all of LowerVECTOR_SHUFFLEtoBlend and not just the switch. Saves a little bit of binary size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9d35240eee370542523bf68199d2cdb21ffbb42a |
|
23-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make getZeroVector and getOnesVector more alike as far as how they detect 128-bit versus 256-bit vectors. Be explicit about both sizes and use llvm_unreachable. Similar changes to getLegalSplat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 69947b9cea32d0c0df11c5451b7902b5a4ee82ff |
|
23-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up by removing some 'else' after 'return'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1842ba0dfc441b586187ce8174ee8b3d986f1e3a |
|
23-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up spacing in LowerVECTOR_SHUFFLEtoBlend. Remove code that checks if shuffle operand has a different type than the the shuffle result since it can never happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 731dfd0da928e10980eacb6edd104ebb1c71e0f0 |
|
23-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add a couple llvm_unreachables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0fbf364fd791a5179a777ad7dbe628f7439b629f |
|
23-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove some tab characers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e8eb116ff33b101708b3dbf84f660539268c1776 |
|
23-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove some 'else' after 'return'. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b14940a047d1bbf9927881d506f0b8b669658e52 |
|
22-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make Extract128BitVector and Insert128BitVector take an unsigned instead of an ConstantNode SDValue. getConstant was almost always called just before only to have the functions take it apart and build a new ConstantSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 767b4f64a09b6f3880e7cdc55ccdd02a090a97d0 |
|
22-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert getNode(UNDEF) to getUNDEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| df966f6beec0bcfa5f2c9bbcccd6e445f118668a |
|
22-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make calls to getVectorShuffle more consistent. Use shuffle VT for calls to getUNDEF instead of requerying. Use &Mask[0] instead of Mask.data().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d63fa657e4434f9e4b1bb6e54b66fee6093a86f3 |
|
22-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up. 80 columns and argument alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c7972d6385ff17574d76d0fdda5a1a5f53d49e8 |
|
22-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify code by converting multiple places that were manually concatenating 128-bit vectors to use either CONCAT_VECTORS or a helper function. CONCAT_VECTORS will itself be lowered to the same pattern as before. The helper function is needed for concats of BUILD_VECTORs since getNode(CONCAT_VECTORS) will just return a large BUILD_VECTOR and we may be trying to lower large BUILD_VECTORS when this occurs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1da5867236f4132ec56493f3535c7b5830878b55 |
|
22-Apr-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9e401f22ec4d1fc42c22802fef1479180ca31600 |
|
21-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make some fixed arrays const. Use array_lengthof in a couple places instead of a hardcoded number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d0cf565e799063555f3a3e2858d2ccf53056a0c4 |
|
21-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up. 80 columns and some other spacing issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c909950c384e8234a7b3c5a76b7f79e3f7012ceb |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a963c81819bed30d54174cdaf5a7e58696838d5a |
|
18-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove AVX vpermil intrinsics. I removed their uses from clang headers and builtins a while back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2091df3d09bba0705fc62d020e5177a246d67978 |
|
17-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Don't decode vperm2i128 or vperm2f128 into a shuffle if bit 3 or 7 of the immediate is set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c651fe6f445724627dcc48064797dca2aa4aedc |
|
16-Apr-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix incorrect atomics codegen introduced in r154705, and extend test to catch it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ffa6c40ecf502281ea171969b42a38c2eef0493f |
|
16-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Replace vpermd/vpermps intrinic patterns with custom lowering to target specific nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 92040745984933f51b7c36b8b93f0e5a1931feee |
|
16-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Change type profile for vpermv back to using operand type for the mask argument to match intrinsic behavior. Add a bitcast to the lowering code to convert mask from v8i32 to v8f32 for vpermps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8325c11d473a340217fa0de648ba8f733f2d626e |
|
16-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge vpermps/vpermd and vpermpd/vpermq SD nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 095c528f30a07f5f7819448ec4f144623239eca8 |
|
16-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Spacing fixes and 80 column fixes. Use 0 instead of 0x80 for undef indices in vpermps/vpermd. Hardware only looks at lower 3-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 73c504af9d86a426532ee32c5d07a4b872794675 |
|
15-Apr-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added VPERM optimization for AVX2 shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 42fc29e7176ff51d649eccf82c836510fde4438f |
|
14-Apr-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ~*x & y.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 91794872cefaf6c2652abad640048784bd6b0d02 |
|
11-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
remove unused argument
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e611378a6e45fcb4a039d8c0089cd8fed2d311dc |
|
11-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Reapply 154396 after fixing a test.
Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7f1f1453895431f948abbb5d9bf09b4faf87926a |
|
10-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9142ed58eb9e613ca72e5ac67b827a5e421a5e93 |
|
10-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r154396, which looks to be the real culprit behind the bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a1390516548b7abee4f1eb305afecdca5733ee30 |
|
10-Apr-2012 |
Eric Christopher <echristo@apple.com> |
Temporarily revert this patch to see if it brings the buildbots back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2330636a667b6015c038f2847139c9a5b3ee70ed |
|
10-Apr-2012 |
David Blaikie <dblaikie@gmail.com> |
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 50e64cfe6e250dbe2528fc5bda75c68b04a8bc49 |
|
10-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendv uses a register for the selection while vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf010eb9110009d745382bf15131fbe556562ffe |
|
10-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a long standing tail call optimization bug. When a libcall is emitted
legalizer always use the DAG entry node. This is wrong when the libcall is
emitted as a tail call since it effectively folds the return node. If
the return node's input chain is not the entry (i.e. call, load, or store)
use that as the tail call input chain.
PR12419
rdar://9770785
rdar://11195178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e80aa7c783ab27711505b540597d83e038fc6900 |
|
09-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Lower some x86 shuffle sequences to the vblend family of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 154819dd6f60d0d1d1c75a22e8902c5125fad49b |
|
09-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix a bug in the lowering of broadcasts: ConstantPools need to use the target pointer type.
Move NormalizeVectorShuffle and LowerVectorBroadcast into X86TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 34797136cb9fa9f450c0e1c47983482083979dd4 |
|
08-Apr-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Move the TLSModel information into the TargetMachine rather than hiding
in TargetLowering. There was already a FIXME about this location being
odd. The interface is simplified as a consequence. This will also make
it easier to change TLS models when compiling with PIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9d68b06bc5ef1157d198d52e3f6829c721d72552 |
|
08-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
AVX2: Build splat vectors by broadcasting a scalar from the constant pool.
Previously we used three instructions to broadcast an immediate value into a
vector register.
On Sandybridge we continue to load the broadcasted value from the constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9e5512a8ca49df9c8776a5a6f9dfbd7b2bd50616 |
|
06-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix narrowing conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9a2b6e1d7b26069fca0cac7766fbe1b29d710f23 |
|
06-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Allow 256-bit shuffles to be split if a 128-bit lane contains elements from a single source. This is a rewrite of the 256-bit shuffle splitting code based on similar code from legalize types. Fixes PR12413.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
|
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4ac9081c7110dbf099d682fa51c091741e763491 |
|
01-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
This commit contains a few changes that had to go in together.
1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
(and also scalar_to_vector).
2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))
3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y).
4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.
Code which was previously compiled to this:
movd (%rsi), %xmm0
movdqa .LCPI0_0(%rip), %xmm2
pshufb %xmm2, %xmm0
movd (%rdi), %xmm1
pshufb %xmm2, %xmm1
pxor %xmm0, %xmm1
pshufb .LCPI0_1(%rip), %xmm1
movd %xmm1, (%rdi)
ret
Now compiles to this:
movl (%rsi), %eax
xorl %eax, (%rdi)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3d092dbb91af75c7d39798c6d7a52d32446c3381 |
|
21-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Spacing fixes and using 'unsigned' instead of 'int' to index to select shuffle elements for consistency with other shuffle code in X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 89f4e6639d174d20f8be59af4895d7d851e4f624 |
|
20-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a1ffc681ed7372bd371c44a6e186291b6416fe47 |
|
20-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 97327dc6ef5183bbad308e19ed86488c7e94d973 |
|
18-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c5eaae4e9bc75b203b3a9922b480729bc4f340e2 |
|
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c8d7eea264bc82d96153e77667a595c8338c842f |
|
05-Mar-2012 |
Chad Rosier <mcrosier@apple.com> |
Address Evan's comments for r151877.
Specifically, remove the magic number when checking to see if the copy has a
glue operand and simplify the checking logic.
rdar://10930395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 74bab7f597b24d847175f8550002d8a014f63c8c |
|
02-Mar-2012 |
Chad Rosier <mcrosier@apple.com> |
Prevent obscure and incorrect tail-call optimization.
In this instance we are generating the tail-call during legalizeDAG. The 2nd
floor call can't be a tail call because it clobbers %xmm1, which is defined by
the first floor call. The first floor call can't be a tail-call because it's
not in the tail position. The only reasonable way I could think to fix this
in a target-independent manner was to check for glue logic on the copy reg.
rdar://10930395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
|
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9a68fdc7f8211a9330537d44e3406d79fc5562af |
|
25-Feb-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: Fix assertion failures and warnings caused by r151382 _ftol2 lowering for i386-*-win32 targets. Patch by Joe Groff.
[Joe Groff] Hi everyone. My previous patch applied as r151382 had a few problems:
Clang raised a warning, and X86 LowerOperation would assert out for
fptoui f64 to i32 because it improperly lowered to an illegal
BUILD_PAIR. Here's a patch that addresses these issues. Let me know if
any other changes are necessary. Thanks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a2d061ec08b86ba91d7009b6ffcf08d5bac3f42 |
|
24-Feb-2012 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Add WIN_FTOL_* psudo-instructions to model the unique calling convention
used by the Win32 _ftol2 runtime function. Patch by Joe Groff!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
|
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1bf724b28b7a44d5323f9e42718192987c75ce79 |
|
19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove some unneeded includes and fix ordering in X86ISelLowering.cpp. Remove unneeded 'using namespace'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd637ae0c316334cd7b353c96ae270cc0d9095e4 |
|
19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Unify all shuffle mask checking functions take a mask and VT instead of VectorShuffleSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5aaffa84703debaba17650c5ca9eae9a49844cf1 |
|
19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make a bunch of X86ISelLowering shuffle functions static now that they are no longer needed by isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 527a08b253795cf09de41c289c9dc071f00b1d4a |
|
16-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the same CALL instructions for Windows as for everything else.
The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8bcde2aa66415ba2e63b22d2a3c1750bfb25b550 |
|
16-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Enable register mask operands for x86 calls.
Call instructions no longer have a list of 43 call-clobbered registers.
Instead, they get a single register mask operand with a bit vector of
call-preserved registers.
This saves a lot of memory, 42 x 32 bytes = 1344 bytes per call
instruction, and it speeds up building call instructions because those
43 imp-def operands no longer need to be added to use-def lists. (And
removed and shifted and re-added for every explicit call operand).
Passes like LiveVariables, LiveIntervals, RAGreedy, PEI, and
BranchFolding are significantly faster because they can deal with call
clobbers in bulk.
Overall, clang -O2 is between 0% and 8% faster, uniformly distributed
depending on call density in the compiled code. Debug builds using
clang -O0 are 0% - 3% faster.
I have verified that this patch doesn't change the assembly generated
for the LLVM nightly test suite when building with -disable-copyprop
and -disable-branch-fold.
Branch folding behaves slightly differently in a few cases because call
instructions have different hash values now.
Copy propagation flushes its data structures when it crosses a register
mask operand. This causes it to leave a few dead copies behind, on the
order of 20 instruction across the entire nightly test suite, including
SPEC. Fixing this properly would require the pass to use different data
structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2dcd718c1352f79a9728e6cc8d961fc1fe67bf2c |
|
13-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d4a19b6a72d19a6f90b676aac37118664b7b7a84 |
|
11-Feb-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add support for implicit TLS model used with MS VC runtime.
Patch by Kai Nacke!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 39a9e485f2ed2aa84ced9ec98c97daf00bfaf510 |
|
11-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f602040c4900d89bbf55478420769e36604588fb |
|
08-Feb-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Fixed a bug in printing "cmp" pseudo ops.
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0 llc 0x0000000001355803
> 1 llc 0x0000000001355dc9
> 2 libpthread.so.0 0x00007f79a30575d0
> 3 libc.so.6 0x00007f79a23a1945 gsignal + 53
> 4 libc.so.6 0x00007f79a23a2f21 abort + 385
> 5 libc.so.6 0x00007f79a239a810 __assert_fail + 240
> 6 llc 0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119
I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.
You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5a313bb7e8f3c7e24f69f7e7bff5bc2a2293bd31 |
|
08-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dbd98a4b1b4c5311a45d0ade760ec1218924f45d |
|
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7302d80490feabfc8a01bee0fa698aab55169544 |
|
06-Feb-2012 |
Chris Lattner <sabre@nondot.org> |
Remove some dead code and tidy things up now that vectors use ConstantDataVector
instead of always using ConstantVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149912 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 699ddcbcb32e933f5a2a63c41c80832da91942ad |
|
06-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Don't call malloc for 4 bits. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d156dc11f9acd83e3369c069d5006a0203be13d6 |
|
06-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5b8a1db7ea6510a2589f710d50754599da742de9 |
|
05-Feb-2012 |
Duncan Sands <baldrick@free.fr> |
Persuade GCC that there is nothing worth warning about here (there isn't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6d1263acb9704b38a8d90fd6ce94f49193cd4dde |
|
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable in X86 Target directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| abb94d06878f49d526c7ed32727faa336a647a57 |
|
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert some assert(0) in default of switch statements to llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5b209e84f498b0e98d7f92123eac50a651aa01e1 |
|
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a02556679e685280bd59e0197d9e4aa51d40480c |
|
03-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fa5b70e1d8856a2e52444ac82fa641d20276280c |
|
03-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6e3f7e4913b17d7f8e3d81d61aa9e133f97e1ccd |
|
03-Feb-2012 |
Lang Hames <lhames@gmail.com> |
Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 478a8a02bc0f2e739ed8f4240152e99837e480b9 |
|
03-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Require non-NULL register masks.
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0f1ead47a0bee861f1a9a2ed9fe728510cef4f62 |
|
02-Feb-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Minor change in signature of the getZeroVector()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dcabc7bca9b81c384d307cbb7d28b29451e263f2 |
|
02-Feb-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Optimization for SIGN_EXTEND operation on AVX.
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1ae52f686cb04a08cb64b3fab90e7ac4c9010384 |
|
02-Feb-2012 |
Francois Pichet <pichet2000@gmail.com> |
Unbreak the MSVC build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 50a36f710275c0120b6ae6e607503733982815fb |
|
02-Feb-2012 |
Lang Hames <lhames@gmail.com> |
Set EFLAGS correctly in EmitLoweredSelect on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 922d314e8f9f0d8e447c055485a2969ee9cf2dd2 |
|
02-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Instruction scheduling itinerary for Intel Atom.
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 845b1899b62f6f0e87d5c939c6bbd46a934fff4e |
|
01-Feb-2012 |
Mon P Wang <wangmp@apple.com> |
Avoid creating an extract element to an illegal type after LegalizeTypes has run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c2348d5c08dc9cd3f015110700e62a1ed9347c16 |
|
01-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 732525758f3c486f5e570528e7fd9b35fe121ba0 |
|
01-Feb-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Shortened code in shuffle masks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ae98150e3e3c4770644a33cf38fe42a582509bb |
|
01-Feb-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Optimization for "truncate" operation on AVX.
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a1902a18cd289d9554f5649324c5ad27109586bb |
|
01-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cac50c5ab8bc2e8a55eb91a4b36d46e1c20c9c64 |
|
31-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove pcmpgt/pcmpeq intrinsics as clang is not using them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 630ecf0f53168451343e254b1fe4dc21c9e83052 |
|
30-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix refacto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b2f1b5028c03cd16c2452e81544d2da51fb373f2 |
|
30-Jan-2012 |
Douglas Gregor <dgregor@apple.com> |
Eliminate narrowing conversion in initializer list, to make C++11 happy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9c68354956fb8331c18d2cac42dfb5f825fbb8bd |
|
30-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Simplify shuffle mask generation code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cc30006391ef3dac5240b8b2197a7129440f34ad |
|
30-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 86c7c583a36e54ea13f2ee31d622090b4fe9c184 |
|
30-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e566cd0f4d49c7a546e6cd6be0f49f4c74ad3cdb |
|
26-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove some more patterns by custom lowering intrinsics to target specific nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 97484795904498acc5f88df23498c65fcf151a7f |
|
25-Jan-2012 |
Chris Lattner <sabre@nondot.org> |
fix a bug I introduced in r148929, this is not a splat!
Thanks to Eli for noticing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 969ba287cd2be9b2d6843db6fa5337585f84283b |
|
25-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4ca829e89567f002fc74eb0e3e532a7c7662e031 |
|
25-Jan-2012 |
Chris Lattner <sabre@nondot.org> |
use ConstantVector::getSplat in a few places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4bb3f34b2296f0ec70751f332cf7ef96d2d30a48 |
|
25-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 28d7e71a3021d55dce21005112f444facbda0398 |
|
24-Jan-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
ZERO_EXTEND operation is optimized for AVX.
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7925e2555d4a2305784365176dba72a64fc3975c |
|
23-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7fb8b0c5d3eab5047dbec08fe46916e9c09f768c |
|
23-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Update more places to use target specific nodes for vector shifts instead of intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 80e46360e9224a9169b1d2d1cd376e9c36d0d566 |
|
23-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1906d32e55224b7481cd9e5726bd5e14b55f5cc1 |
|
23-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 67609fd0eb05a49cc4636d507398034393dcf302 |
|
22-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed2e13d66709d41a26b96e2a02b6f2797ff2e7b7 |
|
22-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 07a276277fe21f01c19e091b05402b69348e6b2d |
|
22-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Make code a little less verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6a32b6f0c088e4d2972cf5d208c54f42c2c52f85 |
|
22-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unused X86 ISD node type defines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d9ec725db431744be037eaedd29d6575e3cc2754 |
|
21-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8f35c13842187d23e7d10ec2e5f416d0363abf50 |
|
20-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0e2037ba2baed90310f7ba21c4557eb49da05938 |
|
20-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for selecting 256-bit PALIGNR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9a2478ac1a9aafcd5e89808868e170cfdfefcdc1 |
|
20-Jan-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a7700a3fac132b89fa8d577fe90c20a95a5494e |
|
19-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 22de16dc7582dac43429ce0dcb374604020c01f5 |
|
19-Jan-2012 |
Nick Lewycky <nicholas@mxc.ca> |
Add a TargetOption for disabling tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c38c4561cd1c8ee305122205daff2a6324900127 |
|
19-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add experimental -x86-use-regmask command line option.
It adds register mask operands to x86 call instructions. Once all the
backend passes support register mask operands, this will be permanently
enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a16d441430440d9255fe16441cea7a38e8f3c461 |
|
17-Jan-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b94b5f52b11092a69267159dfe0df3acdfcabd7 |
|
17-Jan-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix 11769.
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8b5a6b63dd2e04ba770f216345402b7c80e8f228 |
|
17-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary AVX check from an assert. hasSSE2 is enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37c2677fbcff1187106c579abfbd498aac739c2a |
|
17-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cc6165695fa1713230184d743368b8b3642faa5d |
|
15-Jan-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.
We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.
Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed4c8c633c52a40ad1a3e8687f290be4aeb1f0e8 |
|
15-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 562659ff6bdc3ac5d67b666862b025e4aa9dacd4 |
|
13-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 12216172c04fe76a90e9de34fc4161e92d097278 |
|
13-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e6cf4a070d41d19c133b8713dafa91e51a198e60 |
|
13-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 16db71089814c2a498cf2980d0013a59ade86e58 |
|
12-Jan-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed.
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d2070b00efb97ee32e360d53edfd7bf6de88d62c |
|
12-Jan-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors.
The attached testcase was stuck in an endless loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 014f7a3b3798580d5aac80b83bcb67e03d302fa4 |
|
11-Jan-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Explicitly set the scale to 1 on some segstack prologue instrs.
Patch by Brian Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 394a1f53b90698486ac7c75724a6bda349cd0353 |
|
11-Jan-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not zero untouched elements. Use INSERT_VECTOR_ELT instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9ffaa6a8a916d88c7ffde6beea7faee1b93ad945 |
|
10-Jan-2012 |
Lang Hames <lhames@gmail.com> |
Fixed order of operands in comment to match code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147890 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f6c0747ae326a5ee83b846d40f6c657cf43a1e21 |
|
10-Jan-2012 |
Bill Wendling <isanbard@gmail.com> |
For i386, don't use the generic code.
As the comment around 7746 says, it's better to use the x87 extended precision
here than SSE. And the generic code doesn't know how to do that. It also regains
the speed lost for the uint64_to_float.c testcase.
<rdar://problem/10669858>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a937633893432b4cdbd1a32602c566f0a006f2fd |
|
10-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1accb7ed98d823c291a4d5df172d0538451aba9e |
|
10-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is the final piece to remove the AVX hack that disabled SSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d0a31177684eddd44eedb05839195820e84a9b54 |
|
10-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. AVX is now an SSE level and no longer disables SSE checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6202e45d53d49e0f973a8d3b362941411b7604b5 |
|
09-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Change some places that were checking for AVX OR SSE1/2 to use hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 435d0bd09d34d0a9df2418b121c845841b0b5e11 |
|
08-Jan-2012 |
Victor Umansky <victor.umansky@intel.com> |
Reverted commit #147601 upon Evan's request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f321e1075eabae96f62b1f2570d9dee5d10b8200 |
|
07-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 272cc580f8eff8b893f3d71f88ac97f49ed2aa8c |
|
07-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary check of hasAVX(). It's already included in hasXMM().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5548755201a49bfe2af709ba0d0e7ba851cdb44f |
|
07-Jan-2012 |
Eric Christopher <echristo@apple.com> |
Make the 'x' constraint work for AVX registers as well.
Fixes rdar://10614894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 19d8559019b75edfd7f5b05ffa266bc278127854 |
|
05-Jan-2012 |
Victor Umansky <victor.umansky@intel.com> |
Peephole optimization of ptest-conditioned branch in X86 arch. Performs instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX.
Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX)
Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 397ae210ce55545eaff21c5813d060fa567843a5 |
|
05-Jan-2012 |
Bill Wendling <isanbard@gmail.com> |
Replace the uint64_t -> double convertion algorithm with one that's more efficient.
This small bit of ASM code is sufficient to do what the old algorithm did:
movq %rax, %xmm0
punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
#ifdef __SSE3__
haddpd %xmm0, %xmm0
#else
pshufd $0x4e, %xmm0, %xmm1
addpd %xmm1, %xmm0
#endif
It's arguably faster. One caveat, the 'haddpd' instruction isn't very fast on
all processors.
<rdar://problem/7719814>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 56f582d664c54bf4567ec37d0bd16b6d4ea6a6eb |
|
04-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
For x86, canonicalize max
(x > y) ? x : y
=>
(x >= y) ? x : y
So for something like
(x - y) > 0 : (x - y) ? 0
It will be
(x - y) >= 0 : (x - y) ? 0
This makes is possible to test sign-bit and eliminate a comparison against
zero. e.g.
subl %esi, %edi
testl %edi, %edi
movl $0, %eax
cmovgl %edi, %eax
=>
xorl %eax, %eax
subl %esi, $edi
cmovsl %eax, %edi
rdar://10633221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b90d2a9046954706f98b8d338b465389834a3bf1 |
|
04-Jan-2012 |
Chad Rosier <mcrosier@apple.com> |
Fix 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c2d064f0283504d7fe91369021bfd44ce5c8eb2a |
|
03-Jan-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Revert 147426 because it caused pr11696.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3d1161e9ae2aedc45f40cc1b7be1db3df2094903 |
|
03-Jan-2012 |
Chad Rosier <mcrosier@apple.com> |
Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.
rdar://10594409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c612d7981756fc379817840704c3d7416fa58892 |
|
02-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a51bb3aa7525b3260575724ba413debd4b56041b |
|
02-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a46f35d3d65425af5eaaaf906fca240a33d6c362 |
|
02-Jan-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b3982da7d219edb24795d7e01513cc55fcd7bd16 |
|
01-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge X86 SHUFPS and SHUFPD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 19ec2a9db1c6105715a5517522671659286dbae3 |
|
29-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d62c16e535424abf739872e355904f2d5a15edff |
|
29-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove some elses after returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3224e6b60a82eedf703c8c4a628362e8095aed01 |
|
29-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da813f420907ad29802ce9e80238258a48385212 |
|
28-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix type-checking for load transformation which is not legal on floating-point types. PR11674.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 021c0a2ee7121c4ccd0765699c14f8c9f7f7c596 |
|
28-Dec-2011 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3738ccd7eb99d75cbe31777a98675e5e5c23fee3 |
|
27-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147287 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7782102c70fdfd48776f05099eb67dd268cfc222 |
|
24-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the
LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type
We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3d636ea8edf9332ab5ab2d92f7ea5c7444e88757 |
|
24-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Add systematic testing for cttz as well, and fix the bug I spotted by
inspection earlier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d873a4b89b365f1e58e808109cd77034517f095d |
|
24-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Expand more when we have a nice 'tzcnt' instruction, to avoid generating
'bsf' instructions here.
This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| acc068e873a1a2afa1edef20452722d97eec8f71 |
|
24-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:
(sizeof(x)*8 - 1) ^ __builtin_clz(x)
Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.
The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.
Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.
These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 30450e89d94a5d7daa887c7b25a33aa9aa19863c |
|
22-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Fix 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 649326ab15d7092ad12ceb592127a28d3d17d432 |
|
21-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
necessary. Please chime in if I'm mistaken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f2d7693fbb10f9ec3457e539dd5ba4bdb4cb3b85 |
|
20-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Begin teaching the X86 target how to efficiently codegen patterns that
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0581ed792b0e28803b3d584f1b15243e583c6a84 |
|
18-Dec-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Another variadics tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ea4cdb81f0f69f89d93f4726f25e849216ac973 |
|
18-Dec-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Use the fancy new VariadicFunction template instead of a plain variadic function.
Some compilers were complaining about passing StringRef to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab44d3cf49886f14018db9e67fffc58d9c67cbfb |
|
17-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove an unused X86ISD node type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e6cddb77dce72553cc7d7188ca92bad9d01ca498 |
|
17-Dec-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Factor the bswap asm matching to be slightly less horrible to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8b99c1e42cff9a55996907901a5ad81a97f24912 |
|
17-Dec-2011 |
Lang Hames <lhames@gmail.com> |
Make sure that the lower bits on the VSELECT condition are properly set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 94438ba53828ed866d1d18ba94faabf4253cf194 |
|
16-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0660cfe3c88bbe2b06fc272bab36048826ccef1e |
|
15-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a0a251372f838a6a916812cfff87cc0d71072d81 |
|
15-Dec-2011 |
Lang Hames <lhames@gmail.com> |
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 01d426e0e16aab075c1b0c03552e1cc9b5f3cef1 |
|
15-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Use SmallVector/assign(), rather than std::vector/push_back().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a860b189e4bce05346754d7475541bcd851e195b |
|
15-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for lowering fneg when AVX is enabled.
rdar://10566486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 63974b2144c87c962effdc0508c27643c8ad98b6 |
|
13-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d93e4c34963e83befbe67370fa39b66530b5e193 |
|
11-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b653397dcd34fe281286cf80d4c101000516e88e |
|
09-Dec-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 587e34065fcda3b379cfda92b034d4731ce48043 |
|
08-Dec-2011 |
Owen Anderson <resistor@mac.com> |
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
Fixes failures caused by r146171.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4a4fdf3476473021f62d5b02e8ee8802f5b25e5a |
|
08-Dec-2011 |
Owen Anderson <resistor@mac.com> |
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fe03315925dafb484f850fbd86edd72bb8310144 |
|
06-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86ISD::HADD/HSUB to getTargetNodeName
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 34671b812a9855623fd9a02e5e2b2cb95a13ba2f |
|
06-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge floating point and integer UNPCK X86ISD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3d8c2ce3e44bc161118a8922e7aa412ef00f6034 |
|
06-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1ff73d7a67e4a5bc464523cd1dd7ed3f20baf85b |
|
06-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8c741b8064f1116d8d8dc435b60b75abdf5c4d57 |
|
06-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use logarithmic units for basic block alignment.
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.
CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.
Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.
Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1dc0fbc168de60c0cbb2b57e936b8a3313887fcb |
|
05-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| beabc6cc6de617a339c740fe4f1e5870c03dacbe |
|
05-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Clean up and optimizations to the X86 shuffle lowering code. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 |
|
02-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f8363305ebd026fafda41491fc7df3b22d58f968 |
|
02-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 138a5c66b9ccaded2ee5d63b96f69349c098e49a |
|
02-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 18197d74255ef076d48c6cec7b6f7ce3d987c3fb |
|
30-Nov-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b72039cf52dc1cf8d4393c21d3c6588546e535c3 |
|
30-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add instruction selection support for AVX2 horizontal add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ec24e61ab0a22f58fedac374ef0df3e69d9a2587 |
|
30-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge VPERM2F128/VPERM2I128 ISD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 316cd2a2c57037ecca93bb20d939b89dad4c5243 |
|
30-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 36e36ace77cf84d7c8326957925550624b3fc89c |
|
29-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 70b883b3a723b1d0af538c0b78cd45139597d216 |
|
28-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71c4c1223257995d7bf37e49b53509b749476b89 |
|
28-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Make isCommutedVSHUFP more like the way isCommutedSHUFP is handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9d7025b56b582b8de50625ac58495527756af103 |
|
27-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge detecting and handling for VSHUFPSY and VSHUFPDY since a lot of the code was similar for both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 38034c568c5f006b5bfe57d6777f5479282ed511 |
|
26-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 06cb680779597c35e6b6399dea6f10276273970b |
|
26-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 705f2431a086bbe662bca0035938e774378de3ec |
|
24-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f475a55bd41a2fc047e74c38014564e8e6b678f0 |
|
24-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f238f50aaf8a68f16dcc43a017aa32cbb73e938e |
|
23-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Use btq for bit tests if the immediate can't be encoded in 32 bits.
Before:
movabsq $4294967296, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
testq %rax, %rdi ## encoding: [0x48,0x85,0xf8]
jne LBB0_2 ## encoding: [0x75,A]
After:
btq $32, %rdi ## encoding: [0x48,0x0f,0xba,0xe7,0x20]
jb LBB0_2 ## encoding: [0x72,A]
btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off
saving one register and a giant movabsq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52a35a89e6c07d010d7abdba9646a56536331c36 |
|
23-Nov-2011 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
I added several lines in X86 code generator that allow to choose
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.
The patch was reviewed by Bruno.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f7de577a08a705970f0fd8f3c1bb40f7040e4476 |
|
22-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c0d82857e095de15b31b0d654856aebea60dd339 |
|
22-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6fa583d78701390079db0cc4d944823af06023c6 |
|
21-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6347e8662cea47065ed7092d75322076fc3e57f8 |
|
21-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a124f949527e36efc05d2dbc999ddce43791b4ec |
|
21-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0d86d462f8458b803d5209a77961dc63d5a9dae0 |
|
20-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 745a86bac9684f9617aeb0e1566194ca797a64d4 |
|
19-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 98fc72940b8f3ec553c96a719eb0d6f4196fae49 |
|
19-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 54f952afac04cb1e944f4fa0c1cd494e291bef20 |
|
19-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3113384a346709f1c3578c4ff2bd15c920dc02a6 |
|
19-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1666cb6d637af89a752d2be938be53be5253bdfd |
|
19-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Extend VPBLENDVB and VPSIGN lowering to work for AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cbbe33fde4f484ffdc9a171b69d6f98eb89dabd9 |
|
18-Nov-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add AVX2 vpbroadcast support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f8c10e5cb1779920307e05ce1d9bc57e7463e040 |
|
15-Nov-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2d496897934adfc0e3e1563dd64d9a7122971e22 |
|
15-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
by later instructions.
Only done for DEC64m right now.
Fixes <rdar://problem/6172640>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d9190c0f148b218ab046deadd0c7ae475414cde5 |
|
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Remove some unnecessary includes of PseudoSourceValue.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a77214a4c43d7a0c49c348439c6887f28bd6d53d |
|
14-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered
Constant idx case is still done in tablegen but other cases are then expanded
Fixes <rdar://problem/10435460>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3426a3efef546a20adf9e2064f589417ab89442b |
|
14-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e6a6277d3683ef7aa9d799b32b5194a79eefde62 |
|
13-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add BLSI, BLSMSK, and BLSR to getTargetNodeName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7be5dfd1a164707fbfc9bb49de23d68b6e15df44 |
|
12-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 46154eb6fd7d0dc908eda5dd52fe16d893e8e008 |
|
11-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add lowering for AVX2 shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c6c7e85a71b3a9a7392beade7e345c1b79b66966 |
|
09-Nov-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
AVX2: Add patterns for variable shift operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bb539bf973bb861ffe8179ac8791fad19448cd52 |
|
09-Nov-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add AVX2 support for vselect of v32i8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0a15035f523a13177b83463779c8b07d8e2873ed |
|
09-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add instruction selection for AVX2 integer comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aaa643c70e6b252ac1f7b3de5950a1d6a6656690 |
|
09-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add AVX2 instruction lowering for add, sub, and mul.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d752e0f7e64585839cb3a458ef52456eaebbea3c |
|
08-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7bc389b6b00e26e07fa5ac64e43d9b06b73828c1 |
|
08-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144052 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 65fd6564b8aedd053845c81ede1ac594acb470e4 |
|
03-Nov-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143206, with fixes. Disallow physical register lifetimes
across calls, and only check for nested dependences on the special
call-sequence-resource register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f6aa6b12f132b41b1337fef14110696458a0f323 |
|
01-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dade3c144818e4888831ed13c1efaef28934ac78 |
|
30-Oct-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fb0dfbbff7fb3a9cff09301c174a65aec7b98760 |
|
30-Oct-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix pr11266.
On x86: (shl V, 1) -> add V,V
Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f3ddef7c51f03945644ad0e69068dfb24d4b092 |
|
29-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Revert r143206, as there are still some failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf923b815d6da97367e3eedab69230918bf128a3 |
|
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 62c1d00dfd38996f381edae55e1028b8e52a1107 |
|
28-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ba60e593012ba9b2a9d20b86733eadca288bcb2 |
|
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 15701f8969fcb36899a75ca2df6fdcbc52141106 |
|
27-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Rename NonScalarIntSafe to something more appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 66bf7430f5586188944e45514abbb04fe3383107 |
|
26-Oct-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fixes an issue reported by -verify-machineinstrs.
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5b2bba61229fb8c262be90ef7705b41cb29edde0 |
|
22-Oct-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix pr11193.
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b4c945716f232ee07ec6fd3e1146175801fa1278 |
|
21-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fd230df463107f6439a866103df6201bb3b0ef40 |
|
20-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 17001ce25cc205ac1cd2604492c2bce310964220 |
|
18-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Fix a bunch of unused variable warnings when doing a release
build with gcc-4.6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 003fad98ccf88c3d44688e8cb73b90d766e4705b |
|
15-Oct-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
SmallVector -> array
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 54a11176f6a5e07e243f1d87ba19ac3f4681976b |
|
14-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 ANDN instruction. Including instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 909652f6876a97d63db20606cd1b37e95d016caf |
|
14-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1203fe7fc80d0fe16a30ae3ddb9b0823b17f39ce |
|
13-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r141854 because it was causing failures:
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8ab1d1e900a5346db019b6a038e3f497bcfb506e |
|
13-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37f2167f15608ff56d202ff21954a456aab6e534 |
|
11-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 LZCNT instruction. Including instruction selection support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dca62d53b74164364b3eaa58df3a284cf86fa016 |
|
11-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a7934dd8e4d61346f7a66736653c1e76750322ad |
|
10-Oct-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
instruction set has no 64-bit SRA support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7c1780c5fe1e57bb57bf1e4bc43e159f03a8b556 |
|
07-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d3e2b78c74ad92bda0836de3e056ee8ec41e446 |
|
28-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 04aa4aee8901faf750120ac4571bee74e5a81a90 |
|
23-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Implement Chris's suggestion of legalizing the various SSE and AVX
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140383 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 17470bee5fd18bb2eae7825dae535c060a34ee7d |
|
22-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
floating point add/sub of appropriate shuffle vectors. Does not
synthesize the 256 bit AVX versions because they work differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c2ccbf108919aeaf5627a1f05fe0ec3f1a32321 |
|
22-Sep-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
The SSE version differences for fmin/fmax are more involved than I thought.
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 74f3501d15c05a92eeb7962da76e97cabc3c7557 |
|
22-Sep-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Don't form min/max nodes if the target is missing SSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 64ac73bb15e510c268479646816ec069ff12cd64 |
|
21-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
fix comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9c6cdf4c1c82842a97e02bef4cef2431ad2e61a3 |
|
21-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 23946fcaaefaf3c1a9d1ef86a3786f622c005f1a |
|
21-Sep-2011 |
Richard Trieu <rtrieu@google.com> |
Change:
assert(!"error message");
To:
assert(0 && "error message");
which is more consistant across the code base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 149f29f1fdd3f806fcc2570173105d27d718bd1d |
|
21-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Simplify max/minp[s|d] dagcombine matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3699261d3f49d65cee6a645c849c41cdca51a01f |
|
20-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ca6f296b483e203b33a050fe52ebab2eae1541b0 |
|
18-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix typos in my prev commit, found by Tobi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 354efd88db96c9662d41c1e154fdee37324802db |
|
18-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
setOperationAction should be done on the return value of the type, not the operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 91e43fd17a2167ef91150a567a072326ea3a3e29 |
|
18-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
When promoting integer vectors we often create ext-loads. This patch adds a
dag-combine optimization to implement the ext-load efficiently (using shuffles).
For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 89af15ee11b0cab2315fe2affa54189619aac8e7 |
|
18-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix typo by changing Lower256IntVETCC to Lower256IntVSETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139993 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6bcd2196e5febb97efe188d0d6de403c577d96fc |
|
17-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Synthesize x86 max/min instructions also for vectors (i.e. produce
maxps and maxpd). This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it. Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0c4b9ff0775c8d15242f65dc4a7ab98f04bd5d68 |
|
15-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change all checks regarding the presence of any SSE level to always
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 322ea080ada5608de41f82127f053f754e459910 |
|
15-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix the code creating VZEXT_LOAD so that it creates the right memoperand. Issue spotted in -debug output. I can't think of any practical effects at the moment, but it might matter if we start doing more aggressive alias analysis in CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5ca0d149158eaa8e30cbd00efa0024149b029bb0 |
|
14-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 809f17fbb1260fdc2e7a7e4ca0fa1aef9a75a6f7 |
|
13-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert the remaining part of r139528. According to PR10907 the bug seems
to be in the VSELECT operands order, so I'll leave the fix for Nadav.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aec5861bb6ace3734163c000cb75ca2e22e29caa |
|
13-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add vselect target support for targets that do not support blend but do support
xor/and/or (For example SSE2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 457d53d9cedb2add5bb80dc7c77a8bcc602877a2 |
|
12-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert the wrong part of r139528, and fix testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8e03a821f96d270556b2ffce15174f2f89d856da |
|
12-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fbad25e12073e2cbe192b2c4cc4f0bbb26148c9c |
|
11-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
CR fixes per Bruno's request.
Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 106f6e7a27a055a353afecf395504dd7fa609f80 |
|
10-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
r139454 activates an assert in a case where we were doing the right thing anyway. Make that explicit, and un-XFAIL the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2db8628085e92dc76852a922ab50bd3b76a5824f |
|
10-Sep-2011 |
Richard Trieu <rtrieu@google.com> |
Fixed an assert from:
assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8ffad56f8eb41c73ecf40d1aa473819eb6915c12 |
|
09-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ee64be9c176a21a6fd86d2c4eebda571f872d4a2 |
|
09-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 814c6ced85e76c0e0ed0ffdea0c95b2f655847bb |
|
08-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX versions of blend vector operations and fix some issues noticed
in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ffe3e7da849a10cdbe8ee4e5b5e243fc48ca0ffd |
|
08-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add X86-SSE4 codegen support for vector-select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 96428cea3d87aaac2e520a0df8f51c857ebf9cbd |
|
06-Sep-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix style issues and typos found by Duncan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4a544a79bd735967f1d33fe675ae4566dbd17813 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4a1b9d82a4872c02bbe648f70a3595006cef8d40 |
|
03-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use existing function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 439f71eb3030dbd5f4441bacdbd04a819a3dab05 |
|
03-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a39ccdb9d4829548756efaaac0d19ebae8b7ff5d |
|
01-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix vbroadcast matching logic to early unmatch if the node doesn't have
only one use. Fix PR10825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c967ad8c888994bddbfda3dd1a042f204de3ffe1 |
|
31-Aug-2011 |
Eric Christopher <echristo@apple.com> |
Rework this conditional a bit.
Patch by Sanjoy Das
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 57d6a5e491d9ca7a022a156d5a878a54b95f857f |
|
31-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Move all MOVSS and MOVSD patterns close to their definitions
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
and update a testcase to check it properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5affa5196f012dc5e4cf69bd8cd2d2f9aeb42e3f |
|
31-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,
whenever AVX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0899f5c62dc63d199185a2d09e434d992975e700 |
|
31-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 151ab3e2f7b69d2b46fdc25cbad9d43f4a827ef1 |
|
30-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Adds support for variable sized allocas. For a variable sized alloca,
code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d07b7ec77203d4dbaf426786912a700cc07f0142 |
|
30-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Adds a SelectionDAG node X86SegAlloca which will be custom lowered
from DYNAMIC_STACKALLOC.
Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added. They
will be custom emitted to inject the actual stack handling code.
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 76927d758657b3a511c73467ec5a7288795c1513 |
|
30-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Emit segmented-stack specific code into function prologues for
X86. Modify the pass added in the previous patch to call this new
code.
This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f3704769bb2e8170769840528869ae5696545481 |
|
29-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2753ae314f656eab6d42c918469ce4ebf422cee5 |
|
27-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Silence GCC warnings and make an array const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 43f51aeca8367ea35adad963c00bd2bc5b8d1391 |
|
26-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6292eceea07d142c10aff86362fdaa12ef7878ea |
|
25-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for AVX 256-bit version of MOVDDUP!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 06ef923d1491b056555ebcb5cb276f8acd322187 |
|
25-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Make isMOVDDUP mask check more strict and update comments!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 07b7f672a066317ffc8224c61dc3b72ce857f24d |
|
25-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af002d840543b5a6c9ec3a1a5c095e08156af454 |
|
25-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f8f90f01747b9c7f6c332d8ec12c92fc5158af96 |
|
25-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4317fe1fc669cf439cf253533323dd974f94ba4b |
|
24-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 327236cd6c211e54fc6288b0ac2b413901cc0611 |
|
24-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Basic x86 code generation for atomic load and store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 13894fa135d33151072ddf5e80abe4540ec2afcd |
|
24-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d8b7dd52525e99b998544bbeecb56907587b25a9 |
|
24-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
permutations. Also tidy up some patterns and make them close to their
instruction definition!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 726ebd6ff3178499e8455ce8433a4310badefe26 |
|
23-Aug-2011 |
Nick Lewycky <nicholas@mxc.ca> |
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a534780da0b369d9e6801922605113ea86b55324 |
|
23-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ac811115910be3f439a4b424839991281622af8 |
|
22-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for breaking 256-bit int VETCC into two 128-bit ones,
avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138271 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0dd80b0d695b94b3baa8ec9195e9b41f3493da4f |
|
18-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR10688. Add support for spliting 256-bit vector shifts when the
shift amount is variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0e6d230abdbf6ba67a2676c118431a4df8fb15dd |
|
17-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a5b262e808ce93cb2817a42b473b99e5bea1000 |
|
17-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Update comments about vector splat handling in x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fc0a7021282a447f4ea2f60e2249da5cdca8d2c3 |
|
17-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Now that we have a canonical way to handle 256-bit splats:
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3b86598cfaa6fa820af67dc0999f2c59a3bcbe84 |
|
16-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Instead of always leaving the work to the generic legalizer when
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:
For this shuffle:
shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
<i32 1, i32 0, i32 7, i32 6>
This was expanded to:
vextractf128 $1, %ymm1, %xmm2
vpextrq $0, %xmm2, %rax
vmovd %rax, %xmm1
vpextrq $1, %xmm2, %rax
vmovd %rax, %xmm2
vpunpcklqdq %xmm1, %xmm2, %xmm1
vpextrq $0, %xmm0, %rax
vmovd %rax, %xmm2
vpextrq $1, %xmm0, %rax
vmovd %rax, %xmm0
vpunpcklqdq %xmm2, %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0
ret
Now we get:
vshufpd $1, %xmm0, %xmm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vshufpd $1, %xmm1, %xmm1, %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 50b37c79203668af8b223710dc6362d399040fdd |
|
15-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
when AVX mode is one. Otherwise is just more work for the type
legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4002d7e1e6e049fe355c53ba5337f215952f2ba4 |
|
12-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix comment!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 53cae1362dca8aa312c3e36c10b106ea7d349f93 |
|
12-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ef8d6999f379c1a551d89b9cce7ca6dc7246fe52 |
|
11-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add a dag combine to xform 256-bit shuffles into simple vector
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 59353b436af38fb6e620b5360251bc733e4ad167 |
|
11-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6236f7f2b66cecdfe18c7c9b77b59cb922617f3f |
|
11-Aug-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add a comment, per Bruno's CR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5e742a3e1b29104fcadc26286f6daa6c450f87d9 |
|
11-Aug-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
[AVX] If the data which is going to be saved is already in two XMM registers
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.
Before:
vinsertf128 $1, %xmm3, %ymm0, %ymm3
vinsertf128 $0, %xmm1, %ymm3, %ymm1
vmovaps %ymm1, 416(%rsp)
After:
vmovaps %xmm3, 416+16(%rsp)
vmovaps %xmm1, 416(%rsp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5f1d8abf759ab3553abe5e7ed40174bc57a985c8 |
|
11-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing
infinite recursive calls in legalize. Fix PR10562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a5134a0ea3ee9e12ae3ca7907b7998e0d7f4d441 |
|
11-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use the splat index to generate the desired shuffle. Otherwise we
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 586272d67ca0cd91e49aa0f03298cc1294128385 |
|
11-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).
Fixes PR9693.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 614061bfb4fea3c1233ecf2676282e063724ae93 |
|
10-Aug-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
When performing a truncating store, it is sometimes possible to rearrange the
data in-register prior to saving to memory. When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 155a92a4918f290e56869bec6360fd8dd6e3950d |
|
10-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix a bug in vpermilps mask checking. Fix PR10560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d40aa24ebf2e67ae0802d15e1ff20373c1e9dc2f |
|
10-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cde4a1abd5c9ee58898e633e3801da4f98468d66 |
|
10-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use fp unpack instructions to unpack int types. Until we have AVX2, this
is the best we can do for these patterns. This fix PR10554.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a511b8e519b5a13c7ace04a0e77df1e2071f2313 |
|
09-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert r137114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e321d7ffc5b06152efc4d6e8e1880e08f5c936a8 |
|
09-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Handle sitofp between v4f64 <- v4i32. Fix PR10559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0f0e0a0e58d00ce75d14bf09a152b1469cbfac27 |
|
09-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Make LowerVSETCC aware of AVX types and add patterns to match them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 328a9d4a0fda149302a8c60bb80cbabe86e922d6 |
|
08-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for several vector shifts operations while in AVX mode. Fix PR10581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd5663c8e4c6fb68e3b45cd4ab327fcc992db481 |
|
04-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious type. Patch by Ivan Krasin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 456a925c6177d65ed63d6518cd7fdad3e6502ae6 |
|
04-Aug-2011 |
Bill Wendling <isanbard@gmail.com> |
Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR.
Fixes PR10527.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1488f76ed95c88dfcf61c193f0e3b715f23838cc |
|
03-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6cdc1f43e6a6dd7ba38a334b0b2f8fa70d4dc4cd |
|
02-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Don't create a ridiculous EXTRACT_ELEMENT. PR10563.
The testcase looks extremely fragile, so I'm adding an assertion which should catch any cases like this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ac5f13fe3f4b79fa188d407dc97de9c9f8fdf368 |
|
02-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Make this kind of lowering to be supported by 256-bit instructions:
shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 55244ceac400dfb170d4df81029ddec9f38ad7cc |
|
01-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise
the legalizer. This commit together with the two previous ones fixes
PR10495.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aed890bee04cce1896a4230cd493774c9700f545 |
|
01-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Teach PreprocessISelDAG to be aware of vector types and to not process them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8af2451679b4e3b7d51e139b5ab2bc5bcb4ba041 |
|
01-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Lower CONCAT_VECTORS to use two VINSERTF128 instructions instead of
using a stack store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 531f19f7677b2e0ab20caaa36c539d398c7b4aea |
|
01-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Since vectors with all ones can't be created with a 256-bit instruction,
avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 55ba816883842e793cdeb32fcb805c4e011b527f |
|
29-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to be
working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6126005259422581d165e406af0e46de19c0b401 |
|
29-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix two tests that I crashed in the previous commits. The mask elts
on the second half must be reindexed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd6353073f8345e76716e5785da5a48bc964eac9 |
|
29-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Match VPERMIL masks more strictly and update the target specific mask
generation to always catch the weird cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2eb4c2bcadfbef9d3c4e2fbb6478ed5dc3d65524 |
|
29-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add DecodeShuffle shuffle support for VPERMIPD variantes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 377baa5bc9901f705f7af97d0bee7a281e264eca |
|
29-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix a bug while generating target specific VPERMIL masks: skip
undef mask elements. This fixes PR10529.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b0a09f4bff8de703f02edb218ee765f7c6831ce |
|
29-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Enable usage of SSE4 extracts and inserts in their 128-bit AVX forms.
Also tidy up code a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9065d4b65f3bd57888d1ea8a2cdb2745a970165d |
|
29-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Cleanup PALIGNR handling and remove the old palign pattern fragment.
Also make PALIGNR masks to don't match 256-bits, which isn't supported
It's also a step to solve PR10489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 15d03fb7f496562d7256ecac69f63e08ee0bfd2e |
|
28-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Invert the subvector insertion to be more likely to be taken as a COPY
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2e64ae410172d937d8c82ef315458ccc6e213c0a |
|
28-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move
a convert pattern close to the instruction definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 14648468011c92a4210f8118721d58c25043daf8 |
|
28-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a44defeb2208376ca3113ffdddc391570ba865b8 |
|
27-Jul-2011 |
Jeffrey Yasskin <jyasskin@google.com> |
Explicitly cast narrowing conversions inside {}s that will become errors in
C++0x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b4ad12b1e499c88deee4d51ade862646bb56303 |
|
27-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Move some code around to open opportunity for more shuffle matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cea34e41fa3bde8a7271c725abc6bb79c31377c9 |
|
27-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
The vpermilps and vpermilpd have different behaviour regarding the
usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 162ee5c725fdfd327243dc11520afb88659f2ed4 |
|
27-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a neat little two's complement hack for x86.
On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.
This code is generated for __builtin_clz and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4ea496846a84918c5e5cdd67ae43d6e2b0a110ea |
|
27-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Recognize unpckh* masks and match 256-bit versions. The new versions are
different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 61cc47e15d1899dac5b2633b2e13f9fcd04d3ce9 |
|
26-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9123c6fea0e07304094230cd8d44af0984ea5c66 |
|
26-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
More movsldup/movshdup cleanup. Rewrite the mask matching function and add
support for 256-bit versions (but no instruction selection yet, coming next).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5f6c440e53bd54f677d8e5f5f0d1b90e8c3109c4 |
|
26-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
More cleanup, subtarget info isn't used here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 863bd9d5cf86e57752975d1ab6779f3116a23b90 |
|
26-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128
This also fixes PR10452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6a32adc4e5e9aae2c6d5d2192ae0c0a01858d8c2 |
|
26-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Handle special scalar_to_vector case: splats. Using a native 128-bit
shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 233fa392453158a41c567b2e445f503d3553b2af |
|
26-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reintroduce r135730, this is indeed the right approach, there is no
native 256-bit vector instruction to do scalar_to_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 63f8dde4827c801499a9887c7a10ba43dac9df08 |
|
25-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask.
Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 23e31011fb1a87715d57b0b8d18d893c9374b134 |
|
22-Jul-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64
too. Patch by Jeff Muizelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6e5fda213fc94e7c3440b9613602b08b8f84e52a |
|
22-Jul-2011 |
Dan Gohman <gohman@apple.com> |
Fix x86's XALUO lowering to return its replacement values instead
of doing the RAUW calls for the overflow value itself. This makes
it more consistent with how the rest of LegalizeDAG works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 558cc5a914118bba0e7843f1878f6137fea88d91 |
|
22-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
GCC complains about the angle of this line.
Remove the escaped newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c41e5935095de27743c99321890e7a9a26d55aab |
|
22-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn't
the way to go. Doing this here will prevent several node matches later,
and would have to force looking all the way through several
VINSERTF128/VEXTRACTF128 chains to optimize simple things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6683efb4cdb12785d19100e69f597156e434b9f4 |
|
22-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
-Inspected a AVX code block added by someone in early Feb. This was never used
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.
- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.
- Fix a fragile test and make it more useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 74dad551d839814cf8f6d8a8e81f2e365837d2b8 |
|
22-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add a DAGCombine for transforming 128->256 casts into a simple
vxorps + vinsertf128 pair of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d088834fb991d96b4b34aaae7ff68dc413ecec9a |
|
22-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Introduce a new function to lower 256-bit vectors which are not
direclty supported and should be promoted and handled by smaller
shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 589b897a31d2e459bb3fae94c550db86d4c984a6 |
|
22-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Rename function to be more specific and be more strict about its usage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dbd4fe2b0ada8014c2c8e042651de5799a1d4c5d |
|
21-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Register v16i16 as valid VR256 register class
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 65b74e1d00eef81b596b4c207fba069aa1eb8214 |
|
21-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9283b668a1d0b41b83292e7b3577ec34a4ed2810 |
|
21-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Improve splat promotion to handle AVX types: v32i8 and v16i16. Also
refactor the code and add a bunch of comments. The final shuffle
emitted by handling 256-bit types is suitable for the VPERM shuffle
instruction which is going to be introduced in a next commit (with
a testcase which cover this commit)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 67727cac2f6b869cc40c050a0c908e6e51814994 |
|
21-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Tidy up code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 203576aa0cb9d8bf2d2e4d910ebab4b7a63262ae |
|
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0e6a052331f674dd70e28af41f654a7874405eab |
|
18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
|
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5bc37dd1319c81e77878003f557c7c852e819f78 |
|
16-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix a couple of things:
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.
2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.
3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.
4) Tidy up code to be more clear and explicit about AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5427edeb68d653ced860ed14f83848ebbb01b64b |
|
14-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Check register class matching instead of width of type matching
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.
Fixes PR10352 and rdar://9777108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d0f3ef807ee4210b97a7a6bc4231e89403145b83 |
|
14-Jul-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
[VECTOR-SELECT]
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 466b022c9956b320a62eac7057eba632c6e512f9 |
|
13-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c1af4772f1f71a955c7c9cfbabba98a2a2c109e4 |
|
13-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
The target specific node PANDN name is misleading. That happens because
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135087 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f29608267baf911ccff7015327839201bd1de529 |
|
08-Jul-2011 |
Julien Lerouge <jlerouge@apple.com> |
Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 33390848a7eca75301d04a59b89b516d83e19ee0 |
|
08-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9bf45d0b1a5d9229978135d48de803edf729599e |
|
08-Jul-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 77ed1353bfd456efd35c2b6e17115ce624d19e92 |
|
08-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.
Fixes PR9675 and rdar://9740801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 31b5f00c4ebd870fc2745f1bed86a7b67f802210 |
|
08-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://9738585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d176af8cf3e3b3fb39385798e25e55449933648c |
|
29-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Use getRegForInlineAsmConstraint instead of custom defining regclasses
via vectors.
Part of rdar://9643582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9bbe4d6c004f25bc491e2583cce7bc91891f68c7 |
|
28-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clean up the handling of the x87 fp stack to make it more robust.
Drop the FpMov instructions, use plain COPY instead.
Drop the FpSET/GET instruction for accessing fixed stack positions.
Instead use normal COPY to/from ST registers around inline assembly, and
provide a single new FpPOP_RETVAL instruction that can access the return
value(s) from a call. This is still necessary since you cannot tell from
the CALL instruction alone if it returns anything on the FP stack. Teach
fast isel to use this.
This provides a much more robust way of handling fixed stack registers -
we can tolerate arbitrary FP stack instructions inserted around calls
and inline assembly. Live range splitting could sometimes break x87 code
by inserting spill code in unfortunate places.
As a bonus we handle floating point inline assembly correctly now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 14d71aac84505fb69b28436a02465df73ea6c6f5 |
|
25-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
Replace dyn_cast<> with cast<> since the cast is already guarded by the necessary check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| df78fcd2d6ba4fd499ead3bdea2fde83dbcecab9 |
|
25-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
Enable tail call optimization in the presence of a byval (x86-32 and x86-64).
<rdar://problem/9483883>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2416da36ace2130607c652a94b814de7e724efeb |
|
24-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
Hoist simple check above more complex checking to avoid unnecessary
overheads. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ef41ff618f2537539b538e6c7bf471c753391f92 |
|
23-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove TargetOptions.h dependency from X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1396c403897e3d3e04fbf59f6c5fe77cbbab74a6 |
|
18-Jun-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused but set variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3a3465b71db858723988f61d72b7135e6dff329b |
|
15-Jun-2011 |
John McCall <rjmccall@apple.com> |
Add a new function attribute, nonlazybind, which inhibits lazy-loading
optimizations when emitting calls to the function; instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call. This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.
Currently only implemented for x86-64, where it turns into a call through
the global offset table.
Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 471e4224809f51652c71f319532697a879a75a0d |
|
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Add a parameter to CCState so that it can access the MachineFunction.
No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f99a4b82a4ff0383138ccaf9e22511eb786168fb |
|
07-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Followup to 132458, omit unnecessary stack copy when x87 input is a
load. rdar://problem/6373334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 865f09334f67edb2000fb38c6c3c28283b88b3bf |
|
04-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Reapply 132424 with fixes. This fixes PR10068.
rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 100c83341676d8aae8fc34b5452563ed08b14f3e |
|
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 251b4a04057a8397791ad3924377888fe4f8a2ad |
|
02-Jun-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert 132424 to fix PR10068.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 84be958ed8db1ba2e0caca8964b7077761694f92 |
|
02-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Omit unnecessary stack copy when x87 input is a load.
rdar://problem/6373334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ec880283b3682982c750c9b78f6a9b4777e21883 |
|
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Recommit 132404 with fixes. rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4abc5fea9c6c3b329fec58840999db06e108e535 |
|
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Revert 132404 to appease a buildbot. rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 10ff0bbdfbeb6f7485979744d16daea4795d45b2 |
|
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Add support for x86 CMPEQSS and friends. These instructions do a
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs. Only profitable when the user wants a materialized 0
or 1 at runtime. rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4fd0dee3bfe8a35bbb62c9e9dea511cbc06cec2d |
|
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
FGETSIGN support for x86, using movmskps/pd. Will be enabled with a
patch to TargetLowering.cpp. rdar://problem/5660695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2aa0f23e1cb5afc96981ecc057980d1958c0be72 |
|
26-May-2011 |
Stuart Hastings <stuart@apple.com> |
Reverting 132105: it broke some LLVM-GCC DejaGNU tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aa4e6afc9be330770e0b5d41e79aa26c3115bcca |
|
26-May-2011 |
Stuart Hastings <stuart@apple.com> |
Correctly handle a one-word struct passed byval on x86_64.
rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b5a55d979c84e100f383ce11c5c5e3b616b9dcc4 |
|
24-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Teach SelectionDAG::isKnownNeverZero to return true (op x, c) when c is
non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.
rdar://9490949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a166089f36cf17cd3733c98000bbe2428011503b |
|
20-May-2011 |
Chad Rosier <mcrosier@apple.com> |
Don't attempt to tail call optimize for Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2e6496026f41d2c05ff038d14df9972f8a27fb94 |
|
20-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert r131664 and fix it in instcombine instead. rdar://9467055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2bbecd8f6d0891087789ea640133bd47167ccea5 |
|
19-May-2011 |
Eric Christopher <echristo@apple.com> |
Oddly people want to use the 'r' constraint for fp constants on x86.
Fixes rdar://9218925
Fixes PR9601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0efaa5e6a184cd6658aebc9873462ee60262a6bd |
|
19-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
crc32 with 64-bit output zeros upper 32-bits. rdar://9467055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 871f6640936b20ef5d2fcf1a414e98265e2852ed |
|
18-May-2011 |
Chad Rosier <mcrosier@apple.com> |
Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b8e0d3412c8319a19f37c1d7000b786c8975bd61 |
|
17-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Clean up the mess created by r131467+r131469.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6db2c2fe216637f4120899c7734a8600c64af0e8 |
|
17-May-2011 |
Stuart Hastings <stuart@apple.com> |
Revert 131467 due to buildbot complaint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 504421e327a5af90dbb42f33086b6db6f6738477 |
|
17-May-2011 |
Stuart Hastings <stuart@apple.com> |
Fix an obscure issue in X86_64 parameter passing: if a tiny byval is
passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 86694297ff146275d74a7312fef1d2f0c41d4b19 |
|
17-May-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
with two different types, in cases where the index and the ptr had different
types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 57f4b0362189c879c54c12892a37670c38dcc7ab |
|
16-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Remove dead code. Fix associated test to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4301222525b565028850030835b8db9ce6d153db |
|
11-May-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
|
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 558692fd0a31d4d3ae4fd09a3a02f80da2e44e5c |
|
20-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
triple component.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2cf711f1e69dc1d00d57814478c8eb12d97ce3a8 |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/X86: Eliminate uses of getDarwinVers().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ee2e0e347e253d103ebbb0c59fcb48ca2d80b7ef |
|
31-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't try to create zero-sized stack objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 050db52276d0a9609ed4e2ba7ccaa76b7b33cdd1 |
|
26-Mar-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make helper static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a2e0762fae050464494a50c8b5d53ac2f4ba738c |
|
24-Mar-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
FIXME: Some cleanups would be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f6c39412dde6e81e586ee78829b3d7fa7422b5da |
|
24-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Revert r128175.
I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d8fa01fbd7f32e2e1f17c9adb57899baae1d0cfe |
|
23-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.
(target-specific branchless method for double-width relational comparisons on x86)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 485fafc8406db8552ba5e3ff871a6ee32694ad90 |
|
21-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7a90e04fc76392972bd8bd0ddee5c934c22c1393 |
|
19-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
to canonicalize IR", it broke a lot of things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ae16d6b9722dd6ff4a606308e3a14d200f3a903f |
|
19-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
switch(x) {
case 1: return f1();
case 2: return f2();
case 3: return f3();
case 4: return f4();
case 5: return f5();
case 6: return f6();
}
}
=>
LBB0_2: ## %sw.bb
callq _f1
popq %rbp
ret
LBB0_3: ## %sw.bb1
callq _f2
popq %rbp
ret
LBB0_4: ## %sw.bb3
callq _f3
popq %rbp
ret
This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:
sw.bb7: ; preds = %entry
%call8 = tail call i32 @f5() nounwind
br label %return
sw.bb9: ; preds = %entry
%call10 = tail call i32 @f6() nounwind
br label %return
return:
%retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
ret i32 %retval.0
This allows codegen to generate better code like this:
LBB0_2: ## %sw.bb
jmp _f1 ## TAILCALL
LBB0_3: ## %sw.bb1
jmp _f2 ## TAILCALL
LBB0_4: ## %sw.bb3
jmp _f3 ## TAILCALL
rdar://9147433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 06cc324b9da1dc8fb7360a560343c28f5e7a940a |
|
19-Mar-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add support for legalizing UINT_TO_FP of vectors on platforms which do
not have native support for this operation (such as X86).
The legalized code uses two vector INT_TO_FP operations and is faster
than scalarizing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b6192d2a9f05e05504470a6df0f4374a0424d7f3 |
|
18-Mar-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Revert r127852; it's apparently causing an ICE on mingw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127909 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b4b8b0cc901ce41a0fb025885897d022eab390f2 |
|
18-Mar-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add a target-specific branchless method for double-width relational
comparisons on x86. Essentially, the way this works is that SUB+SBB sets
the relevant flags the same way a double-width CMP would.
This is a substantial improvement over the generic lowering in LLVM. The output
is also shorter than the gcc-generated output; I haven't done any detailed
benchmarking, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7bbf0ee97c77f7712154648a44ac6eeb57886462 |
|
17-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move more logic into getTypeForExtArgOrReturn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 44579680111b807613703ab401db3b8c0148e36c |
|
17-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ebe8173941238cfbabadb1c63bca7fb7dcf2adbe |
|
16-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byte
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.
This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| de5e101b0db683931132ba4e4d5e13fe0b5c547a |
|
11-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Change the x86 32-bit scheduler to register pressure and fix up the
corresponding testcases back to the previous versions.
Fixes some performance regressions only seen on 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 03d5826164206c67be152d2b6fa62bfa8f5f92c5 |
|
10-Mar-2011 |
Stuart Hastings <stuart@apple.com> |
Revert 127359; it broke lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f26fa48380da12fd8e3d00a7b6baa7ae280870f |
|
09-Mar-2011 |
Stuart Hastings <stuart@apple.com> |
X86 byval copies no longer always_inline. <rdar://problem/8706628>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ca99435e90327990e9db7218e61dfd6ee6b6f8a |
|
09-Mar-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c175a4bd7eaf595cc298bbe3ab4b36fe0333e409 |
|
08-Mar-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1.
Found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127247 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7c2cdb1c05cd94b494729f5e034aec0562165230 |
|
08-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Turn on list-ilp scheduling by default on x86 and x86-64, fix up
testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.
Performance results:
roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated
john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES
Small compile time impact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| be2119e8e2bc7006cfd638a24367acbfda625d16 |
|
07-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e0ef509aeb47b396cf1bdc170ca4f468f799719f |
|
05-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Increased the register pressure limit on x86_64 from 8 to 12
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a20244d1bab2ae6dad1c82c16670d7eb1b3a9087 |
|
02-Mar-2011 |
David Greene <greened@obbligato.org> |
[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement
missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c4db4e5105ccd82df19f141957511f735a9be2d0 |
|
28-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit
and 256-bit forms. Because the number of elements in a vector
does not determine the vector type (4 elements could be v4f32 or
v4f64), pass the full type of the vector to decode routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 95771afbfd604ad003fa3723cac66c9370fed55d |
|
25-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 12d18a07a084b073b768e47b9afe45cc3c6a92f2 |
|
24-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
remove command line option debugging hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fbf05d32b45478696df16277b5c363ef2b9bb7c9 |
|
23-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] General VUNPCKL codegen support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 68e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1 |
|
22-Feb-2011 |
Devang Patel <dpatel@apple.com> |
Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working.
- The debugger needs to be aware of prolog_end attribute attached with line table entries.
- The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 893a882d0944ac0b7dc22aecf8c649fb4dd7d316 |
|
20-Feb-2011 |
Eric Christopher <echristo@apple.com> |
If both operands are loads from stores in memory we can't use movlpd/movlps
since one needs to be a register operand. Just use movss instead of forcing
an operand into a register.
Fixes PR9239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd6e40a4f4b131f9d5454183fa014553c9c8b44c |
|
19-Feb-2011 |
Eric Christopher <echristo@apple.com> |
Fix typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 583b68f34fd9bdb6114fa48dadc8def2ec96edac |
|
17-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Recorganize X86ShuffleDecode into its own library
(LLVMX86Utils.a) to break cyclic library dependencies between
LLVMX86CodeGen.a and LLVMX86AsmParser.a. Previously this code was in
a header file and marked static but AVX requires some additional
functionality here that won't be used by all clients. Since including
unused static functions causes a gcc compiler warning, keeping it as a
header would break builds that use -Werror. Putting this in its own
library solves both problems at once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a901129169194881a78b7fd8953e09f55b846d10 |
|
16-Feb-2011 |
Stuart Hastings <stuart@apple.com> |
Swap VT and DebugLoc operands of getExtLoad() for consistency with
other getNode() methods. Radar 9002173.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0a9481f44fe4fc76e59109992940a76b2a3f9b3b |
|
13-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
Enhance ComputeMaskedBits to know that aligned frameindexes
have their low bits set to zero. This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.
Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively. Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST). The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2fcdfb448debafcea8b22c02e2370ea8a5da8bad |
|
11-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Implement 256-bit vector lowering for SCALAR_TO_VECTOR. This
largely completes support for 128-bit fallback lowering for code that
is not 256-bit ready.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 74a579d9eb1c822f6dd4689671f9ea100666fa03 |
|
10-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Implement 256-bit vector lowering for EXTRACT_VECTOR_ELT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b38126da3dcc924b37715c70fa8abde69e02634 |
|
09-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Implement 256-bit vector lowering for INSERT_VECTOR_ELT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f125a298853e883c7c0630db544460723a610663 |
|
08-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Implement BUILD_VECTOR lowering for 256-bit vectors. For
anything but the simplest of cases, lower a 256-bit BUILD_VECTOR by
splitting it into 128-bit parts and recombining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a5f2601e4d75e6c83d7b2c439f5a25001c342354 |
|
07-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Insert/extract subvector lowering support. This includes a
couple of utility functions that will be used in other places for more
AVX lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3f4be4fb86172e6b87a457b338483efc0c1efd05 |
|
05-Feb-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be enough for caller to allocate one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fb840c9117ce57f9fc6ebde30ff02c8ad1143a01 |
|
05-Feb-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
lib/Target/X86/X86ISelLowering.cpp: Introduce a new variable "IsWin64". No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2763538609fd455d63c192b320c73fb5d48c3e47 |
|
05-Feb-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 66c357dbc44c3f3fe1b789f1ad581bd55f25dea4 |
|
05-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Revert 124910 until clients are ready.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124912 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ffc5533e7c3ace514fc8450b9b804382ff088181 |
|
05-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Add some utilities to insert and extract 128-bit subvectors.
This allows us to easily support 256-bit operations that don't have
native 256-bit support. This applies to integer operations, certain
types of shuffles and various othher things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ccacdc1952d022108d51b1c8270eb85b2b862c9d |
|
04-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Support VSINSERTF128 with more patterns and appropriate
infrastructure. This makes lowering 256-bit vectors to 128-bit
vectors simple when 256-bit vector support is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c38a03eeca3a506577b2d5a29629a81a0cefff03 |
|
03-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] VEXTRACTF128 support. This commit includes patterns for
matching EXTRACT_SUBVECTOR to VEXTRACTF128 along with support routines
to examine and translate index values. VINSERTF128 comes next. With
these two in place we can begin supporting more AVX operations as
INSERT/EXTRACT can be used as a fallback when 256-bit support is not
available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f297c931913ec4285395fa278fa9c9898685c469 |
|
03-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix PR9127 by reversing the operands even if they have more then one use.
Reversing the operands allows us to fold, but doesn't force us to. Also, at
this point the DAG is still being optimized, so the check for hasOneUse is not
very precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2bffee2ee725047137d2523e31db9ecc7b246cbb |
|
01-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Patches to build EFI with Clang/LLVM. By Carl Norum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124639 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e9a7ea68653689966417443b8ac2528c1d9d3ccf |
|
31-Jan-2011 |
Devang Patel <dpatel@apple.com> |
Keep track of incoming argument's location while emitting LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 54d8ebafc7cee5fc55d37f92e93a760e01cab27b |
|
27-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Clean up the code to configure target lowering for AVX. Specify
how to lower more/new operations. This is a prerequisite for adding
additional AVX lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cfe33c46aa50f04adb0431243e7d25f79b719ac6 |
|
26-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR. Eventually this
will get matched to VINSERTF128 if AVX is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 91585098eff1f0acdefa2667e091742b60dcbf15 |
|
26-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Support EXTRACT_SUBVECTOR on x86. This provides a default
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7754f85885f8a961cb403ef13ab39583492d2b1e |
|
26-Jan-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: Tweak win64's tailcall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e5fffe9c3fa402cb5d5167327783f82b86f52b8f |
|
26-Jan-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9cd3da47f9d67d345a94dddf85fcbb3ff2dd7200 |
|
16-Jan-2011 |
Chris Lattner <sabre@nondot.org> |
fix PR8981, a crash trying to form a conditional inc with a floating point compare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
|
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c9df025e33ac435adb3b3318d237c36ca7cec659 |
|
10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 55d42003368c57d3a41c5f464d39b8440050d558 |
|
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a5e1362f968568d66d76ddcdcff4ab98e203a48c |
|
07-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert r122955. It seems using movups to lower memcpy can cause massive regression (even on Nehalem) in edge cases. I also didn't see any real performance benefit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 461f1fc359dff438dad25e809499845b10a3d032 |
|
06-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Use movups to lower memcpy and memset even if it's not fast (like corei7).
The theory is it's still faster than a pair of movq / a quad of movl. This
will probably hurt older chips like P4 but should run faster on current
and future Intel processors. rdar://8817010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0521928ae7cc492f3f45ef0e0cedc349102489c5 |
|
06-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e915ff30cd15f71ed9bb87ba0bf6c7d8b5a84747 |
|
23-Dec-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Lower a select directly to a setcc_carry if possible.
int test(unsigned long a, unsigned long b) { return -(a < b); }
compiles to
_test: ## @test
cmpq %rsi, %rdi ## encoding: [0x48,0x39,0xf7]
sbbl %eax, %eax ## encoding: [0x19,0xc0]
ret ## encoding: [0xc3]
instead of
_test: ## @test
xorl %ecx, %ecx ## encoding: [0x31,0xc9]
cmpq %rsi, %rdi ## encoding: [0x48,0x39,0xf7]
movl $-1, %eax ## encoding: [0xb8,0xff,0xff,0xff,0xff]
cmovael %ecx, %eax ## encoding: [0x0f,0x43,0xc1]
ret ## encoding: [0xc3]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d6fe13efc9bcb69d3479e32f8eace933c5bd2d5 |
|
21-Dec-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add some x86 specific dagcombines for conditional increments.
(add Y, (sete X, 0)) -> cmp X, 1; adc 0, Y
(add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y
(sub (sete X, 0), Y) -> cmp X, 1; sbb 0, Y
(sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y
for
unsigned foo(unsigned a, unsigned b) {
if (a == 0) b++;
return b;
}
we now get:
foo:
cmpl $1, %edi
movl %esi, %eax
adcl $0, %eax
ret
instead of:
foo:
testl %edi, %edi
sete %al
movzbl %al, %eax
addl %esi, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 672fb6225b381b4dcb2e88fccb79d928eaabf82c |
|
20-Dec-2010 |
Nate Begeman <natebegeman@mac.com> |
Implement feedback from Bruno on making pblendvb an x86-specific ISD node in addition to being an intrinsic, and convert
lowering to use it. Hopefully the pattern fragment is doing the right thing with XMM0, looks correct in testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 23a0199f05fe61c4bde921d5729ed2b927657bcb |
|
20-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results,
the same as setcc. Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS). This is
a step towards finishing off PR5443. In the testcase in that bug we now get:
movq %rdi, %rax
addq %rsi, %rax
sbbq %rcx, %rcx
testb $1, %cl
setne %dl
ret
instead of:
movq %rdi, %rax
addq %rsi, %rax
movl $0, %ecx
adcq $0, %rcx
testq %rcx, %rcx
setne %dl
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d8ff7eca8cea6313e1090903091d79b19d726c35 |
|
20-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
use for loop over types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5b85654844d673939bd1ceba66cd1f5022fd7c0d |
|
20-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which
their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.
We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.
With the previous series of changes, this causes no changes in the testsuite, woo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a0fd0d5b27257c7397e9f6e4234cd600683c9248 |
|
20-Dec-2010 |
Mon P Wang <wangmp@apple.com> |
Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types
has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c19d1c3ba2b216f0f91d71cf6fc2e983fc995854 |
|
19-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
improve the setcc -> setcc_carry optimization to happen more
consistently by moving it out of lowering into dag combine.
Add some missing patterns for matching away extended versions of setcc_c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 481eebc9315a3231355d33121f8d0afcdddac5e0 |
|
19-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
simplify some code to just reuse a setcc if we can instead of
going through the CSE maps to get it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a786eb030bbcbadc2fc7713b8933e6e8b383b28 |
|
19-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
now that generic vector types aren't selected onto MMX operations,
we don't need -disable-mmx anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e019ec168be3c2b54454fe73b4a6d66abf5a7516 |
|
19-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
reduce copy/paste programming with the power of for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a34b3cf953867b0802f3c19ee57e574277003cd7 |
|
19-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
X86 supports i8/i16 overflow ops (except i8 multiplies), we should
generate them.
Now we compile:
define zeroext i8 @X(i8 signext %a, i8 signext %b) nounwind ssp {
entry:
%0 = tail call %0 @llvm.sadd.with.overflow.i8(i8 %a, i8 %b)
%cmp = extractvalue %0 %0, 1
br i1 %cmp, label %if.then, label %if.end
into:
_X: ## @X
## BB#0: ## %entry
subl $12, %esp
movb 16(%esp), %al
addb 20(%esp), %al
jo LBB0_2
Before we were generating:
_X: ## @X
## BB#0: ## %entry
pushl %ebp
movl %esp, %ebp
subl $8, %esp
movb 12(%ebp), %al
testb %al, %al
setge %cl
movb 8(%ebp), %dl
testb %dl, %dl
setge %ah
cmpb %cl, %ah
sete %cl
addb %al, %dl
testb %dl, %dl
setge %al
cmpb %al, %ah
setne %al
andb %cl, %al
testb %al, %al
jne LBB0_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b65c175d32510d32aa556d1db5e6782b411d192c |
|
17-Dec-2010 |
Nate Begeman <natebegeman@mac.com> |
Add support for matching psign & plendvb to the x86 target
Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ea8ee7c76b8d8754d81072e691caf25d23289e3 |
|
10-Dec-2010 |
Nate Begeman <natebegeman@mac.com> |
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d8c0536651af94513b60061f0ea51b948e856374 |
|
09-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite the darwin tlv support to use a chain and return to copying
the output to the correct register. Fixes a hidden problem uncovered
by the last patch where we'd try to DAG combine our MVT::Other node
oddly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2040961f893815e597e831110e0cef391141473a |
|
09-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Stop confusing people, it's not really a chain, or a tumor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8bce7cc3bfa7d5b47ca0b05f7c663068d1da592a |
|
09-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Remove extraneous copy from DAG conversion for darwin tls. This was
popping up at O0 when it wasn't folded and the fast allocator would
complain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9637d5b22ec655d9b2f6cdb5fb23b0ce0ec9c8a5 |
|
05-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Teach X86ISelLowering that the second result of X86ISD::UMUL is a flags
result. This allows us to compile:
void *test12(long count) {
return new int[count];
}
into:
test12:
movl $4, %ecx
movq %rdi, %rax
mulq %rcx
movq $-1, %rdi
cmovnoq %rax, %rdi
jmp __Znam ## TAILCALL
instead of:
test12:
movl $4, %ecx
movq %rdi, %rax
mulq %rcx
seto %cl
testb %cl, %cl
movq $-1, %rdi
cmoveq %rax, %rdi
jmp __Znam
Of course it would be even better if the regalloc inverted the cmov to 'cmovoq',
which would eliminate the need for the 'movq %rdi, %rax'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b20e0b1fddfd9099e12b84a71fbc8ccff5a12b10 |
|
05-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 96908b17ae7df4c838853a41df9a4c034b435446 |
|
05-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
generalize the previous check to handle -1 on either side of the
select, inserting a not to compensate. Add a missing isZero check
that I lost somehow.
This improves codegen of:
void *func(long count) {
return new int[count];
}
from:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
## encoding: [0xeb,A]
to:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
cmpq $1, %rdx ## encoding: [0x48,0x83,0xfa,0x01]
sbbq %rdi, %rdi ## encoding: [0x48,0x19,0xff]
notq %rdi ## encoding: [0x48,0xf7,0xd7]
orq %rax, %rdi ## encoding: [0x48,0x09,0xc7]
jmp __Znam ## TAILCALL
## encoding: [0xeb,A]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a2b5600e615feb71840cd66d2676a8938daf737e |
|
05-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Improve an integer select optimization in two ways:
1. generalize
(select (x == 0), -1, 0) -> (sign_bit (x - 1))
to:
(select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
2. Handle the identical pattern that happens with !=:
(select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
cmov is often high latency and can't fold immediates or
memory operands. For example for (x == 0) ? -1 : 1, before
we got:
< testb %sil, %sil
< movl $-1, %ecx
< movl $1, %eax
< cmovel %ecx, %eax
now we get:
> cmpb $1, %sil
> sbbl %eax, %eax
> orl $1, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1292c226458b68a119d3a387a0527f453b2065c2 |
|
04-Dec-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add patterns for the x86 popcnt instruction.
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
supports SSE4.2 (nehalem) or SSE4A (barcelona).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 983839609ffa589cda60efaea847eecede77b524 |
|
04-Dec-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1bf891ae6e174ac92c1091be0c62891f4676beb8 |
|
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix and re-enable tail call optimization of expanded libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 38169788fa26464353f0010f66f8b933c3d8c4bc |
|
01-Dec-2010 |
Duncan Sands <baldrick@free.fr> |
I don't think it makes any sense to assert that the target supports SSE3 here.
The user (i.e. whoever generated a call to the intrinsic in the first place) is
essentially asking for a particular instruction to be placed in the assembler.
If that instruction won't execute on the target machine, that's their problem
not ours. Two buildbots with processors that don't support SSE3 were barfing
on the apm.ll test in CodeGen/X86 because of this assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 28cd48fffbe2e31184332674429d6d087ad3631f |
|
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Speculatively disable x86 portion of r120501 to appease the x86_64 buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3d2125c9dbac695c93f42c0f59fd040e413fd711 |
|
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable sibling call optimization of libcalls which are expanded during
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 41c902fdbe8dac2a2104c374a121c782d3317092 |
|
30-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Fix insertion point in pcmp expander.
While I'm there, clean up too many \n even for me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 82be220092cfb9d432c5a6da1bd5e8c56dc21d4d |
|
30-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Fix some cleanups from my last patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 228232b2821f8e7f9c0b874ad733414bda183db6 |
|
30-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite mwait and monitor support and custom lower arguments.
Fixes PR8573.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d652dbe72044b07a681b579a0a938c613ef15ae8 |
|
28-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5bf7c534cf057a52f30624743841fadd241c4dbb |
|
27-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Lower TLS_addr32 and TLS_addr64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
|
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
|
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1e61e69d401045c54b15815f15a0fdb3ca56a9b5 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add targetoperand flags for jump tables, constant pool and block address
nodes to indicate when ha16/lo16 modifiers should be used. This lets
us pass PowerPC/indirectbr.ll.
The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC. I have a terrible hack in the meantime, but this will have
to be revisited at some point.
Last major conversion item left is global variable references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 142b531e024c7b814df74951b378b9e3e11d0d42 |
|
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
move the pic base symbol stuff up to MachineFunction
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4fd0ea01660d7e447f072a1032abf0d7537821bf |
|
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
simplify getPICBaseSymbol a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 948cf0289f8280f7e069603837d56c862515c6e1 |
|
13-Nov-2010 |
Peter Collingbourne <peter@pcc.me.uk> |
Recognise 32-bit ror-based bswap implementation used by uclibc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 983611836cd1edec8d1b8032e0539b6ed80461d6 |
|
13-Nov-2010 |
Peter Collingbourne <peter@pcc.me.uk> |
Support ; as asm separator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0e03456a6592dd8c628a17a37d2b95467f053037 |
|
12-Nov-2010 |
Dale Johannesen <dalej@apple.com> |
Remove possibly useful info from comment, per Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cdfad36b401be6fc709ea4051f9de58e1a30bcc9 |
|
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4590766580ff94e3a7fa95cda7b602b23f14843e |
|
31-Oct-2010 |
Duncan Sands <baldrick@free.fr> |
Factorize the duplicated logic for choosing the right argument
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 44ab89eb376af838d1123293a79975aede501464 |
|
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6dad10ed66b3340a57d991d1081a85308942a04f |
|
27-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
x86-Win32: Switch ftol2 calling convention from stdcall to C.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d155d7e428e0e14b520dddbf00b6745d7eb2d7b8 |
|
26-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
An stdcall function calling a non-stdcall function
cannot use tailcall. PR 8461.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1e1ca0b56da1acaa6f6515d14df4ba6e6c0a9a9e |
|
21-Oct-2010 |
Duncan Sands <baldrick@free.fr> |
Add parentheses to pacify gcc, which warns otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e9c253e0bc01fd50bf788efb62093a5fa6ef5849 |
|
21-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e93d99cf0742eebab859022e4cfdcf03cb9d5dfa |
|
20-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Remove Synthesizable from the Type system; as MMX vector
types are no longer Legal on X86, we don't need it.
No functional change. 8499854.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 94f7eeb84d8d25c647e560f352912ca1017ca10f |
|
19-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
X86: Add MS-CRT libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87b86658780b8ce2db1b4f3c675c4b9f51bf0d44 |
|
19-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Fix Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52b45056b2dc9246f732aa9cf655b6b2cb355c93 |
|
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Combine these together - should probably have some text associated
that says what why what we just asserted is wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 65b65d6ca49fe1c55722053d3ed2549e1399e717 |
|
12-Oct-2010 |
Nick Lewycky <nicholas@mxc.ca> |
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 320afb8c818b5cd5b9d4fcd0dba83ba3384ed4b4 |
|
12-Oct-2010 |
Dan Gohman <gohman@apple.com> |
Initial va_arg support for x86-64. Patch by David Meyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a2cf3b4d9c6cac6123417aaa4aae3a9e4f7bb48 |
|
11-Oct-2010 |
Andrew Trick <atrick@apple.com> |
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 335b806c627bf04eb079009abcc41e5d36f2ef22 |
|
11-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 92bf38c956f60b99d1888b289755bcaa4ab945f5 |
|
11-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
X86: MinGW should always use libgcc on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1802a9f8fe657e270fe3fb2c9ca324fe3aec4591 |
|
11-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ec38de2ca87d738aa3d4d5c36740f29f1a9f27de |
|
11-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Fix Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ec37b00b17fba355ac6d4a1bee918d3004c54584 |
|
08-Oct-2010 |
Cameron Esfahani <dirty@apple.com> |
Recommit 116056, now with the missing file...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5900201aa787d4196130cc9e538fe35ae3051a15 |
|
08-Oct-2010 |
Andrew Trick <atrick@apple.com> |
reverting 116056: win64_params.ll may need to be conditionalized?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d7b8d91d4a2a284bbe9ef6f32b3c25daa7ea0513 |
|
08-Oct-2010 |
Cameron Esfahani <dirty@apple.com> |
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 835580fc3ada684cd30e21c1367ea880d2237a0f |
|
07-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e7beda183db01deffb626bc154b42a0bac27b1de |
|
04-Oct-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
va_args support for Win64.
Patch by Cameron!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0488fb649a56b7fc89a5814df5308813f9e5a85d |
|
01-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Massive rewrite of MMX:
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 80945784f916135c06012b3c68de689cc44964a5 |
|
27-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
improve indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 722d315ac941a8b89715288c6a1c6a9f06f7e33c |
|
27-Sep-2010 |
Eric Christopher <echristo@apple.com> |
This code should never fire on non-darwin subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c4510511573ca6f9bcba941427d29d93e3863180 |
|
24-Sep-2010 |
Dale Johannesen <dalej@apple.com> |
We can't return SSE/MMX vectors if SSE is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eafca4e2b27d5b63d4375291b6db20d66e663c31 |
|
22-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Attempt to fix llvm-gcc build. It was crashing when building gcov.o for an
ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f93b90c5dfe98958eb43715a6e674565ab162502 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 492a43e6f64997a0ab26ef047dced193931fda85 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the last 4 X86ISD nodes that should have memoperands to have them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2156b79c493751f165d445535f8b598b4769b3e8 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
can access the stack due to how it is generated though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0729093cd7e15ed6469e50b74f0edd7f205b50ff |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
used with stack slots, but hey, lets be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8864155a35eb59fbebfd1822aaf224128b5c5d23 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give VZEXT_LOAD a memory operand, it now works with segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 93c4a5bef780e43552d3b9d702756d3acb7801d2 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bc146b0a4dcee601459eee943b4133d3cf63f1dd |
|
21-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114473 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fc448ff89b4fb7721de9da0b96fd00c13160c4c7 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert a couple more places to use the new getStore()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c004eec71b49ae13ee4d9f859c61cdb9ed092b22 |
|
21-Sep-2010 |
Owen Anderson <resistor@mac.com> |
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.
This fixes <rdar://problem/8449754>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8026a9d3eef3ae30d4ec16a17b7d60d287ddf25d |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate some uses of the getStore overload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d1c24ed81c43635d00ff099844a9d0614021a72b |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the targets off the non-MachinePointerInfo of getLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e8639036b1fb3a5b5e9589fe4e9f2ee1b77c36bd |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
it's more elegant to put the "getConstantPool" and
"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 51abfe490b62a936dc87462a2b1ddc450651ac6e |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
update the X86 backend to use the MachinePointerInfo version of one
of the getLoad methods. This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e72f2027e9116c55a5b39ac72732df8d6c45d37c |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 59db5496f4fc2ef6111569e542f8b65480ef14c1 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert targets to the new MF.getMachineMemOperand interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eac6e1d0c748afc3d1496be0753ffbe5f5a4279b |
|
13-Sep-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Added skeleton for inline asm multiple alternative constraint support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0a7dd4fa4062eb4e452864e049ca3c8a6db8b8d7 |
|
08-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Minor change. Fix comments and remove unused and redundant code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1485cc2bb386aa07c2598f65e4cc10edd2f0a065 |
|
08-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
x86 vector shuffle lowering now relies only on target specific
nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 90462b4ae15950b987eb778426f5be727286f3b3 |
|
07-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0d1340b181cd1defddfe7afb51a17124ad61ea1e |
|
07-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Move code around to prepare for moving some of the logic together to another function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d8dd5757e0e31c55bb15498aa1d75fad08850c5a |
|
07-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Add an MVT::x86mmx type. It will take the place of all current MMX vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 58277b17c3c90512237cb84ca567e8884823aa59 |
|
07-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113247 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 673bf78bb5104e28d7295bbca87ebdc2c237353e |
|
07-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove now useless check, because the code can be matched below, no need to leave it for isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 67fc1e76d4561635dbd56a79285e77c1ed595a30 |
|
07-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Minor change. Since the checks are equivalent, use isMMX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2eb63dfa0a618fe58b9335ceb4e2b67ab5c9f679 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 828f6ae03c214609fec1fce8cd32f4fcf2645f57 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
make explicit that we not handle several mmx shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aace0f295b0e2467a38424aa7ead34de09b3f37d |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c800c0d25f70e445ff4f17bf720ae5d2f942e695 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Emit target specific nodes to handle splats starting at zero indicies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bbfc31012bad41d1eda6d65c0081760e8fdbc323 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Emit target specific nodes for isPSHUFHWMask and isPSHUFLWMask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c827f5ae1d2afe81af719ba6c4ab31b731e3616 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Emit target specific nodes for isSHUFPMask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d344f28b9d2e07f994a425a25ba7dc9a1299c3a4 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Previous isMOVLMask matching already emits targets nodes, remove check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e09abcd3c46f7ff5e56ea3e4483b5760539e4c0a |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
One more check from the original isShuffleMaskLegal goes away
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b733996110921028df24f72325580ba856a98c86 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove a duplicated but useless check that i've inserted in the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a22c84571ac97aaafaed2ff38f1ee9f29791320d |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Refactor some code and remove the extra checks for unpckl_undef and unpckh_undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 43c05744b58ff24fab998080680b5ba1e2120dec |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove check for unpckh mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ef3adb3243f9a11ceeba3ebca2fd37c2c321da60 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove check for unpckl mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7256e22f77dcfda7e8afd3f819230fd8329a04d7 |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start
checking each standalone condition and decide whether emit target
specific nodes or remove the condition if it's already matched before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e8f279cbd45a9f65f211830940b980a850e856be |
|
04-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply considered harmfull part of rr112934 and r112942.
"Use target specific nodes instead of relying in unpckl and
unpckh pattern fragments during isel time. Also place a
depth limit in getShuffleScalarElt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a4460606e6fb3323182b3259c40e214753d9367 |
|
03-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reintroduce a simple function refactoring done in r112934, also without any functionality changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| be8b084d8ab51ee7f402cad3b56347c8a260d42c |
|
03-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply piecies of r112942 and r112934 which don't do
functional changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b3e0669b8e202551743c93454a99a3eee5db323b |
|
03-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply Fix comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 31394220586783bb95bf112556d75906e3d197b2 |
|
03-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced
some infinite loop and select failures.
- Apologies for eager reverting, but its branch day.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 78541f258c8b7c00c5e06e8bae39dd3a65eddf94 |
|
03-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r112938 "Fix comment", which depends on r112934, which introduced some
infinite loop and select failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a87ccce95be29e5b5a8567febaf0597fb165ecc7 |
|
03-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh
mask pattern fragment", which depends on r112934, which introduced some infinite
loop and select failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4b0c9f3e732f671003dfd1ad75d1cd42e8775444 |
|
03-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 01f0847ce8d15f547c762c1781b3b1883847f030 |
|
03-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5e5342b0a8e9484b660e15e9a6568b05c0d4cea4 |
|
03-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Use specific nodes to match unpckl masks.
- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c7c62bb3caed31fb1e43a9f6c3b833627388d2fc |
|
03-Sep-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Revert win64 changes. They seem to be incomplete
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f4fad99ea776906c853f0c4eef0eb0f7d2dc579 |
|
03-Sep-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly allocate win64 shadow reg area.
Patch by Jan Sjodin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3722f007b6f60f7556c721d6ca3e10bfd171141d |
|
02-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Replace unpckl_undef and unpckh_undef matching with target specific opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd69db858c82011f515232523d2910c906ed6415 |
|
02-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Move condition out to prepare for more matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ad10fb2b56d296a5f7458a58f40d98ee69af6099 |
|
02-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d00bfe1f8dded563fa32a045d6d74ec1c25427dd |
|
02-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
become more strict about when it's safe to use X86ISD::MOVLPS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4783a3ee13a2a63d5618405cf6ae0a4afaa97e63 |
|
02-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert r112689, avoid those kind of checks cause they mess up with mmx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 56098f5d26ed05401bd889960deffa72eb7bbce9 |
|
01-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9cfad89a680e50568ad8f6ff243e7409f42bb2d7 |
|
01-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
minor change, simplify some logic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e654b56eb1e7870b63392a4e8a92f55d1b60f45e |
|
01-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Move some functions around so they can be used for some other to come function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 013bb3dee9d3cb4f2d83e00c3718eb40e2b4d149 |
|
01-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5023ef281c719914681e4f2b12d4d120923d8127 |
|
01-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use x86 specific MOVSHDUP node and add more patterns to match it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7ff30bb1a5b04e52a0b2a3a2cb961eb34a7dde56 |
|
31-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f2db5b48d0a4f0800e83d8c3cd6dc5ad6a551bd6 |
|
31-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 20a07f422de575156f194ca02d4920f8c084e992 |
|
31-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the handling of those nodes when seeking for scalars inside vector shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 24faf611a33900b225c636f908eb30234215af21 |
|
28-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix the buildvector->insertp[sd] logic to not always create a redundant
insertp[sd] $0, which is a noop. Before:
_f32: ## @f32
pshufd $1, %xmm1, %xmm2
pshufd $1, %xmm0, %xmm3
addss %xmm2, %xmm3
addss %xmm1, %xmm0
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm3, %xmm0
ret
after:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movdqa %xmm2, %xmm0
insertps $16, %xmm3, %xmm0
ret
The extra movs are due to a random (poor) scheduling decision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ddcc430401f0d16bee17b2afb52dcaa2f480f8b |
|
28-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix the BuildVector -> unpcklps logic to not do pointless shuffles
when the top elements of a vector are undefined. This happens all
the time for X86-64 ABI stuff because only the low 2 elements of
a 4 element vector are defined. For example, on:
_Complex float f32(_Complex float A, _Complex float B) {
return A+B;
}
We used to produce (with SSE2, SSE4.1+ uses insertps):
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $16, %xmm2, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm0
addss %xmm1, %xmm0
pshufd $16, %xmm0, %xmm1
movdqa %xmm2, %xmm0
unpcklps %xmm1, %xmm0
ret
We now produce:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movaps %xmm2, %xmm0
unpcklps %xmm3, %xmm0
ret
This implements rdar://8368414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6e80e449261e259d41a247603228be7802c112d1 |
|
28-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
improve comments in the unpcklps generating logic, introduce
a new EltStride variable instead of reusing NumElems variable
for a non-obvious purpose. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 27f1279411fd7e7386869e6235e4b395b739e921 |
|
28-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Clean up the logic of vector shuffles -> vector shifts.
Also teach this logic how to handle target specific shuffles if
needed, this is necessary while searching recursively for zeroed
scalar elements in vector shuffle operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c52bedba5489aedad7013067ae1fd5b49b5fe525 |
|
27-Aug-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly handle passing of FP stuff to varargs function on Win64:
value should be copied to the corresponding shadow reg as well.
Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af57738f008e56bceac2e600dd741fefbffce973 |
|
26-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
zap the now unused MVT::getIntVectorWithNumElements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8306968c147d5861d8a53fba86ac0fbf5c050b84 |
|
26-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 97a2a56f433b35ab60431e7681cf1b5c97c71529 |
|
26-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix sse1 only codegen in x86-64 mode, which is something we
apparently try to support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3e60a232c130990035e86c11584856b5adc25bfa |
|
25-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert this for now, PUNPCKLDQ dont operate on v4f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9f7f83b861f6d03df81c440364ba10f55f6447d5 |
|
25-Aug-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there.
Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f76c55aa407050d4fd98f13adb9dba6a7a4c9857 |
|
25-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
PUNPCKLDQ should also be used for v4f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7338bbd32af40b664f6bb744f3e8db8f0dc90fb4 |
|
25-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
teach lowering to get target specific nodes for pshufd, emulating the same isel behavior for now, so we can pass all vector shuffle tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 92b651fb199557b9e54c7263e83c34ab39eb644f |
|
24-Aug-2010 |
Dan Gohman <gohman@apple.com> |
Fix X86's isLegalAddressingMode to recognize that static addresses
need not be RIP-relative in small mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8878e21fe6ba26b0eb83bcd47ab07cff175141e2 |
|
24-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111890 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3efc0778c9baacc3dff4c50b62396d14f2420ba5 |
|
23-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Start using target speficic nodes for shuffles: pshufhw and pshuflw
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4654a07e254b13d168e5470394c4d954cc260d03 |
|
23-Aug-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Revert invalid r111792. Jump tables are not broken on x86-64 / coff,
it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3464cec4d8cf09f9e1b3b9af9ab7b7d4a6a69a59 |
|
23-Aug-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Workaround broken jump tables on x86-64 COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf8154a4395bf941f57f6453503a850cb9805a64 |
|
21-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3157ef1c13376f669a32bc152f2c3000480cedd3 |
|
21-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This is the first step towards refactoring the x86 vector shuffle code. The
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.
The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3a1e54a6b97f81d61d5de38d220b2b75746ae481 |
|
17-Aug-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
More fixes for win64:
- Do not clobber al during variadic calls, this is AMD64 ABI-only feature
- Emit wincall64, where necessary
Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c0b2a2018ad194de6a9cf46a2a5936319787f1b1 |
|
14-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Rework how the non-sse2 memory barrier is lowered so that the
encoding is correct for the built-in assembler.
Based on a patch from Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 132929aa9e1b0b00d2643408d88239c20f1e7ed7 |
|
14-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
improve indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bb0a9489e00d93e3944da0c7458f46e9ccb32c9f |
|
13-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix comment to reflect code, and remove an unused argument
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8c05a850f43cda2e62ac48562281f504ab763d59 |
|
12-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Begin to support some vector operations for AVX 256-bit intructions. The long
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d881627d3307ef3379627de4eeb65395867a7b08 |
|
11-Aug-2010 |
Dan Gohman <gohman@apple.com> |
Use ISD::ADD instead of ISD::SUB with a negated constant. This
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.
Also, use getCopyFromReg instead of getRegister to read a
physical register's value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 045573ce21282ee7d1c58e57d00a77ede8c732da |
|
11-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX matching patterns to Packed Bit Test intrinsics.
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.
This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 405f11b3003076aa69d53277ea4639d7deec4752 |
|
10-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support AVX 256-bit load and store intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ac09835a2282412b90c634e71081db22cd5521f3 |
|
06-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support very basic (doesn't include ABI support in the front-end, varags, ...) 256-bit argument passing and return for AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b6729dc0ef7556ced99e79a7d37ec4d7f6dd75b4 |
|
05-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Make x86-64 membarriers work without sse and clean up some of the
uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 98f985607b9521935efbb537cc475724b97449e9 |
|
30-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support all 128-bit AVX vector intrinsics. Most part of them I already
declared during the addition of the assembler support, the additional
changes are:
- Add missing intrinsics
- Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file.
- Duplicate some patterns to AVX mode.
- Step into PCMPEST/PCMPIST custom inserter and add AVX versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b2eeed7464e3492833bb7a495e78a9f031621653 |
|
29-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r109652, and remove the offending assert in loadRegFromStackSlot instead.
We do sometimes load from a too small stack slot when dealing with x86 arguments
(varargs and smaller-than-32-bit args). It looks like we know what we are doing
in those cases, so I am going to remove the assert instead of artifically
enlarging stack slot sizes.
The assert in storeRegToStackSlot stays in. We don't want to write beyond the
bounds of a stack slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c010ec85185e2f1d671ac17a387b55228199d5b |
|
28-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Create a fixed stack object for varargs that is as large as any register.
The size of this object isn't used for anything - technically it is of variable
size.
This avoids a false positive from the assert in
X86InstrInfo::loadRegFromStackSlot, and fixes PR7735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 51409214d7471328df2e92e0a8f9d05221fe0e6f |
|
28-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
Implement a vectorized algorithm for <16 x i8> << <16 x i8>
This is about 4x faster and smaller than the existing scalarization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bdcb5afb77547337ba148ce24d5e1046c0b25ced |
|
28-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches.
For:
define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
%shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1]
%tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp2
}
We get:
_shl: ## @shl
pslld $23, %xmm1
paddd LCPI0_0, %xmm1
cvttps2dq %xmm1, %xmm1
pmulld %xmm1, %xmm0
ret
Instead of:
_shl: ## @shl
pshufd $3, %xmm0, %xmm2
movd %xmm2, %eax
pshufd $3, %xmm1, %xmm2
movd %xmm2, %ecx
shll %cl, %eax
movd %eax, %xmm2
pshufd $1, %xmm0, %xmm3
movd %xmm3, %eax
pshufd $1, %xmm1, %xmm3
movd %xmm3, %ecx
shll %cl, %eax
movd %eax, %xmm3
punpckldq %xmm2, %xmm3
movd %xmm0, %eax
movd %xmm1, %ecx
shll %cl, %eax
movd %eax, %xmm2
movhlps %xmm0, %xmm0
movd %xmm0, %eax
movhlps %xmm1, %xmm1
movd %xmm1, %ecx
shll %cl, %eax
movd %eax, %xmm0
punpckldq %xmm0, %xmm2
movdqa %xmm2, %xmm0
punpckldq %xmm3, %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dee81010eb4f932b76dd3f64eacba13b55d2d105 |
|
26-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
On x86, f32 / f64 nodes share the same registers as 128-bit vector values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 70017e44cdba1946cc478ce1856a3e855a767e28 |
|
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an ILP scheduler. This is a register pressure aware scheduler that's
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.
On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c76d23f2e2550c60aaa26ec23711aecebea7f533 |
|
23-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
The only supported calling convention for X86-64 uses
SSE, so we can't return floating point values if this
is disabled. Detect this error for clang.
With SSE1 only, f64 is a problem; it can be done, but
neither llvm-gcc nor clang has ever generated correct
code for it. Since nobody noticed this I think it's
OK to treat it as an error for now.
This also handles SSE-sized vectors of floating point.
8207686, 8204109.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9a9d275dc7897dfba7f41ce1b3770ca27ac149e8 |
|
22-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Custom lower the memory barrier instructions and add support
for lowering without sse2. Add a couple of new testcases.
Fixes a few libgomp tests and latent bugs. Remove a few todos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 90eb4024ba1ff2b945b0c157910dd41cd4e74575 |
|
22-Jul-2010 |
Eric Christopher <echristo@apple.com> |
80-columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c8ea673bc0e19f36738bec998fe27fad01bf9749 |
|
21-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
Fix a couple issues with Win64 ABI
1) all registers were spilled as xmm, regardless of actual size
2) win64 abi doesn't do the varargs-size-in-%al thing
Still to look into:
xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dab4dac2a0b145be9bee4c25a5f5a502ab441f51 |
|
21-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Pulling out previous patch, must've run the tests in
the wrong directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87f41370a827a1674640e8e1ef3af454679f16c9 |
|
21-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Lower MEMBARRIER on x86 and support processors without SSE2.
Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 60108e96bbc5432f4fe06ba313e64448e97a0e15 |
|
16-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b5378ea12e2171e6150df57c6ddc1039c4c48d3f |
|
15-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use TargetOpcode::COPY instead of X86-native register copy instructions when
lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dedd974e7e47ba3091363f9b97e4881c6ec36edf |
|
14-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR7193 was overly conservative. The only case where sibcall callee
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.
This fixes PR7610.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 84023e0fbefc406a4c611d3d64a10df5d3a97dd7 |
|
10-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d737fcafc4cedcbe798930d96203a9e22c1e6e68 |
|
10-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
An x86 function returns a floating point value in st(0), and we must make sure
it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent
the required sideeffect, so insert an FpGET_ST0 instruction directly instead.
This will matter when CopyFromReg gets lowered to a generic COPY instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 02266e29f9250d74c5ec720aff23add3410ae920 |
|
09-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
--- Reverse-merging r107947 into '.':
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 01dcb18cf38556ba4ebfb60a1cb39f47d9d5e423 |
|
09-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Fix the memoperand offsets in code generated for va_start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf87e2491789d6ff788629e22e93d0c1ca02ae85 |
|
09-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 599b531a960833719f607d66c97871f1f5ad12c0 |
|
09-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
Change LEA to have 5 operands for its memory operand, just
like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ac0ed5dc082dff9ce359af5422f5b82047b4fe6b |
|
09-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
add some long-overdue enums to refer to the parts of the 5-operand
X86 memory operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f59514152511694d46ca8b8d2db466d256ab5759 |
|
08-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bcc8017c738e92d9c1af221b11c4916cb524184e |
|
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f423a69839c4810b890f8a8b09fb8cfbd6bf0139 |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Add X86FastISel support for return statements. This entails refactoring
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a4160c3434b08288d1f79f1acbe453d1b9610b22 |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e2b448c20862ec3da494ef502cca0074c1301acb |
|
07-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Accept RIP-relative symbols with 'i' constraint, and
print the (%rip) only if the 'a' modifier is present.
PR 7528.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c9af33c6854afe7b082af2d892ec5f05dfa383c7 |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
SelectBasicBlock doesn't needs its BasicBlock argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0d881dabc1a4e1aefad6dd38de166d8358285638 |
|
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Propagate debug loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 14152b480d09c7ca912af7c06d00b0ff3912e4f5 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 258c58cc6257cf61c9bdbb9c4cea67ba2691adf0 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert r107655.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b81c771c0d9ab5a980caf3383932b051eafd1a39 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of custom-inserter functions to handle the case where
the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f7a0c7bf8bc8318ed28d889c9a56437ab3e91385 |
|
06-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Fix up -fstack-protector on linux to use the segment
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 62f35a2c133cd7de818dfc366a393282f01b111c |
|
05-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Have the X86 backend use Triple instead of a string and some enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 32b4b5aea6dc38ac5aaff56fc717aebf188e39c9 |
|
05-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
more tidying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f172ecd964307a09f2412b38688ac71fd3c1b87d |
|
05-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
Just rip v2f32 support completely out of the X86 backend. In
the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e35d9842f73cb7273b1d0712183854f5f99fe24f |
|
05-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
fix PR7518 - terrible codegen of <2 x float>, by only marking
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed2ae136d29dd36122d2476801e7d7a86e8301e3 |
|
03-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e1c2b9cc3deca9dec9a53caac576412061cec813 |
|
30-Jun-2010 |
Gabor Greif <ggreif@gmail.com> |
use ArgOperand API
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 78337b4d4d848c85a70d7977bd889317bd830dc7 |
|
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove pointless and unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c25ccf85e55137d9d5cc6f607317d841ff5ae347 |
|
28-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
Reduce indentation via early exit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1cfe44a4609a36cbf1cc0e70091c30f4162a5b36 |
|
26-Jun-2010 |
Gabor Greif <ggreif@gmail.com> |
use ArgOperand API
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1784d160e4efa75782884d451d0788b9457e67dc |
|
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 730c07e50d03be3d64fd4d808c590e6890d32178 |
|
25-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
- Reapply r106066 now that the bzip2 build regression has been fixed.
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e5ff9ef195722cbbf4b6ed7d34412f7277d05eda |
|
24-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Disallow matching "i" constraint to symbol addresses when
address requires a register or secondary load to compute
(most PIC modes). This improves "g" constraint handling. 8015842.
The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously. Fixed to use Linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4e39e9da0f3a435445261d0f796bb0913f3c2bf0 |
|
24-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r106634, now that the bug it exposed is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b13cbca61f2cb00a750a49f844d82c170c6e4c8 |
|
24-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bug in the code which determines when it's safe to use the
bt instruction, which was exposed by r106263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cbe762b5d165c565feb98b745e93b71d208a1e36 |
|
23-Jun-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f1ab49e83abccd9f7b885e74172419249bd5fd8a |
|
23-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
The generic DAG combiner can now fold atomic fences when needed, so switch
to using that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d24c9d5f91442f893bebc2ea8d5ee845bc8b77a9 |
|
23-Jun-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.
Conflicts:
lib/CodeGen/MachineSink.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd11ee2273c946add077ec79abbb3ac9a44178b3 |
|
22-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a3ee5e8e95ac4f1572776b257f83fdee9fdb29e |
|
20-Jun-2010 |
Nick Lewycky <nicholas@mxc.ca> |
Fix warning in no-asserts build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 027657db7cf60bcbf40403496d7e4a170f9ce1ec |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Change UpdateNodeOperands' operand and return value from SDValue to
SDNode *, since it doesn't care about the ResNo value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5ff12fc41a0c53811b59b06deb11d59f45f6df69 |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Delete unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e368b460a206fafa0d31d5d059b1779b94f7df8c |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate unnecessary uses of getZExtValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7720cb3823d5b5868f9b88b0127277820edcb562 |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
isValueValidForType can be a static member function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a7f7426eeb18fef58c3471db23fc829b67bc350 |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
which is faster, simpler, and less surprising.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d361a77f14997d4674f41545103acad3a4a902f1 |
|
16-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
Create a more targeted fix for not sinking instructions into a range where it
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6102549737d2a56031d8f9f0468d3a1a627e181f |
|
16-Jun-2010 |
Eric Christopher <echristo@apple.com> |
For 32-bit non-pic tlv mach-o addressing we don't need a pic base or
a relative address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 544153653b0bccf7ef42a00f68057a87932b47f4 |
|
09-Jun-2010 |
Eric Christopher <echristo@apple.com> |
Ensure that mov and not lea are used to stick the address into
the register. While we're at it, make sure it's in the right one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 88004c25c795dae031d22e5560cc4a0f98594e7c |
|
05-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Fix some liveout handling related to tail calls, see comments.
I don't think this ever resulted in problems on x86, but it
would on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 30ef0e5658b0b8b04437f73f74162d5d72923f29 |
|
03-Jun-2010 |
Eric Christopher <echristo@apple.com> |
Add first pass at darwin tls compiler support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 962f549d207337c03f7d1d1a120860034a52a0e7 |
|
02-Jun-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Fix comment so it doesn't include comments which are irrelevant to the x86
backend. Add a FIXME noting what can be fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71c62a2977c405fb3f7b6dc5dcc59f63ca08be0f |
|
02-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Use comments to document non-obvious code rather than
mailing list archives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a993f0a45fed5e33eb480cb5c8b9c02a76c6602d |
|
02-Jun-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Don't try to custom-lower 64-bit add-with-overflow and friends on x86-32; the
x86 backend currently doesn't know how to handle them.
This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either. We do get a better error message, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9c044674e6349caff46fea79a103dfe210dfde56 |
|
29-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f05cc06a2dd1b5b7b2ae0d7e39f2ddf67649db2 |
|
29-May-2010 |
Dale Johannesen <dalej@apple.com> |
Fix comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 54feef29500dda8ee885af177b449c62ac8b6444 |
|
27-May-2010 |
Dale Johannesen <dalej@apple.com> |
Mark some math lib intrinsic nodes Legal on SSE4.1.
No functional effect as these nodes are not generated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4d3d6e1a0c99e2212953a90185a8d027c595bf5a |
|
27-May-2010 |
Dan Gohman <gohman@apple.com> |
FastISel doesn't yet handle callee-pop functions.
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c2798a18a779b7aa71dda714349ff41eb6679d9f |
|
26-May-2010 |
Zhongxing Xu <xuzhongxing@gmail.com> |
SRetReturnReg was set in LowerFormalArguments(). So only assert it here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2457f2c66184e978d4ed8fa9e2128effff26cb0b |
|
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| acbf6348b1a3503531f7fb0c9f180d149e9927be |
|
21-May-2010 |
Dale Johannesen <dalej@apple.com> |
Previous commit message should refer to 104308.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e39859a838c9cc378509de31eabfb0d216918253 |
|
21-May-2010 |
Dale Johannesen <dalej@apple.com> |
Fix two bugs in 104348:
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d07b48b26370153246de179efe5548365d31054 |
|
21-May-2010 |
Dale Johannesen <dalej@apple.com> |
Fix i64->f64 conversion, x86-64, -no-sse. A bit
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 211ffa13519cadfb7f9baf4c8447fa055bf38fe8 |
|
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f7f5a2760a69370e41b69a66872494bb0aa5fdc9 |
|
16-May-2010 |
Dale Johannesen <dalej@apple.com> |
Revert 103911; it broke a test that expects bitconvert
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine). The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f9b22429278412fda6e1cae3f5727dbc61ff6770 |
|
16-May-2010 |
Dale Johannesen <dalej@apple.com> |
Make x86-64 64-bit bitconvert work when SSE is not available.
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ded05e34b65dc42998e9db6ca1abd513e7a9d120 |
|
16-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add support for thiscall calling convention.
Patch by Charles Davis and Steven Watanabe!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8d908ebd1926d00ff47d8284e52657705efb7f9b |
|
15-May-2010 |
Dale Johannesen <dalej@apple.com> |
Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
The implementation in LegalizeIntegerTypes to handle this as
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people. Use this implementation only
when it is safe. This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)
Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.
7885399, 5901940. This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b92187a4103dca24c3767c380f63593d1f6161a7 |
|
14-May-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71ea4e5b05924c25000013f3b6d6be4946a77a18 |
|
14-May-2010 |
Dan Gohman <gohman@apple.com> |
Lowering of atomic instructions can result in operands being
used more than once. If ISel had put a kill flag on one of them,
it's not valid to transfer the kill flag to each new instance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ff7a562751604a9fe13efc75bd59622244b54d35 |
|
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3335a22a3799c691efe16f697031f405f89eaead |
|
30-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Make this code less confusing. Instead of reassigning BB, just operate
on the original variables, so it's easier to see what is being done
to which blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71edb241a1fe36e5fe95244d40a2f95216cb9247 |
|
30-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Remove the -disable-16bit command-line option, which is now obsolete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1361796dd081f5d6c6be4981e7563c5e46799aa4 |
|
30-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2bce5f4b56ac0ea8e452a79e13abba1deca9b7b6 |
|
28-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable i16 to i32 promotion by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 39cfeecae5102a6544b01e720e718607be068a45 |
|
28-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak the build. Only form shld / shrd after legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8b1190a5400d263b5344f1fcd7b54ae1b6263e7c |
|
28-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5a6a65be468b23fb345211658d935a297fc29245 |
|
28-Apr-2010 |
Stuart Hastings <stuart@apple.com> |
Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b3716e3e28fea28196188734c9868f3b14df0ad2 |
|
27-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
SRA promotion is also not free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 552f09a0d716a73dc70efd66384146e73ee63a3e |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Promoting 16-bit cmp / test aren't free. Don't do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 962021bc7f6721c20c7dfe8ca809e2d98b1c554a |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f822e733aff93b34e6cd85b2f92d86e71fe67f87 |
|
25-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Stop abusing EmitInstrWithCustomInserter for target-dependent
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c82c20b315d47c124893ed1cb27c39b0050fd227 |
|
24-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2808ccb77515d049bfeb44fdf1228ccf9f034f2f |
|
23-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix X86ISD::CMP i16 to i32 promotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f81eca0ab908fdcf98ae0efaa75acccc8ba40dc2 |
|
22-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
and into SelectionDAGBuilder and FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 07c4e1085d04fa773708d0bd91794d80c426eae6 |
|
22-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- It's not safe to promote rotates (at least not trivially).
- Some code refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5528e7bcb1209094a68bbf6d1efeefc3ca34774f |
|
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7609017dc3112337c3098e7d04dcd437549f8b14 |
|
21-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Because of the EMMS problem, right now we have to support
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c26e93e895bfd72a66076de22a216316115f531 |
|
19-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
More progress on promoting i16 operations to i32 for x86. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1e93df6f0b5ee6e36d7ec18e6035f0f5a53e5ec6 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e5b51ac7708402473f0a558f4aac74fab63d4f7e |
|
17-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
More work to allow dag combiner to promote 16-bit ops to 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 551754c4958086cc6910da7c950f2875e212f5cf |
|
17-Apr-2010 |
Eric Christopher <echristo@apple.com> |
Revert 101465, it broke internal OpenGL testing.
Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37f32ee7ffe77d7c2bc1b185802e98979612f041 |
|
16-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4ec2258ffb495d7ce00177e447740ef1123a27db |
|
16-Apr-2010 |
Gabor Greif <ggreif@gmail.com> |
reapply r101434
with a fix for self-hosting
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 64b7bf71e84094193b40ab81aa7dacad921ecbea |
|
16-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
x86 support is off by default. It can be enabled with -promote-16bit.
Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 607a7ab3da72a2eb53553a520507cbb8068dd1d8 |
|
16-Apr-2010 |
Gabor Greif <ggreif@gmail.com> |
back out r101423 and r101397, they break llvm-gcc self-host on darwin10
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ff961f66816daab8bbc58a19025161d969821c2 |
|
15-Apr-2010 |
Gabor Greif <ggreif@gmail.com> |
reapply r101364, which has been backed out in r101368
with a fix
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9ee17208115482441953127615231c59a2f4d052 |
|
15-Apr-2010 |
Gabor Greif <ggreif@gmail.com> |
back out r101364, as it trips the linux nightlybot on some clang C++ tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 165dac08d1bb8428b32a5f39cdd3dbee2888987f |
|
15-Apr-2010 |
Gabor Greif <ggreif@gmail.com> |
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cff6f85454034b9df419e5a1ee9244e086e84f1f |
|
15-Apr-2010 |
Eric Christopher <echristo@apple.com> |
Allow lowering for palignr instructions for mmx sized vectors. Add
patterns to handle the lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2520864773dcb73d76d297605f4bc41c0cf3fa39 |
|
14-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Factor out EH landing pad code into a separate function, and constify
a bunch of stuff to support it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c3b0c341e731b27b550ee9dcded9c17232b296b8 |
|
08-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 75361b69f3f327842b9dad69fa7f28ae3b688412 |
|
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
rename llvm::llvm_report_error -> llvm::report_fatal_error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b1fb4497b0a468a0cb75958ee8ddabf409a12d87 |
|
07-Apr-2010 |
John McCall <rjmccall@apple.com> |
Clean up some signedness oddities in this code noticed by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed3a8067a60ecf2c215e77327a57904c3ebc3355 |
|
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
unthread MMI from FastISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d850ac79b57e6e0bf68ee93a94d0b3dcd9f6ca35 |
|
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fastisel doesn't need DwarfWriter, remove some tendricles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 20adc9dc4650313f017b27d9818eb2176238113d |
|
04-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f28f8bc40eedc6304ab25dd8bed486fa08f51f70 |
|
02-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Correctly lower memset / memcpy of undef. It should be a nop. PR6767.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e754d3fb852abdeaf910c7331eed60f6303597c1 |
|
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e33c848fa481b038d5ad0c7c898c33b2b27ec71e |
|
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 906af6f5180b179766c07ca867b9eb84e4b37239 |
|
02-Apr-2010 |
Eric Christopher <echristo@apple.com> |
Remove FIXME - if there's a better way to do this it isn't here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ae1d41c8ae243329c6f0dfcd6abd33a7f89bfa7b |
|
02-Apr-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Disambiguate conditional expression for newer GCCs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ea97550e361bc6ae23e9415abc7b0a34c540f53 |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
In 64-bit mode, use i64 to lower memcpy / memset instead of f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 42642d06c915a26af1400de6ce6a53c333e5c247 |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comments about DstAlign and SrcAlign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 94107ba9ceaa199f8e5c03912511b0619c84226d |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Avoid using floating point stores to implement memset unless the value is zero.
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 255f20f7f76e4ca1ac1c73294852cb6fcb18c77d |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix sdisel memcpy, memset, memmove lowering:
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 100f090adde26005b9f1eca96871dff52825b27b |
|
31-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 808bab0169ab7d2e8dfdc72dd2c991cd8ff2396d |
|
30-Mar-2010 |
Mon P Wang <wangmp@apple.com> |
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b97a73dedf736e14b04a3d1a153f10d25b2507b |
|
30-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Rip out the 'is temporary' nonsense from the MCContext interface to
create symbols. It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.
This fixes rdar://7807601.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4bd24c257ed1ee10cef1f1b417e1dd2e52e21968 |
|
30-Mar-2010 |
Eric Christopher <echristo@apple.com> |
Add FIXME for operand promotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 34247a0f356edf45ae3ad9ce04e1f90a77c6dba7 |
|
29-Mar-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make isInt?? and isUint?? template specializations of the generic versions. This
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c12cb47d95ff40f02951344ffee6bfd6ee6e900 |
|
26-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not sibcall if stack needs to be dynamically aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3c262eec5354766bab7b37efc8d203a7afe91458 |
|
26-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow trivial sibcall of vararg callee when no arguments are being passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1449f29100a0d3950a1a17e962f7cf718198e283 |
|
24-Mar-2010 |
Nate Begeman <natebegeman@mac.com> |
Per chris's request, add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fdea31a4630da6a5644e059955ee6899deda3471 |
|
24-Mar-2010 |
Nate Begeman <natebegeman@mac.com> |
BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f5b9d6cc82d46dbac7fc469e316a7f1cadd8277f |
|
20-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
If call result is in ST0 and it is not being passed to the caller's
caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4e815f8a8cae6c846cdca52420046cab902865de |
|
16-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Allow modifiers in MCSymbolRefExpr, and eliminate X86MCTargetExpr.
- Although it would be nice to allow this decoupling, the assembler needs to be able to reason about MCSymbolRefExprs in too many places to make this viable. We can use a target specific encoding of the variant if this becomes an issue.
- This patch also extends llvm-mc to support parsing of the modifiers, as opposed to lumping them in with the symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1bbf72b069d8f01779e99c8de2de8501dd3df20c |
|
16-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Recognize code for doing vector gather/scatter index calculations with
32-bit indices. Instead of shuffling each element out of the index vector,
when all indices are needed, just store the input vector to the stack and
load the elements out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 505ad8bed3321bc4b99af8fba4844efe2fe9e67a |
|
15-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Now that the default for Darwin platforms is to place the LSDA into the TEXT
section, remove the target-specific code that performs this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 757e75b03326d9e124dfd28bb34ca00c9edcd391 |
|
15-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Place the LSDA into the TEXT section for x86 Darwin. If the global it's pointing
to is local to the translation unit, we need to place fill the value of that
symbol into the non-lazy pointer.
This should conclude all Darwin changes for placing the LSDA into the TEXT
section. There is some cleanup to do. I.e., there's no longer a special need for
target-specific code here. But that can come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a375d471378b1674a9d77d180a0b05ea8c90cb4b |
|
15-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid sibcall optimization if either caller or callee is using sret semantics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da0688e08a1b9e95ef3fda1158409f40e07be910 |
|
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix PR6605, X86ISD::CMP always returns i32 (EFLAGS), not
the operand type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 314a11318404569efaee74b7208d4b8ab1f64510 |
|
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add support for pentium class CPUs which do not have cmov,
PR4841. Patch by Craig Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f48ef0365545b6160836e3f4b4a210d1e21f1881 |
|
14-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1b2eb0e8a6aaf034675b17be6d853cb1c666200f |
|
13-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the now-unneeded context argument of MBB::getSymbol()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ec041eba384a5553b47295361fde15acc21d5607 |
|
12-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a beta-test for placing the LSDA into the TEXT section on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 018cbd5ddf11a0bbab48cc2a374148bdfce9a9e2 |
|
12-Mar-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Use StringRef::substr instead of std::string::substr to avoid using a free'd
string temporary. This should fix PR6590.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a257095ebb29fd223be2fdbf86d542c5bdfe05f0 |
|
11-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Remove getWidenVectorType, which is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c6678b0014f915de8010fcfbb39461d371a5ca52 |
|
11-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
revert r98270.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 55282267e144a44232aa4731280d8871ba977bf2 |
|
11-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Bad bad bug. x86 force indirect tail call address into eax when it's meant to force it into a call preserved register instead. Change it to ecx for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 29689434635364346cbef6f4e309f1d9fcdd5d80 |
|
11-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add support, testcases, and dox for the new GHC calling
convention. Patch by David Terei!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33 |
|
10-Mar-2010 |
Dale Johannesen <dalej@apple.com> |
Progress towards shepherding debug info through SelectionDAG.
No functional effect yet. This is still evolving and should
not be viewed as final.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 98cdab53c302a2d6686fa428c0e896b1fb195311 |
|
10-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
set the temporary bit on MCSymbols correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 043f3c2a0e286dcfd4cc5a16bf006e3c45929516 |
|
06-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Lower dynamic stack allocation on mingw32 to separate instruction.
We cannot use a normal call here since it has extra unmodelled side
effects (it changes stack pointer). This should fix PR5292.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 10718492c8096bc6779515ef47216715fb749fca |
|
05-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4cae133780aa35b0f40f382286b2c0eb57369fee |
|
05-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an oops in x86 sibcall optimization. If the ByVal callee argument is itself passed as a pointer, then it's obviously not safe to do a tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 26e19ba9aa534e12fc8940036f82dd512b63f69d |
|
05-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Rever 96389 and 96990. They are causing some miscompilation that I do not fully understand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0ef701e6ae816b0360e0a66e8b815ff875fe2a32 |
|
04-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Fix recognition of 16-bit bswap for C front-ends which emit the
clobber registers in a different order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 46ada19645c981a0b7932487d163f7582074a4d9 |
|
02-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 73736df88ba5a35bf172191c2dea5294306fce04 |
|
01-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove the optimize for code size limitation on r67917. Optimize 64-bit imul by constants into leas + shl regardless if optimizing for code size. The size saving from using imulq isn't worth it. Also, the lea and shl instructions may expose further optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c755ba12a79e0bb2899c0bde00b2f7ea2c975a0 |
|
27-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 377fbc073c2e73ef9af8c2e1cf62562a66e9879e |
|
25-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Truncate from i64 to i32 is "free" on x86-32, because it involves
just discarding one of the registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cfe30effbb952ae5b49a01de8329e3a2c14bad75 |
|
24-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
Speculatively revert r97011, "Re-apply 96540 and 96556 with fixes.", again in
the hopes of fixing PPC bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e832693acbfc713bcaf44720efa8149e93a38027 |
|
24-Feb-2010 |
Dan Gohman <gohman@apple.com> |
When forming SSE min and max nodes for UGE and ULE comparisons, it's
necessary to swap the operands to handle NaN and negative zero properly.
Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 97e6b8390b405f9e7dd994f111a5950fca2962d2 |
|
24-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 96540 and 96556 with fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 01be611b8223c80305c7c1ce5d9bd578abc844ed |
|
23-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix rev 96389 by restricting the xform to mask that's either signbit or max signed value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8f2b4cc07161b56e56d6615761ea4ba08dc0e7d3 |
|
23-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
X86InstrInfoSSE.td declares PINSRW as having type v8i16,
don't alis it in the MMX .td file with a different width,
split into two X86ISD opcodes. This fixes an x86 testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9265275a9a5d80ce7005d4f6af134efce52a66af |
|
22-Feb-2010 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Mark the return address stack slot as mutable when moving the return address
during a tail call. A parameter might overwrite this stack slot during the tail
call.
The sequence during a tail call is:
1.) load return address to temp reg
2.) move parameters (might involve storing to return address stack slot)
3.) store return address to new location from temp reg
If the stack location is marked immutable CodeGen can colocate load (1) with the
store (3).
This fixes bug 6225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8ce05daf5409d7bbfdc6bfeaff32304ecd106622 |
|
22-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Remove the logic for reasoning about NaNs from the code that forms
SSE min and max instructions. The real thing this code needs to be
concerned about is negative zero.
Update the sse-minmax.ll test accordingly, and add tests for
-enable-unsafe-fp-math mode as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ccfea35efb0817267a9b997933207863917a8a85 |
|
22-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
fix an incorrect VT: eflags is always i32. The bug was causing us to
create an X86ISD::Cmp node with result type i64 on the
CodeGen/X86/shift-i256.ll testcase and the new isel was assert on it
downstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 293d592bf9cff6c3679998dde32f3cfd3cd53bc4 |
|
21-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
It turned out that we failed to emit proper symbol stubs on non-x86/darwin for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there.
This (I really, really hope) should fix EH issues on ppc/darwin
and arm/darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3eba667081cb63761861e4543715c90f8fc47b18 |
|
19-Feb-2010 |
Duncan Sands <baldrick@free.fr> |
Revert commits 96556 and 96640, because commit 96556 breaks the
dragonegg self-host build. I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier. The
symptom of the 96556 miscompile is the following crash:
llvm[3]: Compiling AlphaISelLowering.cpp for Release build
cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
Stack dump:
0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
g++: Internal error: Aborted (program cc1plus)
This occurs when building LLVM using LLVM built by LLVM (via
dragonegg). Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM. Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.
Found by bisection.
r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 89bb7b56407bf81a5d5fdcdac7106d94bb30dd65 |
|
18-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ae3ecf96035165de3e5327fb33bd30504e21832f |
|
16-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Look for SSE and instructions of this form: (and x, (build_vector c1,c2,c3,c4)).
If there exists a use of a build_vector that's the bitwise complement of the mask,
then transform the node to
(and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)).
Since this transformation is only useful when 1) the given build_vector will
become a load from constpool, and 2) (and (xor x -1), y) matches to a single
instruction, I decided this is appropriate as a x86 specific transformation.
rdar://7323335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96389 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9184b25fa543a900463215c11635c2c014ddb623 |
|
15-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 67c9d42f93a13286a6977686f9d1ed172d2ced0a |
|
15-Feb-2010 |
David Greene <greened@obbligato.org> |
Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b0bc6c361da9009e8414efde317d9bbff755f6c0 |
|
15-Feb-2010 |
Duncan Sands <baldrick@free.fr> |
Uniformize the names of type predicates: rather than having isFloatTy and
isInteger, we now have isFloatTy and isIntegerTy. Requested by Chris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4dd162f3945636cbe6123682619e994f75a62d00 |
|
12-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleanup stdcall / fastcall name mangling.
This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bd13fb62541136a4891d702feec8b7aba5bf695a |
|
11-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
refactor the conditional jump instructions in the .td file to
use a multipattern that generates both the 1-byte and 4-byte
versions from the same defm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f7ea6c3ee89e605c8d0bb7cdb0ade79706c750e8 |
|
11-Feb-2010 |
Mon P Wang <wangmp@apple.com> |
The previous fix of widening divides that trap was too fragile as it depends on custom
lowering and requires that certain types exist in ValueTypes.h. Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements. It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f451cb870efcf9e0302d25ed05f4cac6bb494e42 |
|
10-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Fix "the the" and similar typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 017ec35e28d9960e5398102eceffe9a652703119 |
|
08-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
switch ELF @GOTOFF references to use X86MCTargetExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1797ed50f488f2030f9f9a0ac7426262abf5220a |
|
08-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflect
its current purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f22f9b35d6e6444028ed288bfae526f53740b5c1 |
|
06-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not emit callseq instructions around sibcalls. This eliminated some unnecessary stack adjustments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a62fe66f9916079f97d317f7152f1ac428b4f65a |
|
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
constant propagate a method away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a3a0db01217efc6403d90eec2a6ceb919f5031bc |
|
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
change getSizeOfImm and getBaseOpcodeFor to just take
TSFlags directly instead of a TargetInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5f94193b366435079217dfc34e30241575907cbd |
|
05-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Handle tail call with byval arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1f2fda97b191e480c133989bd31ef87ab31dcba5 |
|
04-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-enable x86 tail call optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dcea16313dfb5ec101daf9483de22daa02e0d59b |
|
04-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Indirect tail call has to go through a call preserved register since it's after callee register pops. X86 isel lowering is using EAX / R11 and it was somehow adding that to function live out. That prevented the real function return register from being added to the function live out list and bad things happen.
This fixes 483.xalancbmk (with tail call opt).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8148ae8847f849e2e1f7d9278b67e7fc9cae6eac |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Speculatively disable x86 automatic tail call optimization while we track down a self-hosting issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 86809ccdaddf48a87ed772bc01464812caaf4baf |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow all types of callee's to be tail called. But avoid automatic tailcall if the callee is a result of bitcast to avoid losing necessary zext / sext etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 90567c35606d65369870d37bf41eb04ef817a90d |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
ByVal frame object size should be that of the byval argument, not the size of the type which is just a pointer. This is not known to break stuff but is wrong nevertheless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
|
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b2c9290a01c5a6f2206f4c47c702086834b65339 |
|
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Perform sibcall in some cases when arguments are passes memory. Look for cases
where callee's arguments are already in the caller's own caller's stack and
they line up perfectly. e.g.
extern int foo(int a, int b, int c);
int bar(int a, int b, int c) {
return foo(a, b, c);
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7276c8c2b5feb321e60fb849a0a109a52ea330b1 |
|
01-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR6196. GV callee may not be a function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0a4fd46d9e0517cbe14f38f52f186094272f8c41 |
|
01-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Undo r94946 now all the tests are passing again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94970 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e626b0f6b187731ea3b3df2171f2d4e093f69f19 |
|
31-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a missing check from my last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 843bd699f68f7dec5724756de10c4146cfde3df6 |
|
31-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid recursive sibcall's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a6bff982c10f6f19c0a9ba20a6300201449c5f39 |
|
30-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow more tailcall optimization: calls with inputs that are all passed in registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7096ae48c931cf42babef061375e5b02840c8957 |
|
29-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Catch more trivial tail call opportunities: no inputs and output types match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5fef8bc1cbcdf70c241ebeb0626849cecd412980 |
|
28-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs.
This fixes PR6146.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b17124553d569c6f09347f2cbe072eab445d30c4 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Perform trivial tail call optimization for callees with "C" ABI. These are done
even when -tailcallopt is not specified and it does not require changing ABI.
First case is the most trivial one. Perform tail call optimization when both
the caller and callee do not return values and when the callee does not take
any input arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1613f40bab14b1c472ed2c491bc65343c073bb31 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete blank lines that bug me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a531673b95639174da449402f6609e7d5a14d2d |
|
26-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ddc419c581ac827045d614099adaa60765ce1ebe |
|
26-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 589c6f620e8dcf3d59af1ae0e15372c934647c82 |
|
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Move getJTISymbol from MachineJumpTableInfo to MachineFunction,
which is more convenient, and change getPICJumpTableRelocBaseExpr
to take a MachineFunction to match.
Next, move the X86 code that create a PICBase symbol to
X86TargetLowering::getPICBaseSymbol from
X86MCInstLower::GetPICBaseSymbol, which was an asmprinter specific
library. This eliminates a 'gross hack', and allows us to
implement X86ISelLowering::getPICJumpTableRelocBaseExpr which now
calls it.
This in turn allows us to eliminate the
X86AsmPrinter::printPICJumpTableSetLabel method, which was the
only overload of printPICJumpTableSetLabel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c64daabb70a2e0cb115f78b0c1548e65c0d527ff |
|
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
implement X86 @GOTOFF jump table entries with the new EK_Custom32
jump table entry kind, instead of overloading
AsmPrinter::printPICJumpTableEntry.
This has a pretty horrible and inefficient FIXME around how @GOTOFF
is currently smashed into the mcsymbol name, but otherwise this is
much cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8c7ecaf524ec3040a9c1c7be5f37e574eb1d0207 |
|
26-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement cond ? -1 : 0 with sbb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94490 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5e1df8d1f71f1a8a534b8b5929a7dd670fe010c6 |
|
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
in 32-bit pic mode for targets with a GOT, x86 emits jump table
entries with @GOTOFF whih is EK_GPRel32BlockAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3a39f8cec8a3302aa924bfe4ef2f0a1bda608182 |
|
25-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
remove dead code: the x86 target never sets usesGlobalOffsetTable,
even on x86-32/elf which uses a GOT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eb38ebf15c326a5bb45ca9da6329cdf19ad6df95 |
|
24-Jan-2010 |
Mon P Wang <wangmp@apple.com> |
Improved widening loads by adding support for wider loads if
the alignment allows. Fixed a bug where we didn't use a
vector load/store for PR5626.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e9625cf6983221ed5d159b822f074a1dfd8f1f3d |
|
23-Jan-2010 |
Eric Christopher <echristo@apple.com> |
Don't lower splat vector load to relative to the esp if the
stack may be misaligned.
Update test accordingly.
Patch by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5ad7de227bd004938747d67d77708e434aea427c |
|
15-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Fix a typo that Anton noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d4f195999a7774611e5f9e457a86f14d5e257324 |
|
11-Jan-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Reimplement getToken and SplitString as "StringRef helper functions"
- getToken is modeled after StringRef::split but it can split on multiple
separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
same behaviour as getToken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a77169dbeb250d1992938650084dc799472fb956 |
|
09-Jan-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Fix http://llvm.org/PR5729: x86-64 tail calls were putting their targets into
R11, and then asserting that the target was in R9. Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 306b4cafc1fd8c075c422825c49bdd14a5f851d7 |
|
09-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ad5b52fd5eaff97e9286255d8626404488a21c21 |
|
08-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 17751dac3e0a7b7a8cdf9bd612ce20f157eb251f |
|
07-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a minor regression from my dag combiner changes. One more place which needs to look pass truncates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d40d03e1bd1d51857fc2f9f9230e334c3a32b249 |
|
06-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach dag combine to fold the following transformation more aggressively:
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))
Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8c65f6e71c1d46d823b9a884819992a9255edd54 |
|
05-Jan-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move remaining stuff to the isInteger predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 11acaa374cdcebb161bf0de5f244265d78a749c1 |
|
05-Jan-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Convert a ton of simple integer type equality tests to the new predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 54de3ea1ca4cfd39048d44fa8d2723079fd84af3 |
|
05-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 760d1945bca8561ca3ca106cc746cca7361b6a6b |
|
04-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Perform this folding as a target specific dag combine:
(or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
The isel patterns may not catch all the cases if general dag combine has reduced width of source operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3cc4a307a8f687dcf33ef947c792b6ede406db0d |
|
04-Jan-2010 |
Dan Gohman <gohman@apple.com> |
A use by operand 1 or 2 of a SELECT is not a FLAGS use. This
lets the test-elimination work in more conditional-move cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7f1a560b2fcd7913544eeaf9712853c58671d3fe |
|
29-Dec-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Replace a few more SmallVectors with arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ea3c2461932d96d3defa0a9aa93ffaf631bb19d |
|
22-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add more plumbing. This time in the LowerArguments and "get" functions which
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 70d0ef1459f332cb7944a20ed65dac3637a2aca7 |
|
17-Dec-2009 |
Ken Dyck <ken.dyck@onsemi.com> |
In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2e489c4f9db83179f9a0bba8ca84265e928b636e |
|
16-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Re-enable 91381 with fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d7760a490544b84127c7c9058238bfb684cf433b |
|
15-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ad9c0a3d8bf625d169596547f893b9ec8b953e26 |
|
15-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2e141d744ee1354f49a99d9da49dbd9570e4269d |
|
15-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Fix integer cast code to handle vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87862e77bbf90cf1b68c9eea1f3641ad81435e38 |
|
11-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 817a46454aa22b80069157a2b02717b7edfd9cbb |
|
11-Dec-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Honour setHasCalls() set from isel.
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c363094e04df621d41ca570eb2a7bf8826bb8c1a |
|
09-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7bd6478cd6a1264f884b46f3694af3a68a6fab0a |
|
09-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 64fa4a9584113f63eccc1a650e7e0cc4ddbab3f6 |
|
09-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cd6e725f21852e2f8cdf5fd0e65eb42c224776f8 |
|
30-Nov-2009 |
Mon P Wang <wangmp@apple.com> |
Added support to allow clients to custom widen. For X86, custom widen vectors for
divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 735afe14eea8049bf69210ce8a3512e391fc643f |
|
24-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bef8888a9197655512f156e50b10799da7240252 |
|
21-Nov-2009 |
Devang Patel <dpatel@apple.com> |
We are not using DBG_STOPPOINT anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 29cbade25aa094ca9a149a96a8614cf6f3247480 |
|
21-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Target-independent support for TargetFlags on BlockAddress operands,
and support for blockaddresses in x86-32 PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d1ba06bf131a9d217426529d2e28af1f2eeed47a |
|
16-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Make X86-64 in the Large model always emit 64-bit calls.
The large code model is documented at
http://www.x86-64.org/documentation/abi.pdf and says that calls should
assume their target doesn't live within the 32-bit pc-relative offset
that fits in the call instruction.
To do this, we turn off the global-address->target-global-address
conversion in X86TargetLowering::LowerCall(). The first attempt at
this broke the lazy JIT because it can separate the movabs(imm->reg)
from the actual call instruction. The lazy JIT receives the address of
the movabs as a relocation and needs to record the return address from
the call; and then when that call happens, it needs to patch the
movabs with the newly-compiled target. We could thread the call
instruction into the relocation and record the movabs<->call mapping
explicitly, but that seems to require at least as much new
complication in the code generator as this change.
To fix this, we make lazy functions _always_ go through a call
stub. You'd think we'd only have to force lazy calls through a stub on
difficult platforms, but that turns out to break indirect calls
through a function pointer. The right fix for that is to distinguish
between calls and address-of operations on uncompiled functions, but
that's complex enough to leave for someone else to do.
Another attempt at this defined a new CALL64i pseudo-instruction,
which expanded to a 2-instruction sequence in the assembly output and
was special-cased in the X86CodeEmitter's emitInstruction()
function. That broke indirect calls in the same way as above.
This patch also removes a hack forcing Darwin to the small code model.
Without far-call-stubs, the small code model requires things of the
JITMemoryManager that the DefaultJITMemoryManager can't provide.
Thanks to echristo for lots of testing!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3f2bf85d14759cc4b28a86805f566ac805a54d00 |
|
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 05872ea804cdc9534960b30d28a391928c61481a |
|
12-Nov-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add compare_lower and equals_lower methods to StringRef. Switch all users of
StringsEqualNoCase (from StringExtras.h) to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b10b91465e69c4ae3649115486e1eb56b8be878 |
|
08-Nov-2009 |
Nate Begeman <natebegeman@mac.com> |
x86 vector shuffle cleanup/fixes:
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect. The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b4997aeab74934ffa6fc0409afc4d8704245e372 |
|
07-Nov-2009 |
Kenneth Uildriks <kennethuil@gmail.com> |
Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f705adbe5ecd156de3f5a3017ddf4017e3890777 |
|
30-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Initial x86 support for BlockAddresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a1eaa3c52b75d4fe2bcd4f7c52e56c405ee91d3c |
|
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a second ValueType argument to isFPImmLegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eb2f969a4ddfb0bc8fdcb5bce3b52e53abff321d |
|
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a49295eae19cb70b451d513aceddc12ba6aaa61 |
|
20-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Make TranslateX86CC return COND_INVALID instead of aborting when it
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a09008bf6ddb61910212c31db1d714182882681e |
|
19-Oct-2009 |
Nate Begeman <natebegeman@mac.com> |
Add support for matching shuffle patterns with palignr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ff89dcb06fbd103373436e2d0ae85f252fae2254 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 20270c909357e5e501cac1f5393430dfacfc57d8 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6553155172a2e74feff1253837daa608123de54a |
|
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 84315 for now. Re-thinking the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf125583f8bd8196a34921276add7f304b7c1433 |
|
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename getFixedStack to getStackObject. The stack objects represented are not
necessarily fixed. Only those will negative frame indices are "fixed."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0032681424a04c321fafb0e6b28ca7cd59b610f8 |
|
12-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Don't forget to mark RAX as live-out of the function when arranging for
it to hold the address of an sret return value, for x86-64 ABI purposes.
Also, fix the test that was originally intended to test this to actually
test it, using FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5f3663e51d1767ebb174d67632dbeca259b6c093 |
|
08-Oct-2009 |
Dale Johannesen <dalej@apple.com> |
Fix handling of x86 'R' constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a55ce4a392f07ac1f3c183100ac591b7ad7c693 |
|
23-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename several variables from EVT to more descriptive names, now that EVT
is also the name of their type, as declarations like "EVT EVT" look
really odd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 670e53977bf289009bb460538987542c9c46ac90 |
|
21-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Recognize SSE min and max opportunities in even more cases.
And fix a bug with the behavior of min/max instructions formed from
fcmp uge comparisons.
Also, use FiniteOnlyFPMath() for this code instead of UnsafeFPMath,
as it is more specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a279bc3da55691784064cb47200a1c584408b8ab |
|
20-Sep-2009 |
Daniel Dunbar <daniel@zuster.org> |
Tabs -> spaces, and remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ce31910eae5bd4896fa6c27798e7b26885691d3b |
|
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
|
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 228252f98157132488a8e2616d9c95a28c167c5c |
|
18-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
Make a new X8632_MachoTargetObjectFile TLOF implementation whose
getSymbolForDwarfGlobalReference is smart enough to know that it
needs to register the stub it references with MachineModuleInfoMachO,
so that it gets emitted at the end of the file.
Move stub emission from X86ATTAsmPrinter::doFinalization to the
new X86ATTAsmPrinter::EmitEndOfAsmFile asmprinter hook. The important
thing here is that EmitEndOfAsmFile is called *after* the ehframes are
emitted, so we get all the stubs.
This allows us to remove a gross hack from the asmprinter where it would
"just know" that it needed to output stubs for personality functions.
Now this is all driven from a consistent interface.
The testcase change is just reordering the expected output now that the
stubs come out after the ehframe instead of before.
This also unblocks other changes that Bill wants to make.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e220c4b3d97bbdc9f6e8cf040942514612349c41 |
|
18-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Add support for using the FLAGS result of or, xor, and and instructions
on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8c6ed05157e9c97ff8f3ccb211dd797e53228da1 |
|
16-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
Big change #1 for personality function references:
Eliminate the PersonalityPrefix/Suffix & NeedsIndirectEncoding
fields from MAI: they aren't part of the asm syntax, they are
related to the structure of the object file.
To replace their functionality, add a new
TLOF::getSymbolForDwarfGlobalReference method which asks targets
to decide how to reference a global from EH in a pc-relative way.
The default implementation just returns the symbol. The default
darwin implementation references the symbol through an indirect
$non_lazy_ptr stub. The bizarro x86-64 darwin specialization
handles the weird "foo@GOTPCREL+4" hack.
DwarfException.cpp now uses this to emit the reference to the
symbol in the right way, and this also eliminates another
horrible hack from DwarfException.cpp:
- if (strcmp(MAI->getPersonalitySuffix(), "+4@GOTPCREL"))
- O << "-" << MAI->getPCSymbol();
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 56d77c70229b9c1345a549d64edfef01f87500c2 |
|
14-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
add some special case handling for strangely named x86 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da9ad384aff792cec928882838653b2e4fe4df12 |
|
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Remove a left over bit of code with no effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c2d98bc0d682419f09659d94afefd6a6266dd6ee |
|
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Remove some not-really-used variables, as warned
about by icc (#593, partial). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81115 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8d44b28bc6f615b9ad79b066987d53b1ea2a2942 |
|
03-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Recognize more opportunities to use SSE min and max instructions,
swapping the operands if necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| efa422023fa750bdef6429e66cc2b628e4d4801b |
|
03-Sep-2009 |
Mon P Wang <wangmp@apple.com> |
Fixed a few problems with vector shifts
- when transforming a vector shift of a non-immediate scalar shift amount, zero
extend the i32 shift amount to i64 since the vector shift reads 64 bits
- when transforming i16 vectors to use a vector shift, zero extend i16 shift amount
- improve the code quality in some cases when transforming vectors to use a vector shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f67df794a053f939bc35cd057c7fcd67a58cbb5 |
|
03-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Add a -disable-16bit flag and associated support for experimenting with
disabling the use of 16-bit operations on x86. This doesn't yet work for
inline asms with 16-bit constraints, vectors with 16-bit elements,
trampoline code, and perhaps other obscurities, but it's enough to try
some experiments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
|
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52600972832cb4ae8f4c63802f3764cbfbcb203d |
|
02-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
refactor select 'sched insertion' out to its own method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c69d74a5d41a6c5e92f9d947f2fa181f48626ca5 |
|
31-Aug-2009 |
Duncan Sands <baldrick@free.fr> |
Revert commit 80428. It completely broke exception
handling on x86-32 linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b35a09e7e5b1aa26588e3852fe00a42b4f383ba |
|
29-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
- Add target lowering methods to get the preferred format for the FDE and LSDA
encodings.
- Make some of the values emitted by the FDEs dependent upon the pointer
size. This is in line with how GCC does things. And it has the benefit of
working for Darwin in 64-bit mode now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f83a5def43635436a6c2618e1b0b279d9930ecc7 |
|
27-Aug-2009 |
Eric Christopher <echristo@apple.com> |
Add FIXME for when we support more specific XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fd17929b864b009ee80144c21489273cc9ec8773 |
|
27-Aug-2009 |
Eric Christopher <echristo@apple.com> |
Nuke trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cbbea0ffc7b40f0d1dc5b692f80aa246bdd37a17 |
|
27-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Expand i8 selects into control flow instead of 16-bit conditional
moves. This avoids the need to promote the operands (or implicitly
extend them, a partial register update condition), and can reduce
i8 register pressure. This substantially speeds up code such as
write_hex in lib/Support/raw_ostream.cpp.
subclass-coalesce.ll is too trivial and no longer tests what it was
originally intended to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 24f20e083280d979e8fa1bc88959ae9e8339ee99 |
|
22-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Record variable debug info at ISel time directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b120ab4057fc66ce11ee1f108af9dbbeafa3fed9 |
|
19-Aug-2009 |
Eric Christopher <echristo@apple.com> |
Implement sse4.2 string/text processing instructions:
Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 25103a2617259e23c4736f0114cfd9a416dcbbf1 |
|
18-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix function alignment at -Os on x86 to be 1, not 2. getFunctionAlignment
returns a log2 value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| face41a4de759e881bea1769d86c4cfda2cd1545 |
|
16-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Avoid emitting XMM save code in soft-float or no-implicit-float mode
or some other situation where no xmm registers need to be saved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af5663405834ca7cf4a847f2efa2d624ce99b1d8 |
|
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Reapply r79127. It was fixed by d0k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f865ea85bd9d3e04aa795ee03cfc8db339f8c9b9 |
|
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Revert r79127. It was causing compilation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 088880cb192fb6dd5b1bf85af62023c5ca3da38f |
|
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change allowsUnalignedMemoryAccesses to take type argument since some targets
support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d6708eade079c30b0790789a00a8d737d84f52b7 |
|
15-Aug-2009 |
Dan Gohman <gohman@apple.com> |
On x86-64, for a varargs function, don't store the xmm registers to
the register save area if %al is 0. This avoids touching xmm
regsiters when they aren't actually used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2247276c6f97abf8ebb6ea0a566e6fed5a4c4fe2 |
|
14-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly handle indirect win64 args when they're passed in memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1d0be15f89cb5056e20e2d24faa8d6afb1573bca |
|
13-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Push LLVMContexts through the IntegerType APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 766b5efd99c01e26f00f22d81b57d1385b3d2ab0 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Fix warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d6662add687f20cffa0755e410efbb40de4dcf23 |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
SimpleValueType-ify a few more methods on TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 70671845adce8ab36ae596bb06d0375459a7a2af |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Continue the SimpleValueType-ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 77547befdc430633aaedf4130ddf17d953ed552e |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b5e01724057e6eabc45da75df3037af4ad29248c |
|
06-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Better handle kernel code model. Also, generalize the things and fix one
subtle bug with small code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
|
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6dde14bc25a0dca2e1ff45753f3f5ae55a4eb109 |
|
03-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Perform bitconvert to proper type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4ab15535e7028a48d75c9d08ed57e9b3b05b1f53 |
|
03-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 80cb8aa86282281ceef49638f11e07d62b0d2ee3 |
|
03-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleanup Darwin MMX calling conv stuff - make the stuff more generic. This also fixes a subtle bug, when 6th v1i64 argument passed wrongly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cf6b739d3d4921dc9fc6908ec2009055c0927125 |
|
03-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cc2b67af91b199ab234afc9e26dee09b056cf4a0 |
|
03-Aug-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove a bitcast that was a no-op.
Thanks to Eli Friedman for noticing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| def390a30aa8c3eb94796a062b161762330fdbe4 |
|
03-Aug-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use movq to move 64 bits in and out of mmx registers.
Fixes PR4669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7e77b0fcb0d00309ab59ad167becf203e61b2aea |
|
01-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Minor code cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f26e03bc7e30162197641406e37e662a15d80f7e |
|
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
refactor section construction in TLOF to be through an explicit
initialize method, which can be called when an MCContext is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 68a31c2583dde574f1dce0b6b161754c2e7e28cd |
|
30-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Rename GRAD to GR32_AD, to follow the naming convention of other
classes. And define its SubRegClassList.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37b7387da90ffd42d28ad0f08fca00b684294b2c |
|
30-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch.
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.
This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.
Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 978dae35e20766d262605b787f8e7f86d8c96dc8 |
|
29-Jul-2009 |
Eric Christopher <echristo@apple.com> |
Add llvm_unreachable for ... unreachable code!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 31dcfe61210305e3b14f3a5ba6a1b8ba453b2d6d |
|
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
whitespace cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 794bfed25dd6a4282af204c8b4bfa76d7d4221d8 |
|
29-Jul-2009 |
Eric Christopher <echristo@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71c6753d03d1bb27d0cf997285c425d631e5807b |
|
29-Jul-2009 |
Eric Christopher <echristo@apple.com> |
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower
to ptest instruction plus setcc. Revamp ptest instruction. Add test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af7ec975870f92245f1f1484ac80a1e2db6a0afa |
|
28-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Return ConstantVector to 2.5 API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4bb253c60f895131371aa2ad1bfa5a2bea213f78 |
|
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
mode, and "ld64" (the default linker) falls back to it in -static
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f0144127b98425d214e59e4a1a4b342b78e3642b |
|
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f83c9c6ef0e7f79825a0a8f22941815e4b684c7 |
|
27-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Move ConstantFP construction back to the 2.5-ish API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77247 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eed707b1e6097aac2bb6b3d47271f6300ace7f2e |
|
25-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fbd6687cf1fb3408e8e34994f13e69c754e5c15e |
|
24-Jul-2009 |
Eric Christopher <echristo@apple.com> |
Update insertps handling based on feedback. Move to a v4f32 style
to support vector arguments and scalar arguments correctly. Update
lowering and fix comment to refer to pinsr* instead of insertps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3dae284f5e865ad21d9ce0e0a2f038e5932b7a13 |
|
22-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for MMX VSETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e922c0201916e0b980ab3cfe91e1413e68d55647 |
|
22-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Get rid of the Pass+Context magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b3e717192635873a0d8491fc45ddb64c0e4bda15 |
|
21-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove shift amount flavor. It isn't actually complete enough to
be useful, and it's currently unused. (Some issues: it isn't actually
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 60b3ba0472c8b764cbfac173446438b682d5093f |
|
21-Jul-2009 |
Dale Johannesen <dalej@apple.com> |
revert 76503 while I figure out what's going on
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71bbebdac9e05b3dd7e8d041ad6907d474968a6a |
|
21-Jul-2009 |
Dale Johannesen <dalej@apple.com> |
Make sure a global matching asm 'i' constraint gets its
flags set properly. (hasMemory is clearly irrelevant
when matching 'i', I don't understand what this was
supposed to be doing.)
gcc.apple/asm-block-25.c (test passed before by
accident, but generated code was wrong)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b8105651527670cb456eb46dd4346bacd3905361 |
|
20-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Copy ExpandInlineAsm to TargetLowering from TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 47e9fab1584a3fc9311fdecdbb87124e0a0b39e8 |
|
18-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a90b3dc2f1f70ab7102ec3f1fc57f199fd56d7cc |
|
15-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Move a few more convenience factory functions from Constant to LLVMContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4f0664949729778a3551970cd74e976f0d9a046f |
|
11-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Fix PR4533, which is about buggy codegen in x86-64 -static mode.
Basically, using:
lea symbol(%rip), %rax
is not valid in -static mode, because the current RIP may not be
within 32-bits of "symbol" when an app is built partially pic and
partially static. The fix for this is to compile it to:
lea symbol, %rax
It would be better to codegen this as:
movq $symbol, %rax
but that will come next.
The hard part of fixing this bug was fixing abi-isel, which was actively
testing for the wrong behavior. Also, the RUN lines are completely impossible
to understand what they are testing. To help with this, convert the -static
x86-64 codegen tests to use filecheck. This is much more stable and makes it
more clear what the codegen is expected to be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e2c920845a407957b8ae2600feae1f4c85a0d4d0 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove the now-dead TM argument to these methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3b67e9ba015624a9904a41d6d0fd61cac1b02055 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dfed413ef6bfb05754ee5a9f3a3c7f98c764a374 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate GVRequiresRegister, replacing it with predicates we
need for other purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 36c250112143a11d0afd4aba91a9e742031e4152 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
change a bunch of logic in LowerGlobalAddress to leverage the work
done in ClassifyGlobalReference instead of reconstructing the info
awkwardly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d392bd97c8203ab4a770dfdd0a5565ac6cd6cacd |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move some classification logic around. Now GVRequiresExtraLoad
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3b6b36d6f54e780a2947cb1b9efe4eed7c40dc11 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
change isGlobalStubReference to take target flags instead of a MachineOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed0dca6a5dfa26e63c5636eb092640159182df89 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
GVRequiresExtraLoad is now never used for calls, simplify it based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 754b7650c20a0fa3a9df3f067dc02a0905992325 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code
more complex and slow than just directly testing what we care about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e6c07b52e76b19d83338901b2e103bd8cbabd42f |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
There is only one case where GVRequiresExtraLoad returns true for calls:
split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 04b304caf633a471946c59c7d313e1560c5d07a5 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d1474d09cbe5fdeec8ba0d6c6b52f316f3422532 |
|
09-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Thread LLVMContext through MVT and related parts of SDISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ac007b64ea24c81338b5f1277ee214c51bbdb1ce |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify this logic a bit more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 75cdf27f48f0b81f778b6aa50efcefa0497a9dae |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move reasoning about darwin $non_lazy_ptr stubs from asmprinter into
isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c388b2c9d263a2c348d926a45548d6caad5e3df |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make isel use MO_PIC_BASE_OFFSET when lowering globalvalues on darwin in pic
mode, instead of having asmprinter just "know" to print them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 74e726e3270c99169cc90fb3c676eeaae273f48c |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make isel decide whether to emit $stub's on darwin instead of asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 48a7d0257f3b01e495593450b3eba5c4c23076d5 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Make isel determine where to emit PLT-relative calls instead of having
asmprinter do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 15a380a03567deba90c074a2cd5a45b81ae0958b |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify some code based on the fact that picstyles != none are only valid
in pic or dynamic-no-pic mode. Also, x86-64 never used picstylegot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3fff30d471ee6f9453c98bdcc4e3e8ebe4692d24 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
all this logic always returns true because GOT mode is never active in x86-64 mode.
Simplify it away, someone should evaluate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 88e1fd539e80827931694e667c119ef01c7d1184 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
isPICStyleRIPRel() and friends are never true in -static mode.
Simplify code based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e4df756289b6d80dcfd67b9f97fd464f62fd4902 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
When in -static mode, force the PIC style to none. Doing this requires fixing
code which conflated RIPRel PIC with x86-64. Fix these to just check for X86-64
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b133a0aff77adf1787afe5d35cf140194c29d386 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
merge two identical functions and simplify things that are GOT specific
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e3ee6f1e1fcd61a9a0f3297848e73bd55b42a97d |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
hoist check for IsTailCall to callers. Eliminate redundant check for
x86-64: GOT-style PIC is never used on x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 951bf7d74f12b6dacfb2691c90603916b9bfd93f |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
change a few methods to be static functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4aa21aa6d13b8ea00eb0817e53f24e5416ed3038 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move handling of dllimport linkage in isel, not in asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 804e0fea4033e3b91dbc8198cef30de30f141bb5 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Convert more abort() calls to llvm_report_error().
Also remove trailing semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab7c09b6b6f4516a631fd6788918c237c83939af |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 76a1e2e250955042e60be4348c5c51e5a55454bf |
|
07-Jul-2009 |
Dale Johannesen <dalej@apple.com> |
Don't accept globals as matching 'i' constraint
in PIC modes (in accordance with existing comment).
gcc.apple/asm-block-25.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b61cd185eeb90bec93f042535594132ae1f0f41 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d94c101abb2753e4d3cb7c7f436c7a38de94dc3c |
|
30-Jun-2009 |
David Greene <greened@obbligato.org> |
Add a 256-bit register class and YMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9917700af4e773b8269b6751014da490c914c524 |
|
29-Jun-2009 |
Owen Anderson <resistor@mac.com> |
Add a target-specific DAG combine on X86 to fold the common pattern of
fence-atomic-fence down to just the atomic op. This is possible thanks to
X86's relatively strong memory model, which guarantees that locked instructions
(which are used to implement atomics) are implicit fences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b9838dbd4593e988b0614bb170427f153b14931 |
|
29-Jun-2009 |
David Greene <greened@obbligato.org> |
Add more vector ValueTypes for AVX and other extended vector instruction
sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b1acd68fe454fe3b98120dcfcbfb2e7e39298da6 |
|
27-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
pull @GOT, @GOTOFF, @GOTPCREL handling into isel from the asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 18c5987fa33ba9d57ea597e3131f664443765f4e |
|
27-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b903bed0feaa35a2b5e404923db724a62b433787 |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
Move all the TLS processing logic into isel, don't do it in asmprinter at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 41621a27008cde333e5281dc4bd4a5a08d0827b5 |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
move magic for PIC constantpool references from asmprinter to isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 55e7c827301da0e5e03b26835bff259c320b3bf7 |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
start adding logic in isel to determine asm printer semantics, step N of M.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4150c086d0c463f1c2c2dffd1b854090b1e48dd6 |
|
21-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
indentation fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6314ac2bca0dfad6951931862b75a4586c9c8249 |
|
16-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Misc accumulated tweaks to legalization logic for various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2e06dd210102ccee4d9ae08ee01130f09ba01173 |
|
15-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
I got J and K backward, many thanks to Eli for spotting this!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e4935150c71170ee0aa174e08282a6913148c04c |
|
15-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
implement support for the 'K' asm constraint, PR4347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bbd8c33ee67f99f5bad7288dfa465d675714e983 |
|
12-Jun-2009 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Fix Bug 4278: X86-64 with -tailcallopt calling convention
out of sync with regular cc.
The only difference between the tail call cc and the normal
cc was that one parameter register - R9 - was reserved for
calling functions through a function pointer. After time the
tail call cc has gotten out of sync with the regular cc.
We can use R11 which is also caller saved but not used as
parameter register for potential function pointers and
remove the special tail call cc on x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b51b6cf1d0b17ee7cdb9cf8365471a39b3b67b7c |
|
10-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Silence a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5d28eb9e9780a19d03ff106fdc609b1587cd6003 |
|
07-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Get rid of some unnecessary code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7a5e55509b99d579d56d126a7b503ec6fe153a8f |
|
07-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Slightly generalize the code that handles shuffles of consecutive loads
on x86 to handle more cases. Fix a bug in said code that would cause it
to read past the end of an object. Rewrite the code in
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general.
Remove PerformBuildVectorCombine, which is no longer necessary with
these changes. In addition to simplifying the code, with this change,
we can now catch a few more cases of consecutive loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 30e71eb61bcbcc31214617996dc4927d5c3169de |
|
06-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Avoid crashing on a variable-index insertelement with element type i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1041553424cb0a9af03398ee0bff0d1a23fccc6f |
|
06-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL
nodes for vectors with an i16 element type. Add an optimization for
building a vector which is all zeros/undef except for the bottom
element, where the bottom element is an i8 or i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 23ef1055808c2bcf5aa29d63b87f5d3aa5da5992 |
|
06-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
PR2598: make sure to expand illegal forms of integer/floating-point
conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> ->
<4 x float>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 578efa920abd218ba75a0fb3c9b8398f4c0a774b |
|
05-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Add new function attribute - noimplicitfloat
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| abc019968067736a499467f7db7fb758a425ca06 |
|
05-Jun-2009 |
Nate Begeman <natebegeman@mac.com> |
Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.
Teach the build_vector dag combine in x86 back end to recognize consecutive
loads producing the low part of the vector.
Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.
Add a testcase for the transform.
Old:
subl $28, %esp
movl 32(%esp), %eax
movl 4(%eax), %ecx
movl %ecx, 4(%esp)
movl (%eax), %eax
movl %eax, (%esp)
movaps (%esp), %xmm0
pmovzxwd %xmm0, %xmm0
movl 36(%esp), %eax
movaps %xmm0, (%eax)
addl $28, %esp
ret
New:
movl 4(%esp), %eax
pmovzxwd (%eax), %xmm0
movl 8(%esp), %eax
movaps %xmm0, (%eax)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6a784894b1e9c85ff52790adc3880a3a7a1a4ea3 |
|
05-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Evan thinks NoImplicitFloat check is not required here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 974d90bb706ad996b3a62cfe440fe1a7f64f54de |
|
03-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Remove unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 874ae251c317788391f9c3f113957802d390a063 |
|
02-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4150d83abe90a5da4ddf86433b7bf4329acfa57c |
|
02-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.
Most targets will still produce a Flag-setting target-dependent
version when selection is done. X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted. All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly. The
same can be done on other targets.
The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 51b16f473759c1546acbf308a5d3f3e7bf3ea23c |
|
30-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Untabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8b944d39b356135676459152385f05c496951f6c |
|
28-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl $65536, 8(%rax)
=>
orb $1, 10(%rax)
Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ba2352b0663e718855d1898fab6d3308dedd14fc |
|
27-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Ger rid of some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 36df499648745871442d552ee584bc2667790a26 |
|
27-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
FP_TO_XINT. Necessary for some cleanups I'm working on. Updated
from the previous version (r72431) to fix a bug and make some things a
bit clearer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 82205570d1017c95fef1fe10b1741ccf6d01904e |
|
26-May-2009 |
Daniel Dunbar <daniel@zuster.org> |
Back out r72431, it is causing a number of compilation crashes with clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ecc23a5240a381ee15aca98301516d86eb09f1c6 |
|
26-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
FP_TO_XINT. Necessary for some cleanups I'm working on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 108b519cc11dd748b55299d34a577971405826b5 |
|
24-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Make the X86 backend mark EXTRACT_SUBVECTOR as Expand, at least for the
moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 948e95a381bf6771639703643ef75e0115b35f53 |
|
23-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Make the x86 backend custom-lower UINT_TO_FP and FP_TO_UINT on 32-bit
systems instead of attempting to promote them to a 64-bit SINT_TO_FP or
FP_TO_SINT. This is in preparation for removing the type legalization
code from LegalizeDAG: once type legalization is gone from LegalizeDAG,
it won't be able to handle the i64 operand/result correctly.
This isn't quite ideal, but I don't think any other operation for any
target ends up in this situation, so treating this case specially seems
reasonable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6ebf7bc7405ee79d27d50b70f0c1a474cbea820d |
|
13-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Run code placement optimization for targets that want it (arm and x86 for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 49921963220485efb9610a45cb21952dd0cdb67f |
|
08-May-2009 |
Chris Lattner <sabre@nondot.org> |
Fix PR4152: asm constraint validation happens before dag combine, so we
need to work a bit to combine things like (x+c1+c2) into x+c3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ec8eee2d3a402dd001daae3865bc5c10b41c323e |
|
30-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5a5ca1519e04310f585197c20e7ae584b7f2d11f |
|
29-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
Implement review feedback for vector shuffle work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9008ca6b6b4f638cfafccb593cbc5b1d3f5ab877 |
|
27-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 15f1b66d64b3c79966e2d36a39817eb97ea579aa |
|
24-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
very elegant, but neither is the tls specification :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 15684b29552393553524171bff1913e750f390f8 |
|
24-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b706d29f9c5ed3ed9acc82f7ab46205ba56b92dc |
|
24-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 005e7984ccc20c65a3bdfc112021b337935131a9 |
|
21-Apr-2009 |
Duncan Sands <baldrick@free.fr> |
Get rid of what looks like a copy-and-pasted typo.
Spotted by gcc-4.5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 998e125a87d49f28c714d8223a37746850401057 |
|
20-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ee3db3003deb18461a72b82166d8d417925d06f |
|
17-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
For general dynamic TLS access we must use
leaq foo@TLSGD(%rip), %rdi
as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7ff5bff45eaa1fabf8bb910daf2907cf981cbf3d |
|
13-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
X86-64 TLS support for local exec and initial exec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fc1665793e62eb4f26d24b8a19eecf59cd872e2a |
|
10-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Remove the obsolete SelectionDAG::getNodeValueTypes and simplify
code that uses it by using SelectionDAG::getVTList instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 349ba4951faf3105775e2276a068c135141d42d9 |
|
09-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Fix grammaros in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 094fad37b90946c91a09eb9270a0dbe800f49d87 |
|
08-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8ef2b89131d5be0cee83f4d3007e437cb37f4335 |
|
08-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Avoid a hard coded constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 97121ba2afb8d566ff1bf5c4e8fc5d4077940a7f |
|
08-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 044b5344c4a97b3c709a05b9c5f9296656477652 |
|
08-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 |
|
07-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1e95580925b173ea13fbe77c0eb299f672391656 |
|
03-Apr-2009 |
Mon P Wang <wangmp@apple.com> |
Added a x86 dag combine to increase the chances to use a
movq for v2i64 on x86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5867de1243c7e43d7bbd5e90287106e3feb7e9e6 |
|
02-Apr-2009 |
Chris Lattner <sabre@nondot.org> |
silence warning in release-asserts build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d54f2d571dd7faaa379eb7833536494aa4ab4609 |
|
31-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
i128 shift libcalls are not available on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 73f24c9f0d9afd1fd65d544f2b7b7b7c77fc2238 |
|
30-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da945e3bb2069c1a7194bcd10579a03ff925a031 |
|
28-Mar-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Have only one definition of X86AddrNumOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b0cd9113af42c422c829563c3b12e6e52bd2d79 |
|
28-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
x * 40
=>
shlq $3, %rdi
leaq (%rdi,%rdi,4), %rax
This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq (%rdi,%rdi,2), %rax
leaq (%rsi,%rax,8), %rax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a82dfca8c6c91ed34b7360afdba771145023b8fd |
|
27-Mar-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
I am trying to add a segment to the X86 addresses matching to
improve TLS support (see http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075220.html), but that code is VERY brittle.
This patch just makes it a bit more resistant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 92722533819ab838d958966d0e40a60030bb3c16 |
|
27-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
-no-implicit-float means explicit fp operations are legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67784 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a02a3dda5652995afaaf11148c11d98c9b9d908f |
|
26-Mar-2009 |
Bill Wendling <isanbard@gmail.com> |
Pull transform from target-dependent code into target-independent code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8b4b874cc67ae4cefc0e723c8f93cf8d6101fcb2 |
|
26-Mar-2009 |
Bill Wendling <isanbard@gmail.com> |
Match this pattern so that we can generate simpler code:
%a = ...
%b = and i32 %a, 2
%c = srl i32 %b, 1
%d = br i32 %c,
into
%a = ...
%b = and %a, 2
%c = X86ISD::CMP %b, 0
%d = X86ISD::BRCOND %c ...
This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 105be5ac99a3b1e3a239765d3fad366eda37046b |
|
13-Mar-2009 |
Bill Wendling <isanbard@gmail.com> |
These instructions have special lowering that may lower them to SSE
instructions. Prevent that if we don't want implicit uses of SSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1606e8e4cd937e6de6681f686c266cf61722d972 |
|
13-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.
Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cee56e7d33fecc74da6f16ebb48dd5b62d73ea8d |
|
13-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
generalize the previous code to use the full generality of LEA
for i32/i64 expressions (we could also do i16 on cpus where
i16 lea is fast, but I didn't add this). On the example, we now
generate:
_test:
movl 4(%esp), %eax
cmpl $42, (%eax)
setl %al
movzbl %al, %eax
leal 4(%eax,%eax,8), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
cmpl $41, (%eax)
movl $4, %ecx
movl $13, %eax
cmovg %ecx, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 97a29a5fee209769c52d78564ffe9dde514d5f03 |
|
13-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
optimize the case of cond ? 42 : 41 and friends. This compiles the
example to:
_test:
movl 4(%esp), %eax
cmpl $41, (%eax)
setg %al
movzbl %al, %eax
orl $4294967294, %eax
ret
instead of:
movl 4(%esp), %eax
cmpl $41, (%eax)
movl $4294967294, %ecx
movl $4294967295, %eax
cmova %ecx, %eax
ret
which is smaller in code size and faster. rdar://6668608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d1980a5acd8509ea34ee2dec5e13de5dbe16af2d |
|
12-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
related transformations out of target-specific dag combine into the
ARM backend. These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).
Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently
with the recently added cp constant select optimization, but is a
very general xform. For example, we now compile the second example
in const-select.ll to:
_test:
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
seta %al
movzbl %al, %eax
movl 4(%esp), %ecx
movsbl (%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal 4(%eax), %ecx
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
cmovbe %eax, %ecx
movsbl (%ecx), %eax
ret
This passes multisource and dejagnu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 536e66764b93fd1368ce4d1f753cbe909c05b62d |
|
12-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f9abd7e33ea6e8f57176d0069d61595c1347a5ff |
|
11-Mar-2009 |
Bill Wendling <isanbard@gmail.com> |
Add a -no-implicit-float flag. This acts like -soft-float, but may generate
floating point instructions that are explicitly specified by the user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b3ef693d78764ba0077cc0c9e770fa57c724b7a |
|
11-Mar-2009 |
Mon P Wang <wangmp@apple.com> |
For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37b9a19653bfa8cbc6047236f563a3d1dccbadf4 |
|
11-Mar-2009 |
Mon P Wang <wangmp@apple.com> |
Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 47b4ce85293b5668eb7b7b6ccc484b69d5f8b602 |
|
11-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
formatting change, reduce indentation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3112581441cd22ac955b1af2d08effe3bab975da |
|
07-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Arithmetic instructions don't set EFLAGS bits OF and CF bits
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 51bb47480ea510ffc490c603244995e8977bc379 |
|
05-Mar-2009 |
Dan Gohman <gohman@apple.com> |
When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand.
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4bfcf2a2a64785f3f0f0dd8fa6f4052d6cd7c08c |
|
05-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix the "test" optimization to recognize "dec" as an add of
negative one, as subtracts of immediates are canonicalized
to adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 076aee32e86bc4a0c096262b3261923f25220dc6 |
|
04-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 29582d1223d2cd851e136bfe39c508930c4b5592 |
|
04-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Revert r66004 for now; it's causing a variety of test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 12bbc52aa7ad84a944f14757f7f6d77b9fa3188f |
|
04-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Teach the x86 backend to eliminate "test" instructions by using the EFLAGS
result from add, sub, inc, and dec instructions in simple cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9a58023c6ce1e77447a21d07a3de4c1ac98a3d24 |
|
27-Feb-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Refactor TLS code and add some tests. The tests and expected results are:
pic | declaration | linkage | visibility |
!pic | declaration | external | default | tls1.ll tls2.ll | local exec
pic | declaration | external | default | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default | tls3.ll tls4.ll | initial exec
pic | !declaration | external | default | tls3-pic.ll tls4-pic.ll | general dynamic
!pic | declaration | external | hidden | tls7.ll tls8.ll | local exec
pic | declaration | external | hidden | X | local dynamic
!pic | !declaration | external | hidden | tls9.ll tls10.ll | local exec
pic | !declaration | external | hidden | X | local dynamic
!pic | declaration | internal | default | tls5.ll tls6.ll | local exec
pic | declaration | internal | default | X | local dynamic
The ones marked with an X have not been implemented since local dynamic is not implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a87008d90b7d894cfca53d407642acfd7be2af3c |
|
25-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 242b38bae5d8eeadca0e0cf4777b3b285cb5eb01 |
|
23-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Only v1i16 (i.e. _m64) is returned via RAX / RDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b9a47b824f6c8ef3989a796018bf974c09cd243f |
|
23-Feb-2009 |
Nate Begeman <natebegeman@mac.com> |
Generate better code for v8i16 shuffles on SSE2
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
cleanups.
New tests that test the above.
Examples:
New:
_shuf2:
pextrw $7, %xmm0, %eax
punpcklqdq %xmm1, %xmm0
pshuflw $128, %xmm0, %xmm0
pinsrw $2, %eax, %xmm0
Old:
_shuf2:
pextrw $2, %xmm0, %eax
pextrw $7, %xmm0, %ecx
pinsrw $2, %ecx, %xmm0
pinsrw $3, %eax, %xmm0
movd %xmm1, %eax
pinsrw $4, %eax, %xmm0
ret
=========
New:
_shuf4:
punpcklqdq %xmm1, %xmm0
pshufb LCPI1_0, %xmm0
Old:
_shuf4:
pextrw $3, %xmm0, %eax
movsd %xmm1, %xmm0
pextrw $3, %xmm1, %ecx
pinsrw $4, %ecx, %xmm0
pinsrw $5, %eax, %xmm0
========
New:
_shuf1:
pushl %ebx
pushl %edi
pushl %esi
pextrw $1, %xmm0, %eax
rolw $8, %ax
movd %xmm0, %ecx
rolw $8, %cx
pextrw $5, %xmm0, %edx
pextrw $4, %xmm0, %esi
pextrw $3, %xmm0, %edi
pextrw $2, %xmm0, %ebx
movaps %xmm0, %xmm1
pinsrw $0, %ecx, %xmm1
pinsrw $1, %eax, %xmm1
rolw $8, %bx
pinsrw $2, %ebx, %xmm1
rolw $8, %di
pinsrw $3, %edi, %xmm1
rolw $8, %si
pinsrw $4, %esi, %xmm1
rolw $8, %dx
pinsrw $5, %edx, %xmm1
pextrw $7, %xmm0, %eax
rolw $8, %ax
movaps %xmm1, %xmm0
pinsrw $7, %eax, %xmm0
popl %esi
popl %edi
popl %ebx
ret
Old:
_shuf1:
subl $252, %esp
movaps %xmm0, (%esp)
movaps %xmm0, 16(%esp)
movaps %xmm0, 32(%esp)
movaps %xmm0, 48(%esp)
movaps %xmm0, 64(%esp)
movaps %xmm0, 80(%esp)
movaps %xmm0, 96(%esp)
movaps %xmm0, 224(%esp)
movaps %xmm0, 208(%esp)
movaps %xmm0, 192(%esp)
movaps %xmm0, 176(%esp)
movaps %xmm0, 160(%esp)
movaps %xmm0, 144(%esp)
movaps %xmm0, 128(%esp)
movaps %xmm0, 112(%esp)
movzbl 14(%esp), %eax
movd %eax, %xmm1
movzbl 22(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 42(%esp), %eax
movd %eax, %xmm1
movzbl 50(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm1, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 77(%esp), %eax
movd %eax, %xmm1
movzbl 84(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 104(%esp), %eax
movd %eax, %xmm1
punpcklbw %xmm1, %xmm0
punpcklbw %xmm2, %xmm0
movaps %xmm0, %xmm1
punpcklbw %xmm3, %xmm1
movzbl 127(%esp), %eax
movd %eax, %xmm0
movzbl 135(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 155(%esp), %eax
movd %eax, %xmm0
movzbl 163(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm0, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 188(%esp), %eax
movd %eax, %xmm0
movzbl 197(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 217(%esp), %eax
movd %eax, %xmm4
movzbl 225(%esp), %eax
movd %eax, %xmm0
punpcklbw %xmm4, %xmm0
punpcklbw %xmm2, %xmm0
punpcklbw %xmm3, %xmm0
punpcklbw %xmm1, %xmm0
addl $252, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4214a5531cdbe538a358033f1847e55c4436be1b |
|
23-Feb-2009 |
Scott Michel <scottm@aero.org> |
Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6140a8b0572c80383a67248e8b1c0cf2379b1c43 |
|
22-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Be bug compatible with gcc by returning MMX values in RAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 79fb3b434f83bcb7c382dbcfea485884a39b9544 |
|
20-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Support return of MMX values in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fdc40a0a696c658d550d894ea03772e5f8af2c94 |
|
17-Feb-2009 |
Scott Michel <scottm@aero.org> |
Remove trailing whitespace to reduce later commit patch noise.
(Note: Eventually, commits like this will be handled via a pre-commit hook that
does this automagically, as well as expand tabs to spaces and look for 80-col
violations.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c7ce29b04fb50bd7a0b4b096d1d23e3de4b0802e |
|
13-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Teach x86 target -soft-float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 78e3e521cd90e5f6382c14b6e4d809fb59610ed6 |
|
12-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Arrange to print constants that match "n" and "i" constraints
in inline asm as signed (what gcc does). Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f38cb61a94b3abab70f0ee463bdcf55d86d334e |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Use getDebugLoc forwarder instead of getNode()->getDebugLoc.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1fdbc1dd4e9cb42c79a30e8dc308c322e923cc52 |
|
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b300d2aa3ef08b5074449e2c05804717f488f4e4 |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of the last non-DebugLoc versions of getNode!
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e8d7230f480654cdb8ff1c3d0a38e1e9ab0bd55f |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc getNode variants. Use
getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| de06470330260f5937e7ca558f5f5b3e171f2ee5 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed2eee63a6858312ed17582d8cb85a6856d8eb34 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 33c960f523f2308482d5b2816af46a7ec90a6d3d |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getLoad and getStore.
Adjust the many callers of those versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37eed798a94b6e4160cc4fc5b239d24707556f9e |
|
04-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Minor code cleanups; no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7bcaefaf5946aa2e902fead5eab321787e38eaf1 |
|
04-Feb-2009 |
Mon P Wang <wangmp@apple.com> |
Fixes a case where we generate an incorrect mask for pshfhw in the presence
of undefs and incorrectly determining if we have punpckldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd64c417c0ef73345222eca60154289c1ad62a09 |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Patch up omissions in DebugLoc propagation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0f502f6f44f2756f5cb7b17d8f1d8eae000d51b4 |
|
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Add some DL propagation to places that didn't
have it yet. More coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e4d209dcb8abb7e1b38bbe940e94cc3605fe7a87 |
|
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
DebugLoc propagation. done with file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ace1610df5fe22519d82cd7418a772e46ebd965b |
|
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
DebugLoc propagation. 2/3 through file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 97d0e0e31409865b2077248a05b1b91b4a259d95 |
|
02-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 961d6d4ac07fedc37b6dadc00e5be54aa720c224 |
|
02-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 67ad9db15b474a667f09eea5e32955a910c09e32 |
|
02-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3f142c36ad04c1aabac90df6a866bd2b0767f24f |
|
01-Feb-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for
var-args, and don't allow FP return values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b0d5cdd52e8448f769cd71aaee6a4b8592dc08b1 |
|
01-Feb-2009 |
Duncan Sands <baldrick@free.fr> |
Fix PR3453 and probably a bunch of other potential
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d2ad624fa749a6d3edac0d94e9c107989c16304 |
|
31-Jan-2009 |
Dale Johannesen <dalej@apple.com> |
Make LowerCallTo and LowerArguments take a DebugLoc
argument. Adjust all callers and overloaded versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7581bfa2757a3149c6d17c0fe592e5c3808aa843 |
|
31-Jan-2009 |
Bill Wendling <isanbard@gmail.com> |
Get rid of the non-DebugLoc-ified getNOT() method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7ad9b5127869e0074565ffaec489c9537c6ec467 |
|
30-Jan-2009 |
Mon P Wang <wangmp@apple.com> |
When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of
an illegal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e5af2d3a224d4b38760a26d237cde040cb6e14eb |
|
29-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Make x86's BT instruction matching more thorough, and add some
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e91a0008895873f3f418640354efcfd996f621f9 |
|
29-Jan-2009 |
Mon P Wang <wangmp@apple.com> |
Fixed lowering of v816 shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3becd093cc308578ca979edbbab0f76d98cef4ec |
|
28-Jan-2009 |
Mon P Wang <wangmp@apple.com> |
Add shuffle splat pattern for x86 sse shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e7852d014432a06c783de3c350eb96e686f10f92 |
|
26-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Take the next steps in making SDUse more consistent with LLVM Use, and
tidy up SDUse and related code.
- Replace the operator= member functions with a set method, like
LLVM Use has, and variants setInitial and setNode, which take
care up updating use lists, like LLVM Use's does. This simplifies
code that calls these functions.
- getSDValue() is renamed to get(), as in LLVM Use, though most
places can either use the implicit conversion to SDValue or the
convenience functions instead.
- Fix some more node vs. value terminology issues.
Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c2fd67f6977d181856e0abd277f78b93593e2e37 |
|
26-Jan-2009 |
Nate Begeman <natebegeman@mac.com> |
De-identifying per sabre review
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 740ab03f12b82eb2ad8ccddc385593f3367fc574 |
|
26-Jan-2009 |
Nate Begeman <natebegeman@mac.com> |
Support pattern matching various x86 sse shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c2454623841f05c6c665659b34c214950d12d7e |
|
22-Jan-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add SelectionDAG::getNOT method to construct bitwise NOT operations,
corresponding to the "not" and "vnot" PatFrags. Use the new method
in some places where it seems appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 50c3dfefd97ebd60ed6159728da644189865ae70 |
|
19-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting.
%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>
The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a06ec9efe122b296056961e3914823b07e67b387 |
|
19-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 030939c87b68292e474dbf518eebf83c9d78d01c |
|
17-Jan-2009 |
Bill Wendling <isanbard@gmail.com> |
Extend thi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f6a4e2edb01a1b57128a7306d7154a88637c406d |
|
17-Jan-2009 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert my last change. It is causing a bootstrap failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8b8a6368437abea4e4adb9afab455727f2da6624 |
|
17-Jan-2009 |
Bill Wendling <isanbard@gmail.com> |
Implement a special algorithm for converting uint_to_fp for i32 values on
X86. This code:
void f() {
uint32_t x;
float y = (float)x;
}
used to be:
movl %eax, -8(%ebp)
movl [2^52 double], -4(%ebp)
movsd -8(%ebp), %xmm0
subsd [2^52 double], %xmm0
cvtsd2ss %xmm0, %xmm0
Is now:
movsd [2^52 double], %xmm0
movsd %xmm0, %xmm1
movd %ecx, %xmm2
orps %xmm2, %xmm1
subsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm0
This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 64e87326d9cec962018d3f6274a8f2b84d0274a1 |
|
16-Jan-2009 |
Bill Wendling <isanbard@gmail.com> |
Add support for non-zero __builtin_return_address values on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f0fcdd8e264e6e787532ec06e360d6c500edd0ab |
|
15-Jan-2009 |
Mon P Wang <wangmp@apple.com> |
Expand insert/extract of a <4 x i32> with a variable index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c13cf130c45c5675ea879e1c5454298dfbe5e02f |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Make getWidenVectorType const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0746392cc29f6484b50852387c72a7dba54bf379 |
|
14-Jan-2009 |
Dan Gohman <gohman@apple.com> |
BT appears to be available on all >= i386 chips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 286575c65c096e4d226b8a4c4a29a88d1c846b4f |
|
14-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Don't use a BT instruction if the AND has multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 83489bb7700c69b7a4a8da59365c42d3f5c8129b |
|
13-Jan-2009 |
Devang Patel <dpatel@apple.com> |
Use DebugInfo interface to lower dbg_* intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 653456c351d9bf908ebd982f6ae9df3449c5f34b |
|
07-Jan-2009 |
Dan Gohman <gohman@apple.com> |
X86_COND_C and X86_COND_NC are alternate mnemonics for
X86_COND_B and X86_COND_AE, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a84e4402a1ab7ff36f52acdf5e1891e283a947e |
|
05-Jan-2009 |
Devang Patel <dpatel@apple.com> |
squash warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52ceafa5c7f86de19c8a98d9686e213a2985c061 |
|
02-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5480c0469e5c0323ffb12f1ead2abd169d6cc0e7 |
|
01-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType. In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e55484eb4521413b31450bd680fcf3694613579f |
|
25-Dec-2008 |
Chris Lattner <sabre@nondot.org> |
Add a simple pattern for matching 'bt'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1c39d4cfaa80addcf8ef4e298be63fc5831b8efe |
|
25-Dec-2008 |
Chris Lattner <sabre@nondot.org> |
translateX86CC can never fail. Simplify it based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4328708bad5808f92bb8bceb358eb04154fcca52 |
|
24-Dec-2008 |
Chris Lattner <sabre@nondot.org> |
indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c78e0286a1523c40440698e74f5fe2bf5c1f212 |
|
24-Dec-2008 |
Chris Lattner <sabre@nondot.org> |
simplify some control flow and reduce indentation, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c7a37d4ff2ee8ffb93ba97e9393ff582f0e79a9a |
|
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add instruction patterns and encodings for the x86 bt instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b1d4a798d1dd2f39521b6b381cd1c1911c9ab52 |
|
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Clean up the atomic opcodes in SelectionDAG.
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.
This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61389 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 62c75ea397bdb3b4de7138a1d67311310da01f40 |
|
23-Dec-2008 |
Mon P Wang <wangmp@apple.com> |
Fixed code generation for v8i16 and v16i8 splats on X86.
Fixed lowering of v8i16 shuffles for v8i16 when we fall back to extract/insert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af9b952627d8fa10412b8cf7319d3e334446547f |
|
18-Dec-2008 |
Mon P Wang <wangmp@apple.com> |
Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d350e02e19e1b79c3fd6dc70ee3c01ab75c631c1 |
|
12-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
- Use patterns instead of creating completely new instruction matching patterns,
which are identical to the original patterns.
- Change the multiply with overflow so that we distinguish between signed and
unsigned multiplication. Currently, unsigned multiplication with overflow
isn't working!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9e5ecb8f8f3b639874b943702a3dd1d0739bb9b9 |
|
12-Dec-2008 |
Mon P Wang <wangmp@apple.com> |
Added support for SELECT v8i8 v4i16 for X86 (MMX)
Added support for TRUNC v8i16 to v8i8 for X86 (MMX)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab55ebda1c2254f98b06e770bc2dae7d05a4a366 |
|
12-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Redo the arithmetic with overflow architecture. I was changing the semantics of
ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.
Similar for SUB and MUL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bc5e15eafb3c39a214631087b6827a5691e9b25c |
|
10-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Whitespace changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 74c376529101acbe141a256d0bf23a44eb454c84 |
|
09-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Add sub/mul overflow intrinsics. This currently doesn't have a
target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 203af58aea3ae341d38e5c2c5b390b0c31d25557 |
|
05-Dec-2008 |
Dale Johannesen <dalej@apple.com> |
Make LoopStrengthReduce smarter about hoisting things out of
loops when they can be subsumed into addressing modes.
Change X86 addressing mode check to realize that
some PIC references need an extra register.
(I believe this is correct for Linux, if not, I'm sure
someone will tell me.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 370e5340a585d7d4b98bd855e52e4624c44ad681 |
|
03-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0ea25cb9413ec60d6f844cf427c99c721062085f |
|
03-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
CC should only be a ConstantSDNode at this point. Just use 'cast' instead of 'dyn_cast'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 61edeb5ed26d970cfc08ee71081d5095df4b59bb |
|
02-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Second stab at target-dependent lowering of everyone's favorite nodes: [SU]ADDO
- LowerXADDO lowers [SU]ADDO into an ADD with an implicit EFLAGS define. The
EFLAGS are fed into a SETCC node which has the conditional COND_O or COND_C,
depending on the type of ADDO requested.
- LowerBRCOND now recognizes if it's coming from a SETCC node with COND_O or
COND_C set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aaffa05d0a652dd3eae76a941d02d6b0469fa821 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
There are no longer any places that require a
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1607f05cb7d77d01ce521a30232faa389dbed4e2 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 109872e36039e3a44c07a2e3272ba6528e78cb62 |
|
27-Nov-2008 |
Bill Wendling <isanbard@gmail.com> |
Comment out code that isn't entirely correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3fafd935607844085a23c012e2a8778fa97206a0 |
|
26-Nov-2008 |
Bill Wendling <isanbard@gmail.com> |
Generate something sensible for an [SU]ADDO op when the overflow/carry flag is
the conditional for the BRCOND statement. For instance, it will generate:
addl %eax, %ecx
jo LOF
instead of
addl %eax, %ecx
; About 10 instructions to compare the signs of LHS, RHS, and sum.
jl LOF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 41ea7e7eb3a6a269f2bfed0bdc191ea046d18e5e |
|
24-Nov-2008 |
Bill Wendling <isanbard@gmail.com> |
- Make lowering of "add with overflow" customizable by back-ends.
- Mark "add with overflow" as having a custom lowering for X86. Give it a null
lowering representation for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9f22a4aaaf2bdde843e0b32f85a1951f12f257d5 |
|
24-Nov-2008 |
Mon P Wang <wangmp@apple.com> |
Added missing description for -disable-mmx option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 03228089d5235f8c90477f88809139464e9c6ea5 |
|
23-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
Rename SetCCResultContents to BooleanContents. In
practice these booleans are mostly produced by SetCC,
however the concept is more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3c81d35e7dd178fe245230892a0cd01a65175f49 |
|
23-Nov-2008 |
Mon P Wang <wangmp@apple.com> |
Added -disable-mmx using a patch from Preston Gurd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 330169fa3e9c46c46bf130746d38e6ec2fac303a |
|
13-Nov-2008 |
Dale Johannesen <dalej@apple.com> |
Extend InlineAsm::C_Register to allow multiple specific registers
(actually, code already all worked, only the comment
changed). Use this to implement 'A' constraint on x86.
Fixes PR 1779.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f007a8b931e229eb325319c97363be8507311e2e |
|
06-Nov-2008 |
Mon P Wang <wangmp@apple.com> |
Widening cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58796 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9dd93b36b8b33281774c6257ad07a3e7d0d1c660 |
|
05-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d17cfbe1cad81b5f420031f73f52411285ec831f |
|
31-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Use MOVSSmr instead of EXTRACTPSmr in the case of extracting
vector element 0 for a store, as it's smaller and faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0c39719bfc7d0b3e61fbd55e1115184a1d5f6ae7 |
|
30-Oct-2008 |
Mon P Wang <wangmp@apple.com> |
Add initial support for vector widening. Logic is set to widen for X86.
One will only see an effect if legalizetype is not active. Will move
support to LegalizeType soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4002a1b6f1cb7c7db7965bd281fb29664fd6c816 |
|
28-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a nasty miscompilation of 176.gcc on linux/x86 where we synthesized
a memset using 16-byte XMM stores, but where the stack realignment code
didn't work. Until it does (PR2962) disable use of xmm regs in memcpy
and memset formation for linux and other targets with insufficiently
aligned stacks.
This is part of PR2888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4047f4a0b478e20e981cc46d2aa0ca3141f79f07 |
|
24-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Fix translateX86CC: if SetCCOpcode is SETULE and
LHS is a foldable load, then LHS and RHS are swapped
and SetCCOpcode is changed to SETUGT. But the later
code is expecting operands to be the wrong way round
for SETUGT, but they are not in this case, resulting
in an inverted compare. The solution is to move the
load normalization before the correction for SETUGT.
This bug was tickled by LegalizeTypes which happened
to legalize the testcase slightly differently to
LegalizeDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e80d67ec11cff70700a13b54a4c057afd58ed33c |
|
22-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Remove allocation of unused stack slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b6aeb3806a877fb2a290450fe4761e2eeab50e2 |
|
22-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Get this working with LegalizeTypes: (1) don't
assume that i64 has been turned into a BUILD_PAIR
node (when called from LegalizeTypes this hasn't
happened yet) and don't use a vector shuffle mask
with an illegal element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9ae0d6df516403265b3c6384615dee9a21e7fa8b |
|
22-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Adjust comments for pedantic satisfaction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 040225fcb7e16ad7485dec9ccd23f178297a8a61 |
|
22-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Add comments to explain uint64->f64 algorithm,
well, sort of. (Algorithm by Ian Ollmann.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1c15bf58a3700d40a6a88ac0ce14a2c99f111483 |
|
21-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Add an SSE2 algorithm for uint64->f64 conversion.
The same one Apple gcc uses, faster. Also gets the
extreme case in gcc.c-torture/execute/ieee/rbug.c
correct which we weren't before; this is not
sufficient to get the test to pass though, there
is another bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4401361a2fb92c82317dbfbb1616f54ced2b51f3 |
|
21-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Don't create TargetGlobalAddress nodes with offsets that don't fit
in the 32-bit signed offset field of addresses. Even though this
may be intended, some linkers refuse to relocate code where the
relocated address computation overflows.
Also, fix the sign-extension of constant offsets to use the
actual pointer size, rather than the size of the GlobalAddress
node, which may be different, for example on x86-64 where MVT::i32
is used when the address is being fit into the 32-bit displacement
field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 279c22e6da2612f024b70e5509ffb0cad32f38b2 |
|
21-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed294c46daa0ee9da1d5efffa57866b23a7cc4d9 |
|
20-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Have X86 custom lowering for LegalizeTypes use
LowerOperation if it doesn't know what else to do.
This methods should probably be factorized some,
but this is good enough for the moment. Have
LowerATOMIC_BINARY_64 use EXTRACT_ELEMENT rather
than assuming the operand is a BUILD_PAIR (if it
is then getNode will automagically simplify the
EXTRACT_ELEMENT). This way LowerATOMIC_BINARY_64
usable from LegalizeTypes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6520e20e4fb31f2e65e25c38b372b19d33a83df4 |
|
18-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1fa7198f36b96462835acb2e1aad342021dac3a4 |
|
17-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
add support for 128 bit inputs on both x86-64 and x86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3d0c4c4657f179d8256dfa04e38ce9bd2cc67d2b |
|
17-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a bug where the x86 backend would reject 64-bit r constraints when
in 32-bit mode instead of assigning a register pair. This has nothing to
do with PR2356, but I happened to notice it while working on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fcab2bd2f3c849816fffff71342477788985b403 |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Remove an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7f042681764c6f8eae22781d8b4cb4c218a86b76 |
|
15-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Add target lowering hooks that specify which setcc conditions are illegal,
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dd5b58ad7be78be90390074f0df138778af5c895 |
|
15-Oct-2008 |
Dan Gohman <gohman@apple.com> |
FastISel support for exception-handling constructs.
- Move the EH landing-pad code and adjust it so that it works
with FastISel as well as with SDISel.
- Add FastISel support for @llvm.eh.exception and
@llvm.eh.selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0329466b6b4927f4e6f5d144891fef06a027fec5 |
|
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e563bbc312f8b11ecfe12b8187176f667df1dff3 |
|
12-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 23a98551ab65eeb8fe5019df8b7db4891582a4bd |
|
10-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Add a "loses information" return value to APFloat::convert
and APFloat::convertToInteger. Restore return value to
IEEE754. Adjust all users accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 882cdfde516fb97a1fda1a3bbc85b1792aa7659c |
|
06-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 880ae364ba4ed3d63542a2ef934980c70e8bb9d7 |
|
04-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Make atomic Swap work, 64-bit on x86-32.
Make it all work in non-pic mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1b54c7fe9b034a6450af8596231ad5368b617725 |
|
03-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Pass MemOperand through for 64-bit atomics on 32-bit,
incidentally making the case where the memop is a
pointer deref work. Fix cmp-and-swap regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d735b8019b0f297d7c14b55adcd887af24d8e602 |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 48c1bc2ace6481d3272ab5c18e1f19352c563be8 |
|
02-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Handle some 64-bit atomics on x86-32, some of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6158d8492cc021bb47caee6d4755135ef1d855a4 |
|
01-Oct-2008 |
Bill Wendling <isanbard@gmail.com> |
Implement the -fno-builtin option in the front-end, not in the back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6e08738d4b1bb6c087d81bca656c24cdc1d504f8 |
|
01-Oct-2008 |
Bill Wendling <isanbard@gmail.com> |
Just don't transform this memset into "bzero" if no-builtin is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f287b22d2e57600b4cd5dc209d0d869e7736c0b |
|
30-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Add the new `-no-builtin' flag. This flag is meant to mimic the GCC
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71d1bf55a27017fceef25554e02021a3bc47cdb4 |
|
30-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Remove misuse of ReplaceNodeResults for atomics with
valid types. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 184793fc8a9cf6ecc9147468bbcc068f472b8517 |
|
27-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 56683 with fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d5d8191b202c0f96f33c826c93d9796451ff7fca |
|
27-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7810bfed5570c192e0714a8fd0e5130a0c38dd2e |
|
26-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode's getSignExtended to getSExtValue, for
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 36a55023c1daae86afedf6e6672c0adad7bbe5ea |
|
26-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 86098bd6a63d2cdf0c9be9ef3151bd2728281fd7 |
|
26-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add "inreg" field to CallSDNode (doesn't increase
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4dcc8a373d23cb5e9aa83c27f2c7ada95ed10708 |
|
26-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Prefer movlhps over punpcklqdq, etc. in more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0598866c052147c31b808391f58434ce3dbfb838 |
|
25-Sep-2008 |
Devang Patel <dpatel@apple.com> |
Large mechanical patch.
s/ParamAttr/Attribute/g
s/PAList/AttrList/g
s/FnAttributeWithIndex/AttributeWithIndex/g
s/FnAttr/Attribute/g
This sets the stage
- to implement function notes as function attributes and
- to distinguish between function attributes and return value attributes.
This requires corresponding changes in llvm-gcc and clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b457f0c3a7e21b1fb9ac8b9f8e404e1312b6a60 |
|
25-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a186ae4aaa58d2af0fb4963a7cb6b96a7346bda |
|
25-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
X86ISD::VZEXT_LOAD should produce and fold a chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da43bcf624acb56a3d77bb5ae9a02728af032613 |
|
24-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d57dd5f4e6740520820bc0fca42a540e31c27a73 |
|
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Arrange for FastISel code to have access to the MachineModuleInfo
object. This will be needed to support debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 364091e0909dc2ab470a40d3981be2efa2643bd7 |
|
23-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Support x86 specific inline asm modifier 'J'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0bb41608e94adfe9884bc188457c4f6ae47ea43c |
|
22-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Make log, log2, log10, exp, exp2 use Expand by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 290ae0398e3673ff742c8e0e2fddfae388950c5b |
|
22-Sep-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 014278e6a11fa0767853b831e5bf51b95bf541c5 |
|
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 095cc29f321382e1f7d295e262a28197f92c5491 |
|
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
|
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1fdc40f0622375f7f9a4ccfbbf5deda68131f6e0 |
|
11-Sep-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d18a462bdd8ba6a7dd14e40ff0ebaedf9c46de26 |
|
11-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
The version of AtomicSDNode::AtomicSDNode used (only) for
cmp-and-swap reversed the Cmp and Swap arguments; comments
make it clear this is unintentional. Unfortunately, the
x86 BE had a compensating reversal, which is removed here.
PPC is OK.
From inspection of the Alpha code I think it is OK, but
if somebody has that platform please check it out. I
cannot test on that platform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0586d91bb3e516d5826826522d9a90ed6ef74d86 |
|
10-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Add X86FastISel support for static allocas, and refences
to static allocas. As part of this change, refactor the
address mode code for laods and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b188dd9c5b5ae7e2d284fcc322e3a510305f57ad |
|
10-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fb0e1323e2759b177df8b57b03475f1135b5000f |
|
10-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Handle new intrinsics with vector arguments.
Patch by Paul Redmond.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bf53c2952de5bc494942007b378970f1584dec03 |
|
10-Sep-2008 |
Duncan Sands <baldrick@free.fr> |
Fix name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ed7d37cbf5391aefab75205d95b3ac2077f1203 |
|
10-Sep-2008 |
Duncan Sands <baldrick@free.fr> |
Add trampoline support for the new FastCC calling
convention (not related to recent Ada testsuite
failures).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56054 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 06d77dd94573543f2bc0a183d12602e194d37981 |
|
10-Sep-2008 |
Duncan Sands <baldrick@free.fr> |
Turn off the new FastCC for the moment. It causes
a slew of Ada testsuite failures on x86-32 linux.
Seems to be related to the use of float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bff66b0c6c8266a6f9ba6c9bd5d2541a4d4c6ec9 |
|
09-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Replace explicit pointer-size constants to TargetData query.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b84c1676f1e324b1ed5bba191f840eff8bdf2f4f |
|
08-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Reapply 55899: First draft of EH support on x86/64-linux
Now with fix, which prevents subtle codegen bug to trigger on darwin.
No fix for bug though, it's still there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 260a6b8f85f4c9a8af34aae97ecbe8b0f28e0758 |
|
08-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Reapply blindly reverted 55898: Implement FRAME_TO_ARGS_OFFSET for x86-64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1b0123c3cd79d50f3b59f6509d93f3ce97a1cbc0 |
|
08-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r55898 as well. This wasn't reverted in the original revert...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a425e0073df51ab99665062a8c00d704e89d2ef8 |
|
08-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 302affbc5337e8b9c2c920eba0756d620d06c386 |
|
08-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
First draft of EH support on x86/64-linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 559189e0ac258e2d0a0aa64978c4808fb99ba9ed |
|
08-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement FRAME_TO_ARGS_OFFSET for x86-64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e9ac9e6b7d906a277911db4db7bef08f84e6f09c |
|
07-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Some code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4a03775777785ef758cff8c0699a6bf571a1f2b9 |
|
05-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c2feb5c2622c132077b157c3056f8f1ffe0cf13b |
|
04-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7794f2a3a7778bdbc9bdd861db1fe914450e0470 |
|
04-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3df24e667f04a7003342b534310919abc9c87418 |
|
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Create HandlePHINodesInSuccessorBlocksFast, a version of
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c3f44b0d636ff9a6d706ea9ac17ae77c8fa8aeff |
|
03-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 456704476f953e4bee7ba4a95f9bf6dbb724e370 |
|
30-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Swap fp comparison operands and change predicate to allow load folding (safely this time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 94a50da93cb9fdc45f3c3ab06f68380b31dd0c1c |
|
30-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Backing out 55521. Not safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4d46d0af583b95a5d4f7d490f542c4fb65b9e824 |
|
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Swap fp comparison operands and change predicate to allow load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 327ef031ed038c55ddccb34fb922dd9c9fd735a6 |
|
29-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
remove tabs, fix > 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
|
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 833a990c26d2f3346371110f1ace3d64a8b342f8 |
|
28-Aug-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use resize instead of reserve. Reserve doesn't change size().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e00a8a2a2e11a37fd1ddf2504bd22d225d0994d0 |
|
28-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Split the ATOMIC NodeType's to include the size, e.g.
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 99a6cb92d173c142073416c81efe6d3daeb80b49 |
|
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6ba50a92525521b46ef5c72ee5a0f80ba0263c01 |
|
26-Aug-2008 |
Chris Lattner <sabre@nondot.org> |
If an xmm register is referenced explicitly in an inline asm, make sure to
assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab6c3bb44d254d1b3c9dcce74ba3a917558feab3 |
|
25-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 59b63e4a1827b4096c997eec0983aecb3676695f |
|
24-Aug-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily reverting r55292. It's causing a bootstraping failure:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 32c727cd95a7718e10e225bb9fc00be6681706aa |
|
24-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move callseq_start above the call address load to allow load to be folded into the call node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ae0218c914331510e2d7e3cda4d33d0457e2552d |
|
22-Aug-2008 |
Bill Wendling <isanbard@gmail.com> |
If part of the mask is "undef", then ignore it as we don't care what goes into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e85dc49e13265af1b41a14e6359537e14d8f9ecb |
|
22-Aug-2008 |
Bill Wendling <isanbard@gmail.com> |
Fix whitespace. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1887c1c2f99903d13406e723f2dcbab4511e3f49 |
|
21-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a number of byval / memcpy / memset related codegen issues.
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7e66510a2e24720af187a7aed4c1e9112a823183 |
|
21-Aug-2008 |
Mon P Wang <wangmp@apple.com> |
Treat floating point ST1 the same as ST0 when lowering for a call result
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bb466331e7e50d03497ce40ee344870236fd9c32 |
|
20-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify FastISel's constructor argument list, make the FastISel
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a99e38495f1485ee0295a920244d0eb48568debd |
|
20-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Add remaining 64-bit atomic patterns for x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5bf1b4eacdd87b0753279a378e93126c0b053144 |
|
20-Aug-2008 |
Bill Wendling <isanbard@gmail.com> |
Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.
Just expand it like the other X-bit sub_and_fetches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55023 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1adf1b03af9b1e2ee5a527caa5b14c9d55a32173 |
|
19-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Instantiate FastISel for X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d9f3c480a7bc0969b08ace68af7dcde40f6caff1 |
|
19-Aug-2008 |
Dan Gohman <gohman@apple.com> |
The X86 target will soon have an implementation of createFastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 140be2dfb76928cb660b7de23f8310d76ca794b5 |
|
19-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Add support for 8 and 16 bit forms of __sync
builtins on X86.
Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0ac3fc2a61f77af74ccde3dcd437d0f72b736b8f |
|
17-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d97f29531cea88fcb05e2d055dde92778fcc41e0 |
|
16-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use correct name for TLS address resolution routine on x86-64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ef521f14b7046a0f7ec169696a13b473c3ab4aee |
|
15-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Also avoid pinsrw and pinsrb with a variable insertelement index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c0573b13a119e1e504225542bddd85db7d4bd29f |
|
15-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Don't try to use the insertps instruction for vector
element inserts with non-constant indices. This fixes
CodeGen/X86/vector-variable-idx.ll on machines that
have SSE4.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e9d503583804b63bdd815e8fdbc2f6cf627e973f |
|
06-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d0859943ac16389fb843f1357746aade3cd07a6f |
|
05-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Add an assert to catch invalid VECTOR_SHUFFLE mask indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 08ca62bb6f1da313ac0fd3ae80c9cf6caa0dd3c6 |
|
03-Aug-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
Add atomic sub for other sizes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8968450305c28444edc3c272d8752a8db0c2f34a |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Tidy SDNode::use_iterator, and complete the transition to have it
parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fb8ead0c20f347fc1f0385f801ee0636d1ff6289 |
|
25-Jul-2008 |
Nate Begeman <natebegeman@mac.com> |
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx
mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.
Also commit Mon Ping's VSETCC patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5e6ebaf4d1d3043d3428b65ee8054c71c24af930 |
|
23-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR2485: do all 4-element SSE shuffles in max. of 2 shuffle instructions.
Based on patch by Nicolas Capens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ace3c17798d49245593cd9d2312a68e1ebafae56 |
|
22-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Factor out SSE 4 wide shuffle lowering code into its own function. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52672b813e0e1741855c5692a84be5bc9ef5869f |
|
22-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR2574: implement v2f32 scalar_to_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d038e04188047eca4749d025ef1f05f7ae660bca |
|
21-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add VerifyNode, a place to put sanity checks on
generic SDNode's (nodes with their own constructors
should do sanity checking in the constructor). Add
sanity checks for BUILD_VECTOR and fix all the places
that were producing bogus BUILD_VECTORs, as found by
"make check". My favorite is the BUILD_VECTOR with
only two operands that was being used to build a
vector with four elements!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3180e20cda2150a3fc694b3713cae4c5f2fda49f |
|
20-Jul-2008 |
Bill Wendling <isanbard@gmail.com> |
Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts
into v4i16 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 30a0de94e7a5cbdcd277a93e543b0788efa78ddc |
|
17-Jul-2008 |
Nate Begeman <natebegeman@mac.com> |
SSE codegen for vsetcc nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f595266b91ea5aef953ce3019557a5f3d3291ff9 |
|
17-Jul-2008 |
Mon P Wang <wangmp@apple.com> |
When lowering certain atomics, we need to copy the memoperand from the old
atomic operation to the new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 817a6a9eaa96a82c821143f13c756d7fa76cea71 |
|
16-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
x86-64 PIC JIT fixes: do not generate the extra load for external GV's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a54cf176613f9ae8301519a61b8935652c0fb8ae |
|
12-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Include a frame index in the "fixed stack" pseudo source value
instead of using the frame index for the SVOffset, which was
inconsistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71ca353ae686ce9249eb333a48f12c1e4d47a319 |
|
11-Jul-2008 |
Bill Wendling <isanbard@gmail.com> |
The frame address on an x86-64 box needs to be offset by -8, not -4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
|
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 126d90770bdb17e6925b2fe26de99aa079b7b9b3 |
|
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4bdcb61af33399d4e01fdf3c47ca1f1f5356e370 |
|
02-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add a new getMergeValues method that does not need
to be passed the list of value types, and use this
where appropriate. Inappropriate places are where
the value type list is already known and may be
long, in which case the existing method is more
efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d9ad8abc8e9759fe9fb38d0397f1ab7a04be9fd1 |
|
01-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Highlight that getMergeValues optimization is
being suppressed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4406604047423576e36657c7ede266ca42e79642 |
|
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87060f55f21a1076be83306f2efb97887d3d7654 |
|
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Update comments to new-style syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7f460203b0c5350e9b2c592f438e40f7a7de6e45 |
|
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.
This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.
This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f9516208e57364ab1e7d8748af1f59a2ea5fb572 |
|
30-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab26227c8c9adce91a606a3691d4da08a9c8551c |
|
25-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Fix a x86 vector isel bug: illegal transformation of a vector_shuffle into a
shift.
- Add a readme entry for a missing vector_shuffle optimization that results in
awful codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fd4418fc9b4725c44210c169c4d6500be468ca70 |
|
25-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Remove the OrigVT member from AtomicSDNode, as it is redundant with
the base SDNode's VTList.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 28873106309db515d58889a4c4fa3e0a92d1b60e |
|
25-Jun-2008 |
Mon P Wang <wangmp@apple.com> |
Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a68f9013f2019652892e5701a876adec1d8b7e7f |
|
25-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Add v2f32 (MMX) type to X86. Support is primitive:
load,store,call,return,bitcast. This is enough to
make call and return work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 09d3fdc254c0b922c38f7c2bcad27c02fa0904f3 |
|
22-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Remove unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c8e64d3e4a3daca9ec74c617a518d03d33eee90 |
|
19-Jun-2008 |
Eli Friedman <eli.friedman@gmail.com> |
Fix a bug with <8 x i16> shuffle lowering on X86 where parts of the
shuffle could be skipped. The check is invalid because the loop index i
doesn't correspond to the element actually inserted. The correct check is
already done a few lines earlier, for whether the element is already in
the right spot, so this shouldn't have any effect on the codegen for
code that was already correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 851bc0453350254cd45a91b6af9592003562d707 |
|
17-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rather than avoiding to wrap ISD::DECLARE GV operand in X86ISD::Wrapper, simply handle it at dagisel time with x86 specific isel code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 507a58ac9b20ddcea2e56a014be26b8f8cc0ecb8 |
|
14-Jun-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
add missing atomic intrinsic from gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 096b461b2e159c3dd158df1a75a44630a6bef906 |
|
11-Jun-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly lower DYNAMIC_STACKALLOC - bracket all black magic with
CALLSEQ_BEGIN & CALLSEQ_END.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8e4eb09b1e3571965f49edcdfb56b1375b1b7551 |
|
08-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits. Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 21323f3a829df0e6d9b4566a551619a01e269ba6 |
|
29-May-2008 |
Dan Gohman <gohman@apple.com> |
Expand small memmovs using inline code. Set the X86 threshold for expanding
memmove to a more plausible value, now that it's actually being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f26ffe987cf3643a7bd66bd9f97c34605ba7d08e |
|
29-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f7333bf4a2c3d833a971b2dc3015aa5304fb4f0d |
|
28-May-2008 |
Nate Begeman <natebegeman@mac.com> |
Don't attempt to create VZEXT_LOAD out of an extload. This an issue where the
code generator would do something like this:
f64 = load f32 <anyext>, f32mem
v2f64 = insertelt undef, %0, 0
v2f64 = insertelt %1, 0.0, 1
into
v2f64 = vzext_load f32mem
which on x86 is movsd, when you really wanted a cvtss2sd/movsd pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b924dcef859daafded64268447aeff3f60f1c08 |
|
23-May-2008 |
Dan Gohman <gohman@apple.com> |
Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add
load-folding table entries for PMULDQ and PMULLD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0ef8de30fa8dd317c8b45711fe144d39e51ecfa4 |
|
16-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix typos and comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f0df03134e698ea84e9cc1c28a853f83c02560d5 |
|
15-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 |
|
14-May-2008 |
Dan Gohman <gohman@apple.com> |
Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 77f0b7a50a08614b5ffd58f1864b68a9a30d0cb0 |
|
13-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
pshufd $1, (%rdi), %xmm0
movd %xmm0, %eax
=>
movl 4(%rdi), %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9bfa03c6fd8e02b738e0077fd1af7b18eeeeb4c1 |
|
13-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c2616e43fd980505d3b29b92473d047f878f6708 |
|
12-May-2008 |
Nate Begeman <natebegeman@mac.com> |
Initial X86 codegen support for VSETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ad4196b44ae714a6b95e238d9d96303df74b0429 |
|
12-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ce3898e410e2b9c155d52fb42a6614eadafca9e |
|
12-May-2008 |
Dan Gohman <gohman@apple.com> |
Fix a compile error on compilers that still want a return value
in a non-void function that calls abort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 50d9e7289b86fa02b8f121f5aeceffb4b248a9b6 |
|
10-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
When transforming a vector_shuffle to a load, the base address must not be an undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9018e836fe4ef55a9bcf2cc02a6a3a4ef455115f |
|
10-May-2008 |
Dan Gohman <gohman@apple.com> |
For now, abort when an ISD::VAARG is encountered on x86-64, rather
than silently generate invalid code.
llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 25210da75746362badd623be54944439b2e64dbf |
|
10-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
If movl top bits are undef, let it be selected to movlps, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d880b97257c7f8ec4e94948874cb87c865d9f96f |
|
09-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle a few more cases of folding load i64 into xmm and zero top bits.
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7e2ff77ef05c23db6b9c82bc7a4110e170d7f94c |
|
08-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab3e747c64dc5cbf00c3e0ce5275a3bfac5e56be |
|
06-May-2008 |
Mon P Wang <wangmp@apple.com> |
Improved generated code for atomic operators
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71f489d72856a0424146a1e24642dfac3ae15522 |
|
06-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 63307c335aa08b0d6a75f81d64d79af7e90eb78b |
|
05-May-2008 |
Mon P Wang <wangmp@apple.com> |
Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6625eff8ec38095e9dab31294a86555a489e56a4 |
|
04-May-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern),
but should work. Work is in progress, more models will follow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5759f97f50b49aed2f7763133a4af3aa54e24c5a |
|
04-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 30e62c098b5841259f8026df1c5c45c7c1182a38 |
|
30-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1f13c686df75ddbbe15b208606ece4846d7479a8 |
|
28-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 998a5bcc80214d4e9651dddd6a2780e7ca900eda |
|
28-Apr-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly lower vararg's FORMAL_ARGUMENTS node on win64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5e764233f398b6929b67701672a5e78fec20ce2e |
|
27-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
A few inline asm cleanups:
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 44c0fd17e11dd3a6cda81632cac5b06fb1618d93 |
|
25-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Extract the lower 64-bit if a MMX value is passed in a XMM register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 10e864276bd94886f20fa067d28d8ab2c9399bf5 |
|
25-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Special handling for MMX values being passed in either GPR64 or lower 64-bits of XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ee472b10814b00eed86f2f8cdab0cbdab431d627 |
|
25-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
MMX argument passing fixes:
On Darwin / Linux x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
On Darwin / Linux x86-32, v1i64 values are passed in memory.
On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].
On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2749c72f30a6d424a09a0f8dc87e42e103d8315b |
|
25-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix bug in x86 memcpy / memset lowering. If there are trailing bytes not handled by rep instructions, a new memcpy / memset is introduced for them. However, since source / destination addresses are already adjusted, their offsets should be zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 61a921344090457f9429e44c7906ea75ce97e020 |
|
22-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Implement an x86-64 ABI detail of passing structs by hidden first
argument. The x86-64 ABI requires the incoming value of %rdi to
be copied to %rax on exit from a function that is returning a
large C struct.
Also, add a README-X86-64 entry detailing the missed optimization
opportunity and proposing an alternative approach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 02a260aa11a2e1b2c14335274d3c42ca3f3eabc0 |
|
20-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
Switch to using Simplified ConstantFP::get API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 28269139ee22c95ab18064b453f52e4e016fa833 |
|
18-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix the handling of va_copy on x86-64. As of llvm-gcc r49920
llvm-gcc is now lowering va_copy on x86-64, so this completes
the fix for PR2230.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9cac5259fe237120a0c347d6d14e549005148f1b |
|
16-Apr-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Ongoing work on improving the instruction selection infrastructure:
Rename SDOperandImpl back to SDOperand.
Introduce the SDUse class that represents a use of the SDNode referred by
an SDOperand. Now it is more similar to Use/Value classes.
Patch is approved by Dan Gohman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 171c11ec93d74c71f7e4f8bfb9c9cd5971214b53 |
|
16-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Add support for the form of the SSE41 extractps instruction that
puts its result in a 32-bit GPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bcda285fcc98129ce48c4eda72a7f3595c7685ec |
|
16-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Recreate the size SDNode instead of reusing the old one in the x86
memcpy lowering code; this ensures that the size node has the desired
result type. This fixes a regression from r49572 with @llvm.memcpy.i64
on x86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 29e4bdbf27c5f03b12dd2bc41d9ccb0d5f3dfdf4 |
|
14-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4b5324ad2cbf774c9c6ed02ea0fcc864f2f5f885 |
|
12-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
This patch corrects the handling of byval arguments for tailcall
optimized x86-64 (and x86) calls so that they work (... at least for
my test cases).
Should fix the following problems:
Problem 1: When i introduced the optimized handling of arguments for
tail called functions (using a sequence of copyto/copyfrom virtual
registers instead of always lowering to top of the stack) i did not
handle byval arguments correctly e.g they did not work at all :).
Problem 2: On x86-64 after the arguments of the tail called function
are moved to their registers (which include ESI/RSI etc), tail call
optimization performs byval lowering which causes xSI,xDI, xCX
registers to be overwritten. This is handled in this patch by moving
the arguments to virtual registers first and after the byval lowering
the arguments are moved from those virtual registers back to
RSI/RDI/RCX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
|
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f836adafee88669273e9302e3344c4b9cef8a0d |
|
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix a bug that prevented x86-64 from using rep.movsq for
8-byte-aligned data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d8143f0ef35fccc98a624525b4517eb790e2d14 |
|
09-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Make isVectorClearMaskLegal's operand list const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dc1adac582fa120861f18ae7221bfe1421fea59f |
|
07-Apr-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Re-commit of the r48822, where the infinite looping problem discovered
by Dan Gohman is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0c0f83ff5d214a7f42e86ae62814526ba40a28cf |
|
05-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Favors pshufd over shufps when shuffling elements from one vector. pshufd is faster than shufps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6397c64441ddce3822ab0e712f224a11bd75811c |
|
03-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Backing out 48222 temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 38c92263eb83f556cdea8bf55b6d7dcc47ce131d |
|
01-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Don't use __bzero for memset if the second argument isn't zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 68d599df37218452acd5a680d5360d3caaa1623c |
|
01-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Speculatively micro-optimize memory-zeroing calls on Darwin 10.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ffbcaccd1a933aaa86bc50d2e9ba66efcc6d1fb |
|
01-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Accept 'y' constraint (MMX) in inline asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d4a2ad35e3118c9f3b7c2cf14fb12709ce52779c |
|
29-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Fix a tokenfactor node to use the load chain rather than the
load value. This fixes PR2177.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e326332acd5fefb9854118603b4d07d4e44b64c5 |
|
26-Mar-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Use a linked data structure for the uses lists of an SDNode, just like
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.
The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.
On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 62a3f1538cf50f0373c2a5eeb440d6288604f969 |
|
24-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a979d9eab68b353208cdff87b09ff703d5bf15d |
|
22-Mar-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add convenient helper for win64 check. Simplify things slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8f88cb08999187b143c6772216dd2ef18d9b7824 |
|
22-Mar-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Initial support for Win64 calling conventions. Still in early state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 276dcbdc8db6614cfd5004dc7dc35e437ddf9c58 |
|
21-Mar-2008 |
Duncan Sands <baldrick@free.fr> |
Introduce a new node for holding call argument
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 920c37afc5896201ec014041cbd270289baa25c0 |
|
21-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
remove Evan's "ugly hack" that sorta attempted to get
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 260e07ec8ceb98337a9eeb5377d97dfcc0058a25 |
|
20-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m)))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 15cbde3cf6542ec9c120f59d5d8f3586f5f332c6 |
|
19-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 586ccac4ec4d023864e720dc36373809b9b88b09 |
|
19-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 58d74910c6b82e622ecbb57d6644d48fec5a5c0f |
|
12-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Reimplement the parameter attributes support, phase #1. hilights:
1. There is now a "PAListPtr" class, which is a smart pointer around
the underlying uniqued parameter attribute list object, and manages
its refcount. It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
ParamAttrsWithIndex's, no need to make a SmallVector of a specific
size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
dereferencing the pointer is simplified to just access the
PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
bit simpler.
Phase #2 will rename some stuff (e.g. PAListPtr) and do other less
invasive changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fce84acbbc36d63cc6bc616795650cad31592ca4 |
|
11-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
start handling the 'f' x87 constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 447ff68c08bc01aa040ae6d0291af69b55bb8e57 |
|
11-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Change the model for FP Stack return to use fp operands on the
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48209 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8e6da15e54125db38c0ae32f7a6b2273c792c588 |
|
10-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
copyfromreg/copytoreg instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d2cde68855125b6815b1575f29cd96927614b0cd |
|
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Default ISD::PREFETCH to expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5b8f82e35b51bf007de07a7ca9347d804084ddf8 |
|
10-Mar-2008 |
Scott Michel <scottm@aero.org> |
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b8cafe3427a168414400e5dfcbea78996792d2c3 |
|
10-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| afb23f48a4f5f76b4a0fca870ae5a28c27dde028 |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
rename FP_SETRESULT -> FP_SET_ST0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6fa2f9c63688ff240d58c80bc0e433bb27a53c85 |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 67f453aae7ac55f30af9e961a21029beabaaf47b |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Finish implementing a readme entry: when inserting an i64 variable
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 62098040a15b492561ca59a8dc6b56d14c0859bf |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Implement a readme entry, compiling
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 19f7969f816000cf5ddf8a19163193b5feb9bc0a |
|
08-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
1) Improve comments.
2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c9517fb6eb0daee39f8d27cdca2e84a924092d11 |
|
08-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
minor simplifications to this code, don't create a dead
SCALAR_TO_VECTOR on paths that end up not using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 27b7db549e4c5bff4579d209304de5628513edeb |
|
08-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d1108222fd7b49d660fa63868cd2428fa1d49c17 |
|
07-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
mark frem as expand for all legal fp types on x86, regardless of whether
we're using SSE or not. This fixes PR2122.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d19189e9905e14a4001a8ca6fc4effb6a3f88e45 |
|
05-Mar-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
64bit CAS on 32bit x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a76e2f0331108805228453bfa071cc43ce1aa31e |
|
04-Mar-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
x86-64 atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c1fa61652d1ce633bf8a1574798f988a8a57088 |
|
03-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add support for lowering i64 SRA_PARTS and friends on x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ce1105da43341620665564faa222084f22f2c04b |
|
01-Mar-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
make CAS work
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 26ed8697d4733f4ad588ef117ec4387560770ad0 |
|
01-Mar-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
all but CAS working on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fb8075d03f5c87bd57dcc9c5f2304f6b13c55aad |
|
28-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b09916bdfbd7ffdc8fbadb5ee0c0b50567823f46 |
|
27-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
Make X86TargetLowering::LowerSINT_TO_FP return without creating a dead
stack slot and store if the SINT_TO_FP is actually legal. This allows
us to compile:
double a(double b) {return (unsigned)b;}
to:
_a:
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
ret
instead of:
_a:
subq $8, %rsp
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
addq $8, %rsp
ret
crazy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 258bb1b8e8a6c1cb3be8cb8fd9366386563f06ce |
|
26-Feb-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Refactor according to Evan's and Anton's suggestions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 16a3e52d08c4eb3e7371afb09d78528f70799aa1 |
|
26-Feb-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Correct function comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a2a4b475fc03202608fd3c298e90f24ca24f122c |
|
26-Feb-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Add support for intermodule tail calls on x86/32bit with
GOT-style position independent code. Before only tail calls to
protected/hidden functions within the same module were optimized.
Now all function calls are tail call optimized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 865c68188a72604a15c8b9b08df89d4775c7c764 |
|
26-Feb-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Change the lowering of arguments for tail call optimized
calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 14e2ea9a557069ecf6383dde509badb3070b8057 |
|
25-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Revise previous patch per review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 079f2a66ae0478a1153306d7afb1b361e56b4a02 |
|
25-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Expand removal of MMX memory copies to allow 1 level
of TokenFactor underneath chain (seems to be enough)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 22c3979fcaa7ff19c44253eb9b0b0160dfef0aa4 |
|
22-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Split ParameterAttributes.h, putting the complicated
stuff into ParamAttrsList.h. Per feedback from
ParamAttrs changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d2b1fb27df44151e153c19055ad1bd4b415b1e9d |
|
22-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
copy mmx values from/to memory with GPRs on x86-32
instead of with mmx registers. This horribleness is apparently
done by gcc to avoid having to insert emms in places that really
should have it. This is the second half of rdar://5741668.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 149a4e56fcd29c37c416e0ce4a5ebed7b514cbc6 |
|
22-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
Start using GPR's to copy around mmx value instead of mmx regs.
GCC apparently does this, and code depends on not having to do
emms when this happens. This is x86-64 only so far, second half
should handle x86-32.
rdar://5741668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7c1c261272b43f2a9397c3052819b92c53918075 |
|
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove bunch of gcc 4.3-related warnings from Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| efec751a1b786724862ceff52748df94873a807e |
|
19-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b00ee21f21858c18af20fd57c7a5e2a6d38ff70c |
|
18-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Chris pointed out that it's not necessary to set i64 MUL to Expand
on x86-32 since i64 itself is not a Legal type. And, update some
comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 339ffedca9f5f367d26507eb631fd5f929c04677 |
|
18-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Don't mark scalar integer multiplication as Expand on x86, since x86
has plain one-result scalar integer multiplication instructions.
This avoids expanding such instructions into MUL_LOHI sequences that
must be special-cased at isel time, and avoids the problem with that
code that provented memory operands from being folded.
This fixes PR1874, addressesing the most common case. The uncommon
cases of optimizing multiply-high operations will require work
in DAGCombiner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d497d9fab6e90499c703f3e672ec001dbfa074f9 |
|
16-Feb-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 00fee65fd21f9615d1a604b8b7d42cd16a3f6b47 |
|
14-Feb-2008 |
Duncan Sands <baldrick@free.fr> |
In TargetLowering::LowerCallTo, don't assert that
the return value is zero-extended if it isn't
sign-extended. It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned". Currently
isSExt is set when signed, and nothing is
set otherwise. This should be right for all
calls to standard library routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e179584f9b740cf3a36bde70f8cab40de59b8081 |
|
14-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Change how FP immediates are handled.
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f4f92f5ebe579ded661ec4c311f65e316405d0e6 |
|
14-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Assigning an APInt to 0 with plain assignment gives it a one-bit
size. Initialize these APInts to properly-sized zero values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3 |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fd29e0eb060ea8b4d490860329234d2ae5f5952e |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cdd1eeca2c2da2e1c9b48e04f2f779ffe5cf3666 |
|
12-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
SSE4.1 64b integer insert/extract pattern support
Move formats into the formats file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5ae45caf793632137bcf8c9f4857cd3fafd47018 |
|
12-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak various insert_vector_elt and extract_vector_elt tests in presence of SSE4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 14d12caf1d2de9618818646d12b30d647a860817 |
|
11-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Enable SSE4 codegen and pattern matching.
Add some notes to the README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0c191872ab61d21907d99695382e157f5d4e4b9f |
|
08-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
64-bit (MMX) vectors do not need restrictive alignment.
128-bit vectors need it only when SSE is on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46890 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 60783304f6385c952634c9da5f9b0c9eee8eccb8 |
|
08-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Avoid needlessly casting away const qualifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3069b8743769527ce7af6cfb6591a2f0fc2faee4 |
|
07-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Follow Chris' suggestion; change the PseudoSourceValue accessors
to return pointers instead of references, since this is always what
is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4fdad172deda12e10a6cf9b5c54cf9346cfaef00 |
|
07-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Add SourceValue information for outgoing argument stores on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 69de1932b350d7cdfc0ed1f4198d6f78c7822a02 |
|
06-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e672af15d6d7000fca2b39981b17403bdd5ec9ed |
|
05-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Implement sseregparm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 916a9f071f525f29bb17e96dfea99431eb3d2a38 |
|
02-Feb-2008 |
Nick Lewycky <nicholas@mxc.ca> |
Don't use uninitialized values. Fixes vec_align.ll on X86 Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a844bdeab31ef04221e7ef59a8467893584cc14d |
|
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 334dc1f58d617dcff969a2e107febaae42bbc883 |
|
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bbfb9c57c71ed4a2a4a60010b98dbfe96c984b14 |
|
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Avoid unnecessarily casting away const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a0248690aaa9f7baaf1247e5f65a1c0c9e3783c |
|
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting
with the real FLT_ROUNDS (defined in <float.h>).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c6c391daddbafa722d9ca87d18f204e9a6e617a3 |
|
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ff9b373e8f5006c629af81e2619778b4c4f5249e |
|
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0d9e976ad2c5479f3d67f8cb09a5908cfc29985c |
|
29-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results.
Status: This only works for direct calls, and only the caller side is done. Disabled for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ba2a0b960ea4c73d0f81557f63ae2ea126e08905 |
|
29-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Handle 'X' constraint in asm's better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 71d07a0dacd113b656a256c17b66b583e1ab76ec |
|
27-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Use fldz and fld1 for long double constants instead of a constant pool load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ba96fbc164e90855a7773a67669e24bad4d674c8 |
|
26-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Remove some code for inferring alignment info from the x86 backend
now that the dag combiner does it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6cf73267c6fc8f1d9287b6eba1aa202693040f53 |
|
25-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
optimize fxor like for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af723b9ae460aa42388ee15a79b68bb1c66e9775 |
|
25-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Add target-specific dag combines for FAND(x,0) and FOR(x,0). This allows
us to compile:
double test(double X) {
return copysign(0.0, X);
}
into:
_test:
andpd LCPI1_0(%rip), %xmm0
ret
instead of:
_test:
pxor %xmm1, %xmm1
andpd LCPI1_0(%rip), %xmm1
movapd %xmm0, %xmm2
andpd LCPI1_1(%rip), %xmm2
movapd %xmm1, %xmm0
orpd %xmm2, %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d43d00cf3ae44b94162552b19e4cf2491bc0533e |
|
24-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 29286502628867b31872ead2f2527592480f0970 |
|
24-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Let each target decide byval alignment. For X86, it's 4-byte unless the aggregare contains SSE vector(s). For x86-64, it's max of 8 or alignment of the type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f9c98e650d2795b8edfae8e1560c221029df218b |
|
23-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
The last pieces needed for loading arbitrary
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ddf89566a93081cb230bb9406a72ab2d3eada4a7 |
|
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0bd4893a0726889b942405262e53d06cf3fe3be8 |
|
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
* Introduce a new SelectionDAG::getIntPtrConstant method
and switch various codegen pieces and the X86 backend over
to using it.
* Add some comments to SelectionDAGNodes.h
* Introduce a second argument to FP_ROUND, which indicates
whether the FP_ROUND changes the value of its input. If
not it is safe to xform things like fp_extend(fp_round(x)) -> x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 339e14fbdc9560cb58091d214c7d628f6dcf7c7d |
|
16-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
Trampoline support for x86-64. This looks like
it should work, but I have no machine to test
it on. Committed because it will at least
cause no harm, and maybe someone can test it
for me!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 78631168d1179415c466620ec99ec626d4a35956 |
|
16-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
make it more clear that this predicate only applies to scalar FP types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1956d1567671ef083efc19c001f5c1d121542aa6 |
|
16-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
introduce a isTypeInSSEReg predicate, which allows us to simplify
some code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7ff79c2d9d5e0c014ca8283cd38f5fbf3dd67790 |
|
16-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
My previous commit had an incomplete message, it should have been:
make the 'fp return in ST(0)' optimization smart enough to
look through token factor nodes. THis allows us to compile
testcases like CodeGen/X86/fp-stack-retcopy.ll into:
_carg:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
fldl (%esp)
addl $12, %esp
ret
instead of:
_carg:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
Still not optimal, but much better and this is a trivial patch. Fixing
the rest requires invasive surgery that is is not llvm 2.2 material.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46054 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 142fb3fee8ebdcf5a501f6fc7d4dfe909e9c478e |
|
16-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
make the 'fp return in ST(0)' optimization smart enough to
look through token factor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b4a6eaa75b0069756045555de621c9616d1bcac5 |
|
16-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
various whitespace cleanups, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46052 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da68d30d24f3f25444793c6d8c3c5a614e523eaa |
|
15-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
no need to expand ISD::TRAP to X86ISD::TRAP, just match ISD::TRAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 66fac79b899904ddd82e5ee354a6d370d80230f6 |
|
15-Jan-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
For PR1839: add initial support for __builtin_trap. llvm-gcc part is missed
as well as PPC codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9e9cf0ce3134f900037abb8c95165eb0f4cb1f90 |
|
13-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
Whitespace tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8e5712b8bb55229d26027e62fd18285065c05338 |
|
12-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a51cf0f074d1b11cb904e44984aa0a48a817dc04 |
|
11-Jan-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
hrm - correct spelling.
Actually were not riding any arguments. Sadly there is no semantic spell checker that is going to safe you from such a mistake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c8ab8cde43f52c1b47448d853035a1d69cf5ab62 |
|
11-Jan-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Improve tail call optimized call's argument lowering. Before this
commit all arguments where moved to the stack slot where they would
reside on a normal function call before the lowering to the tail call
stack slot. This was done to prevent arguments overwriting each other.
Now only arguments sourcing from a FORMAL_ARGUMENTS node or a
CopyFromReg node with virtual register (could also be a caller's
argument) are lowered indirectly.
--This line, and those below, will be ignored--
M X86/X86ISelLowering.cpp
M X86/README.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45867 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 719eb02255efaeb322c1927741b784607296e738 |
|
11-Jan-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Correct a copy and paste error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e70bb598403660463dc21b77e0aa11666507a866 |
|
10-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Mark byval parameter stack objects mutable for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 27a446afaf17a12a08c8c883416e7acc2f300acb |
|
10-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Do not use the stack pointer directly, issue a copyfromreg instead. Otherwise we can end up with something like ADD32ri %esp, x which two-address pass won't like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dffbd837b86f068e708cec93dba0778033473fd4 |
|
10-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove comments that do not correspond to anything after recent refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b44944d3d46bb855b2aa48094628189004c8c51 |
|
08-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 219f67f0a5f07032f06e36c71fdb84188cc29fdb |
|
05-Jan-2008 |
Nate Begeman <natebegeman@mac.com> |
Remove an incorrect optimization that is performed correctly by
the target independent legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 86737665b81550fdb575f7d8cc5decc801a7813d |
|
05-Jan-2008 |
Gordon Henriksen <gordonhenriksen@mac.com> |
Refactoring the x86 and x86-64 calling convention implementations,
unifying the copied algorithms and saving over 500 LOC. There should
be no functionality change, but please test on your favorite x86
target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ae636f8e997294fd997ae8b91e17c4f63b269cc2 |
|
03-Jan-2008 |
Gordon Henriksen <gordonhenriksen@mac.com> |
First steps in in X86 calling convention cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8aa797aa51cd4ea1ec6f46f4891a6897944b75b2 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d60eedca018895df83968d052230129bc25731cb |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Codegen:
as:
_bar:
pushl %esi
subl $8, %esp
movl 16(%esp), %esi
call L_foo$stub
fstps (%esi)
addl $8, %esp
popl %esi
#FP_REG_KILL
ret
instead of:
_bar:
pushl %esi
subl $8, %esp
movl 16(%esp), %esi
call L_foo$stub
fstpl (%esi)
cvtsd2ss (%esi), %xmm0
movss %xmm0, (%esi)
addl $8, %esp
popl %esi
#FP_REG_KILL
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 112dedc520c1aec387a6fef1c8f512a7d27f0570 |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
avoid going through a stack slot to convert from fpstack to xmm reg
if we are just going to store it back anyway. This improves things
like:
double foo();
void bar(double *P) { *P = foo(); }
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 48b0133b8393ca3ff09bc1c55250eb11d4bcaf04 |
|
16-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
fix a questionable cast, thanks to Mike Stump for pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7a831ce85f79a950c3bea2bcfbeda35f9bab9cdb |
|
15-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Make better use of instructions that clear high bits; fix various 2-wide shuffle bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 152804e9c1a9fad358a7a5298cd01d4af0f8cf47 |
|
14-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix ctlz and cttz. llvm definition requires them to return number of bits in of the src type when value is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 18efe269b12624d74c0af6104e88864d6a932344 |
|
14-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implement ctlz and cttz with bsr and bsf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 890813243f9b4f5aa9c6d5ab79ffe948458197ab |
|
12-Dec-2007 |
Dan Gohman <gohman@apple.com> |
Allow vector integer constants to be created with
SelectionDAG::getConstant, in the same way as vector floating-point
constants. This allows the legalize expansion code for @llvm.ctpop and
friends to be usable with vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 794405e6aa012e33d8e619e058d03b8600312208 |
|
12-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use shuffles to implement insert_vector_elt for i32, i64, f32, and f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| db2d524d5f491d55ff1f10809636981cc7506a74 |
|
12-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Lower a build_vector with all constants into a constpool load unless it can be done with a move to low part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 14b32e194152f7147d6f531346b923152e58900f |
|
11-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Improved v8i16 shuffle lowering. It now uses pshuflw and pshufhw as much as
possible before resorting to pextrw and pinsrw.
- Better codegen for v4i32 shuffles masquerading as v8i16 or v16i8 shuffles.
- Improves (i16 extract_vector_element 0) codegen by recognizing
(i32 extract_vector_element 0) does not require a pextrw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 844e0f9def5d1caa28e1f2612cb4226e14fd22b3 |
|
11-Dec-2007 |
Nate Begeman <natebegeman@mac.com> |
x86 doesn't actually want to custom lower v3i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 779ccea5b624eae7f2440444e342339aa372f42c |
|
07-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a86c3f3aee55f68cc227362031596edd93f7170 |
|
07-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Much improved v8i16 shuffles. (Step 1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1076210ee30c7b0ed2b43830d0aa7bd3c3218547 |
|
06-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove a bogus optimization. It's not possible to do a move to low element to a <8 x i16> or <16 x i8> vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dc024674ff96820d6020757b48d47f46d4c07db2 |
|
27-Nov-2007 |
Duncan Sands <baldrick@free.fr> |
Fix PR1146: parameter attributes are longer part of
the function type, instead they belong to functions
and function calls. This is an updated and slightly
corrected version of Reid Spencer's original patch.
The only known problem is that auto-upgrading of
bitcode files doesn't seem to work properly (see
test/Bitcode/AutoUpgradeIntrinsics.ll). Hopefully
a bitcode guru (who might that be? :) ) will fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8a594489bf2e4b533f6403549afb7d5de417c9e4 |
|
25-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a long standing deficiency in the X86 backend: we would
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0a3209210308429b266647c1b3a661aa25b44cdb |
|
24-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
remove bogus assertion that broke CodeGen/Generic/cast-fp.ll on x86
among others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 27a6c7380fa4dfc8e1837a8dd67967d063b26544 |
|
24-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to
take and return entire NODES that need a result expanded, not just
the value. This allows us to handle things like READCYCLECOUNTER,
which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
ExpandOperationResult. This makes the result simpler and fully
general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
allowing them to work with LegalizeDAGTypes.
LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 45b22fa9f1f085d7971cce6db4f11b353e1646c6 |
|
16-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement codegen for flt_rounds on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50 |
|
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 38ada868f24b639512e4cfe07871ccea05e09f1a |
|
10-Nov-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Update tailcall code to include inline attribute operand for memcpy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cc41586b9d79532172b37e1f44a9077da4b73fc9 |
|
09-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Much improved pic jumptable codegen:
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f1ba1cad387dc52f3c2c5afc665edf9caad00992 |
|
06-Nov-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 03e6c7091e1b6f37d6ba55ad3ee1c2cba10ec8e4 |
|
04-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Fix PR1763 by allowing the 'q' constraint to work with 64-bit
regs on x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a9d641e574b350b75d43c7481d6b6c4a7fba1c01 |
|
02-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak tailcall opt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43646 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9df7dc52e8fd5c69a5d6464d02b7496091e18c29 |
|
02-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Missing a getNumOperands check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e0703c84ddeb1a1276de4e38210c1127ef5df130 |
|
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
and by restructuring the X86 version.
New I just have to move this to a common place :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fc05f402ea22e8a9ae465d209b65be7e857a89ff |
|
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 25f1d08619720b82e7c944b18eee488fc07ba153 |
|
31-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Make i64=expand_vector_elt(v2i64) work in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43535 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8d26e594f0d90f2693074a0af5ffaf52ee7875a1 |
|
30-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Add missing MMX PSUBQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3c3ddb3a856e44c603cb8cf8f52ff9c0f06ff14a |
|
29-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Enable more fold (sext (load x)) -> (sext (truncate (sextload x)))
transformation. Previously, it's restricted by ensuring the number of load uses
is one. Now the restriction is loosened up by allowing setcc uses to be
"extended" (e.g. setcc x, c, eq -> setcc sext(x), sext(c), eq).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e127a73154084e88d0eb6e7190660759b7141c55 |
|
29-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Avoid doing something dumb like rewriting using a 64-bit iv in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2bd122c4d934a70e031dc0ca5171719bac66c2c9 |
|
26-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free.
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
movw %dx, %si
LBB1_2: # bb
movl L_X$non_lazy_ptr, %edi
movw %si, (%edi)
movl L_Y$non_lazy_ptr, %edi
movw %dx, (%edi)
addw $4, %dx
incw %si
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
into
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: # bb
movl L_X$non_lazy_ptr, %esi
movw %cx, (%esi)
movl L_Y$non_lazy_ptr, %esi
movw %dx, (%esi)
addw $4, %dx
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 61c7ef34e35dbf059cfc1add03780343dfe33459 |
|
21-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Allow for copysign having f80 second argument.
Fixes 5550319.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5c0d6ed325417baa5d119af9c2b6790231d8565f |
|
19-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for byval function whose argument is not 32 bit aligned.
To do this it is necessary to add a "always inline" argument to the
memcpy node. For completeness I have also added this node to memmove
and memset. I have also added getMem* functions, because the extra
argument makes it cumbersome to use getNode and because I get confused
by it :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7ef1a4bf0401d54ce88d10bcb4d1a2e98663a843 |
|
17-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
Change fp to sint legalization on x86-32 to do 2 x i32
loads instead of 1 x i64 loads. This doesn't change any functionality yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ff75ee9ab90d2f44d6425f03af14077fb747a20 |
|
17-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
fix some funny indentation, add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c274f54ed8b19b445b7fce6895eaa2673b9c391e |
|
16-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Check for invalid cc's in f80 select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 448175fd020acd680c27e61a3aa09d23031a496d |
|
16-Oct-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Correction to tail call optimization code. The new return address
was stored to the acutal stack slot before the parameters were
lowered to their stack slot. This could cause arguments to be
overwritten by the return address if the called function had less
parameters than the caller function. The update should remove the
last failing test case of llc-beta: SPASS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87c8935fd55f3177e787e192b5ed4686b6073c61 |
|
15-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
LowerFP_TO_SINT must not create a stack object if it's not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 364460156360ad2620df29fa18caab108e481754 |
|
14-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 92226dd19fa946998488f419b8c4a096782ded3c |
|
12-Oct-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Correcting the corrections. Bad bad baaad emacs!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 48abc5cf6ba6d53513034aa8c68b0a9abd748190 |
|
12-Oct-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Corrected many typing errors. And removed 'nest' parameter handling
for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2e4d675d9382bea5767e3b2f35f0c5a01a15bd7b |
|
12-Oct-2007 |
Duncan Sands <baldrick@free.fr> |
Due to the new tail call optimization, trampolines can no
longer be created for fastcc functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f0d008934051181e1b879f7383cb333f8770d116 |
|
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Mark vector ctpop, cttz, and ctlz as Expand on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f96e4de403453e57aea75bcac1ed99af686d33c4 |
|
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Set ISD::FPOW to Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c85e1716f0e45e4c18a9ef2fbe431a51ac3a4252 |
|
11-Oct-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Added tail call optimization to the x86 back end. It can be
enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3f41d66d75e0400371a123d2b04624ee5122225d |
|
09-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Bug fix. X86 was emitting redundant setcc and test instructions before a conditional move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42774 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 525178cdbf00720ea8bce297a7d65b0cca0ab439 |
|
08-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| afa98bcf3d9abe4d3887f11120cf904d89737805 |
|
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Not needed any more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e5f6204cd5d2306379bf8954e280ad35619a38b5 |
|
29-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Enabling new condition code modeling scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 068317bfa37ec52ae25f3b2fa3194bea3e7c6027 |
|
28-Sep-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Refactor the memcpy lowering for the x86 target.
The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC behavior and is
better since the run time value can be arbitrarily large.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f42901dff5d0b4a9bb571a2f57157c296584557 |
|
26-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
Enable codegen for long double abs, sin, cos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a35edba13f35ef251e047e5654f35310239bf76 |
|
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
translateX86CC updates the last two operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a37c9f7506af622b9f29a35466b33c650c75e9f7 |
|
25-Sep-2007 |
Dan Gohman <gohman@apple.com> |
When both x/y and x%y are needed (x and y both scalar integer), compute
both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c3b0b5ca1d5772cf90c0c66e03412da33a0d7cdb |
|
25-Sep-2007 |
Dan Gohman <gohman@apple.com> |
Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) and
the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0488db9b99fcfca407e859ef5cccf40dea23de16 |
|
25-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a5a403d7665613f1d1f9a4c084d85c685b1a361a |
|
24-Sep-2007 |
Dan Gohman <gohman@apple.com> |
Add support on x86 for having Legalize lower ISD::LOCATION to ISD::DEBUG_LOC
instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b4baf169299141692e07adedeff691b71e95fda |
|
24-Sep-2007 |
Chris Lattner <sabre@nondot.org> |
claim that "st" is from the 80-bit register file. This causes x87-using inline
asm to die with:
ScheduleDAG.cpp:269: failed assertion `false && "Couldn't find the register class"'
instead of:
failed assertion `RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"'
yay.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f1fc3a8fa6d4e81e30c08983d786c640acb2591c |
|
23-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
Fix PR 1681. When X86 target uses +sse -sse2,
keep f32 in SSE registers and f64 in x87. This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a37ac9ff53ebfe4975141f0d233e8ff6e5879472 |
|
21-Sep-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't add a default STACK_ALIGN (use the generic ABI alignment)
Implement calls to functions with byval arguments on X86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1242d2809311db22712e2dededb4d6904948f45f |
|
21-Sep-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
small cleanup: use LowerMemArgument in LowerFastCCArguments also
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 73328d14acba0144f121b557ce0e1539c6a21a18 |
|
20-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
More long double fixes. x86_64 should build now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5f6913cecd9f760c02754772cb57fa4d9a96624f |
|
17-Sep-2007 |
Dan Gohman <gohman@apple.com> |
Emit integer x<1 as x<=0, as comparisons with zero (now includeing
64-bit) can use test instead of cmp with an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9e3d3abd937c9bb79d56d25ec0e0724c7cbba67c |
|
15-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
Remove the assumption that FP's are either float or
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7effac5475c9057dd1c384d33f41d518ff387207 |
|
14-Sep-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for functions with byval arguments on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3f6eb7419de437436265831fce92f62498556e08 |
|
11-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
Add APInt interfaces to APFloat (allows directly
access to bits). Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling
(untested, probably does not work).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f7331b3dd72409e644833ecaf62a0f6db03c97ee |
|
11-Sep-2007 |
Duncan Sands <baldrick@free.fr> |
Fold the adjust_trampoline intrinsic into
init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 43421b3dd70af5b70e71816521f37502c397cc65 |
|
06-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
Next round of APFloat changes.
Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double. Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 382526239944023e435833ce759f536fec4e6225 |
|
03-Sep-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Reapply r41578 with proper fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1b5dcc34b701639f94008658a2042abc43b9b910 |
|
31-Aug-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Initial support for calling functions with byval arguments on x86-64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eaf089430e7681fcddc3465c3b33b9645273ab02 |
|
31-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f04afdbb48568ef09f11fd10ac03426101f2dbf8 |
|
30-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Change LegalFPImmediates to use APFloat.
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ee465749313579ccd91575ca8acf70b75c221a2c |
|
29-Aug-2007 |
Duncan Sands <baldrick@free.fr> |
Move getX86RegNum into X86RegisterInfo and use it
in the trampoline lowering. Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 44c8265cf86ba3cfc317605726296474aa8d7fa6 |
|
27-Aug-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a comment about using libc memset/memcpy or generating inline code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b83b5d1ae07dcd1c5987f7548ed2cf4be73b6a1 |
|
27-Aug-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
call libc memcpy/memset if array size is bigger then threshold.
Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 48884cd80b52be1528618f2e9b3425ac24e7b5ca |
|
25-Aug-2007 |
Chris Lattner <sabre@nondot.org> |
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
changing the interface to allow for future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 21485be444bd132941faf4e5653ac34b3ec74040 |
|
20-Aug-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Partial implementation of calling functions with byval arguments:
*) The needed information is propagated to the DAG
*) The X86-64 backend detects it and aborts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a2780e11ef0b757f0e5851bcf76c28c2f07dd379 |
|
15-Aug-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed
hard to catch bugs with retaddr lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 12914380ed1fb5e7601e3eb1be1791148f0014de |
|
14-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a typo pointd out by Maarten ter Huurne.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c59e52108bbfca50b23c5d10706484d4b012c344 |
|
10-Aug-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 594d37e21aea4ef841d9ee5d9c328c4bf1c6bed7 |
|
10-Aug-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
propagate struct size and alignment of byval arguments to the DAG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5411a3937f4303f9c3fc50be92f985a4532d95e6 |
|
09-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
long double 9 of N. This finishes up the X86-32 bits
(constants are still not handled). Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a996d52e3767fb560774dfd8bc911c927ed5ca9f |
|
07-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Long double patch 7 of N, unless I lost count:).
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 59a587337e1c3bde6c0c560ad34f9ee73bb78328 |
|
05-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Long double patch 4 of N: initial x87 implementation.
Lots of problems yet but some simple things work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7f55fcbc6bec56662e46d35ca604553effb7a525 |
|
02-Aug-2007 |
Dan Gohman <gohman@apple.com> |
Fix the alignment requirements of several unpck and shuf instructions.
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5278784621bd6f77cad3c6b8388290aa5c5870ec |
|
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Can't handle offset and scale if rip-relative addressing is to be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4ebcc8c2f8f91230066198cd9919766d9e8a4ef1 |
|
31-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
This isn't safe when there are uses of load's chain result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b116fac90f9b54142ac511a30b4d45b54d3508ba |
|
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Trampoline codegen support for X86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d300622ebacde5bffb5b5e58142323e505df9dbe |
|
27-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Re-apply 40504, but with a fix for the segfault it caused in oggenc:
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3e22947d9acef08486c59349702cfb77ef734fbf |
|
27-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Reverting 40504 for now. It's breaking oggenc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d3283832aa4a4df96194157bc3e368c43569dde2 |
|
26-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the
x86 target, replacing them with the new alignment attributes on memory
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a394117bc0a7a94d99869e2e83ff0647d3aff9a6 |
|
25-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Use movaps to load a v4f32 build_vector of all-constant values into a
register instead of loading each element individually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 275769a77acd8f0dadbf9ca03384b31c9f1c3e01 |
|
23-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Fix some uses of dyn_cast to be uses of cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d4d01b71a7c3cf3b0901ccbb8a49c9e1e7cedcb4 |
|
20-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix custom lowering of SSE FXOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2365f51ed03afe6993bae962fdc2e5a956a64cd5 |
|
14-Jul-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2038252c6a36efd18cc0bef216fa2c5bb9236617 |
|
10-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4304bcc1edd75c8db64b46c3f99871a8bb4515a7 |
|
05-Jul-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Proper flag __alloca call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e377d4d142d7e2ec9266435087c99ffc43f394aa |
|
04-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Refactor X87 instructions. As a side effect, all
their names are changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 849f214a4e3676e41168b0c5398165c4d4fb99f8 |
|
03-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Fix for PR 1505 (and 1489). Rewrite X87 register
model to include f32 variants. Some factoring
improvments forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a72cb0ea0925e19ed5278b400bcedfe024cdd01c |
|
29-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
No vector fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0db5862cb88523b8ea2daf7e93650ec04bf6c1d5 |
|
29-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Type of vector extract / insert index operand should be iPTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37784 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7f32156bb9c017b71971c52fac892fa7b9b06dd2 |
|
25-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Generalize MVT::ValueType and associated functions to be able to represent
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
|
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 52387be1e00291a88edc4c2b8a0b5c22478bcd83 |
|
19-Jun-2007 |
Chris Lattner <sabre@nondot.org> |
If a function is vararg, never pass inreg arguments in registers. Thanks to
Anton for half of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 49892af2643cb81d33209a5f30ba02a04d6d52bc |
|
19-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a9e64f6f2d60f81e315b96b0a0ea5370aca021da |
|
17-Jun-2007 |
Bill Wendling <isanbard@gmail.com> |
Revert patch. It regresses:
define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e81369f2a566b4ac482b0b39814af5a3ba80eac8 |
|
16-Jun-2007 |
Bill Wendling <isanbard@gmail.com> |
Fix a failure to bit_convert from integer GPR to MMX register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 51eaa86758338d5935c0eff0469c418b1256aba7 |
|
15-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fdbe720416786c754d23e9282b15dc0b648b6e3c |
|
09-Jun-2007 |
Chris Lattner <sabre@nondot.org> |
fix x86-64 mmx calling convention for real, which passes in integer gprs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37534 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b7c21cc303f3435d496f1799b570337b4d119fd |
|
09-Jun-2007 |
Chris Lattner <sabre@nondot.org> |
fix mmx handling bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37533 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 237898ac1f6f6d1915282cc3afaa3c36435e76c0 |
|
24-May-2007 |
Dan Gohman <gohman@apple.com> |
Add explicit qualification for namespace MVT members.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fa0f77d9b754af16b21634c71ef98a7b8103c447 |
|
18-May-2007 |
Dan Gohman <gohman@apple.com> |
Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 213d2cf94f8f2252253056e37552c9088dd11fc8 |
|
17-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 07c70cd86629846a2584e7311964e9f7753c94b0 |
|
17-May-2007 |
Chris Lattner <sabre@nondot.org> |
This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't
cause other regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f84020295363fbcdb5c5d22d0c2bac53990d5992 |
|
17-May-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Revert patch for PR1427. It breaks almost all vector tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da66472ea65d1624ce8e401598dfffa77aafc6df |
|
17-May-2007 |
Chris Lattner <sabre@nondot.org> |
Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 709fd414e2e5c3f3f282864a16688409ea152706 |
|
15-May-2007 |
Chris Lattner <sabre@nondot.org> |
fix subtle bugs in inline asm operand selection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dc43a88b81f3d1766688082aa23a5203731fd248 |
|
03-May-2007 |
Chris Lattner <sabre@nondot.org> |
Fix two classes of bugs:
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
2. the matcher didn't correctly reject and accept some global addresses.
the right predicate is GVRequiresExtraLoad, not "relomodel = pic".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ce3b46552a03f502e56fb3c4db82f3f92c09eff9 |
|
02-May-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit correct register move information in eh frames for X86. This allows Shootout-C++/except to pass on x86/linux
with non-llvm-compiled (e.g. "native") unwind runtime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f9bb1a0a47622d959ec0cee25a7346c55066817 |
|
24-Apr-2007 |
Bill Wendling <isanbard@gmail.com> |
Support for the special case of a vector with the canonical form:
vector_shuffle v1, v2, <2, 6, 3, 7>
I.e.
vector_shuffle v, undef, <2, 2, 3, 3>
MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d2cc2b98364abc3637639ee9c10aa3ecbf6e028 |
|
23-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
X86 TLS: fix and optimize the implementation of "initial exec" model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c5c111b6c144b05718404c85b9dfcc76b1619e7 |
|
21-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
X86 TLS: Implement review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b3a0417cad8b625acc3033bd5e24afb9ffd0b084 |
|
20-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Implement "general dynamic", "initial exec" and "local exec" TLS models for
X86 32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e060b5385f29ea36a9736bfa509b5a7644932ec3 |
|
17-Apr-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d15dff24c6a3712298e16453eb8d09c4404563a5 |
|
17-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
rename X86FunctionInfo to X86MachineFunctionInfo to match the header file
it is defined in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 57fc00d5cf47343ba762493b8781ca0b14489c35 |
|
17-Apr-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
Also, fixed static case in presence of eax livin. This fixes PR331
PS: Why don't we still have push/pop instructions? :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bed2946a96ecb15b0b636fa74cb26ce61b1c648e |
|
16-Apr-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6c284d716ea1d81ba9206e48c7d2590e1b78e89e |
|
12-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix mmx paddq, add support for the 'y' register class, though it isn't tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eb8c74ddf26a29bec68cd18454f6963e9ddca63e |
|
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove some dead hooks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b445d0cbb9b299ba8ec7be2494e35c501b6d3a93 |
|
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove some dead target hooks, subsumed by isLegalAddressingMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0f65cad57f041a2e7d3e6e11809a795c13cbfec7 |
|
09-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
move a bunch of register constraints from being handled by
getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint. This allows us to let the llvm register allocator
allocate, which gives us better code. For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:
_run_init_process:
subl $4, %esp
movl %ebx, (%esp)
xorl %ebx, %ebx
movl $11, %eax
movl %ebx, %ecx
movl %ebx, %edx
# InlineAsm Start
push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
Now we get:
_run_init_process:
xorl %ecx, %ecx
movl $11, %eax
movl %ecx, %edx
# InlineAsm Start
push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e5a24ec782142ea90be1f24d19faa5fa11598c49 |
|
09-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values
used with x constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ad043e85f8916c2a932cdd5893f0f2dd75a16994 |
|
09-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
implement CodeGen/X86/inline-asm-x-scalar.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c9addb74883fef318140272768422656a694341f |
|
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
implement the new addressing mode description hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a80d7bd66533916b377470dbb1fa7a00f10e33cb |
|
28-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Remove cruft I put in there...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 826f36ff80e318e8dc72f62ac72579137e30dc23 |
|
28-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ccc44add81630c880197beb39a6e083f62a97d5e |
|
27-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Fix so that pandn is emitted instead of an xor/and combo. Add integer
comparison operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab5b49d92e8bdcad5d05e96a7b8390944de7ac1a |
|
26-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Promote to v1i64 type...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eebc8a1bc505ebb5c702e63c248a8956d88fda77 |
|
26-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Add support for the v1i64 type. This makes better code for this:
#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4234f57fa02b1f04a9f52a7b3c2aa22d32ac521c |
|
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 188b9fe834a533c9c9e928005c9c0319012692d4 |
|
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
enforce the proper range for the i386 N constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a348c56fdee38b4d52c4e54ca9d8bea799dda345 |
|
22-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Support added for shifts and unpacking MMX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fa4bce2b76c8557cfd0794beef86efe5fb0087fa |
|
21-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
repair x86 performance, dejagnu problems from previous change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d435dbcbf9fb69fd5dc9d8c5a886ea3200fa8f83 |
|
19-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
fix a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 84f7fd24837be3375a30d45b30073b8a3a154dbb |
|
17-Mar-2007 |
Devang Patel <dpatel@apple.com> |
Support 'I' inline asm constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1b7a81d3aefbbdd0681c78fa00261e3d39454360 |
|
16-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
And now support for MMX logical operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 74027e98f1127fd7a91305e7fa7876f15c1c4e59 |
|
15-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Multiplication support for MMX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ba693005e9bfad78835f3280aa204233fc882f63 |
|
14-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Under X86-64 large code model, do not emit 32-bit pc relative calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a8a155e77f6216d762f218bedd326c5c3bb08f99 |
|
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
More flexible TargetLowering LSR hooks for testing whether an immediate is
a legal target address immediate or scale.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37e8856f74905b664a6506a8ce8f145e3f36184c |
|
12-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Stupid bug: SSE2 supports v2i64 add / sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c1fb0473ed415824bf6ffdbd8d6e3c4a31db3d62 |
|
10-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Adding more arithmetic operators to MMX. This is an almost exact copy of
the addition. Please let me know if you have suggestions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2f88dcdfb3a9c9592da93dcf3f0e0a9333932187 |
|
08-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
moves, loads, etc. are recognized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d0b82b301d700217a716526f9329bb031e0d6578 |
|
07-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bc9bffa27b2acf2363c5a05d88ee3b12a0b5382d |
|
07-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Properly support v8i8 and v4i16 types. It now converts them to v2i32 for
load and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a31bd27f12d9279d59d0560f6452c48f384bf02c |
|
06-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Add LOAD/STORE support for MMX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1d9baccc9b4d664a944f82eef9f708125e3f1552 |
|
06-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use new SDIselParamAttr enumeration. This removes "magick" constants
from formal attributes' flags processing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ae6421935bd3f2e48346fd16a21297ed1a28fd32 |
|
03-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8* }.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f7dcfa81c5fd2f6caddb9e3aef0ade29c5ca1048 |
|
02-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Simplify things
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 82932a5e4a2911cd5faa6376fa9d5dfac9e52091 |
|
02-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
argument lowering should copy from the vreg shadows of live-in arguments
passed in registers, not directly from the pregs themselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9dd9abd87f77da4e523db02a396721e34631ef32 |
|
01-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Ensure that fastcall'ed function is correctly mangled & stack is
properly aligned
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eac6607d7c3239009613aaf6647e5af471b5be98 |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
remove dead option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e32bbf61c0897ee00518392d0ab74c7fcd8ca01a |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
use high-level functions in CCState
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 638402b2539f2f28ab22eebf27e8309acaff405d |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
make use of helper functions in CCState for analyzing formals and calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f5d280a0a649a879f6571fe7c3a7cf5dc5d50cc1 |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
switch LowerFastCCCallTo over to using the new fastcall description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fc664c1bc0044d05dbbb1a3740203024ba05fb6e |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
switch LowerFastCCArguments over to using the autogenerated Fastcall description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fcf1a3de7a54d410678654bdbcd58b5bc924759c |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
rearrange code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2db39b865e689681d39948691e06531dc4f3356c |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
remove fastcc (not fastcall) support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f39f771b02d81956213003807ff3e4f3218dab1c |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
switch LowerCCCArguments over to using autogenerated CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c0bdf3460c195c3a590327f92d8d4d7c59b23a83 |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
simplify sret handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 423c5f44f84ae3de8de9c2498ded37ad7050acff |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
switch LowerCCCCallTo over to using an autogenerated callingconv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 59ed56b9ee4ac2f09cf5c95acbe05b5b91a77215 |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
switch return value passing and the x86-64 calling convention information
over to being autogenerated from the X86CallingConv.td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9774c915f1d27ba6de6b886c537f5fcfab81fd2d |
|
27-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
switch x86-64 return value lowering over to using same mechanism as argument
lowering uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 13513b7a50f5b4497c276796e00ef9bae730d8e0 |
|
27-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Minor refactoring of CC Lowering interfaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 362e98a5f5cf1919ac6435ff5b630b58ecd95fc5 |
|
27-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
move CC Lowering stuff to its own public interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9c71ab77cd591280cc2e79c464a9fbd4efd9bfb8 |
|
27-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
refactor x86-64 argument lowering yet again, this time eliminating templates,
'clients', etc, and adding CCValAssign instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6e50f8cfe9aad6eb0aab81cf7ef0819cd90ce34c |
|
26-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
switch to smallvector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 14dd4c97354c82301fe358e65f68e3ce5b031182 |
|
26-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
initial hack at splitting the x86-64 calling convention info out from the
mechanics that process it. I'm still not happy with this, but it's a step
in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cc7b07a0ff8311ae438bb172f54c5824194e7f8d |
|
26-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
the truncate must always be done, it's only the assert that is conditional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| df5cdb52887bf0ce57473053cf955152ce92b568 |
|
26-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
in X86-64 CCC, i8/i16 arguments are already properly zext/sext'd on input.
Capture this so that downstream zext/sext's are optimized out. This
compiles:
int test(short X) { return (int)X; }
to:
_test:
movl %edi, %eax
ret
instead of:
_test:
movswl %di, %eax
ret
GCC produces this bizarre code:
_test:
movw %di, -12(%rsp)
movswl -12(%rsp),%eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c30654cc96869149fea7b5ac091c2cd3459591e4 |
|
26-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Fix an X86-64 abi bug. We now compile:
void foo(short);
void bar(unsigned short A) {
foo(A);
}
into:
_bar:
subq $8, %rsp
movswl %di, %edi
call _foo
addq $8, %rsp
ret
instead of:
_bar:
subq $8, %rsp
call _foo
addq $8, %rsp
ret
Testcase here: test/CodeGen/X86/x86-64-shortint.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7e22977c0fab3bc46745c8aa4155db6c77663a58 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
fix CodeGen/X86/2007-02-25-FastCCStack.ll, a regression from my patch last
night: fastcc returns should only go in XMM0 if we have SSE2 or above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5e265b29ea1420db59b943bf95a1cb14fa9ca8c5 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
fastcc functions that return double values now return them in xmm0 on x86-32.
This implements CodeGen/X86/fp-stack-ret.ll:test[23]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4dfccf4b484f1a726189876d362c7ad541b94d1c |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
allow vectors to be passed to stdcall/fastcall functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2a9bdd74f2fc91186d0d789827a8382e1a20b631 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
move LowerRET into the 'Return Value Calling Convention Implementation'
section of the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 339b439d47d4d91eebe1ffb2684746f5cf586362 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
make all Lower*CallTo implementations use LowerCallResult to handle their
result value stuff. This eliminates a bunch of duplicated code and now
GetRetValueLocs is the sole place that decides where a value is returned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 09c75a43722e2aa00df4e31af35d97a6f598c28c |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
pass the calling convention into Lower*CallTo, instead of using ad-hoc flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3085e1511750b7d69bf5f1831696e0d178bdb5b1 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
factor a bunch of code out of LowerCCCCallTo into a new LowerCallResult
function. This function now uses GetRetValueLocs to determine *where*
the result values are located and concerns itself with *how* to pull the
values out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2b02a4409f8ca4c4508be8bdba0a4d16cc612553 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
move some code around, pass in calling conv, even though it is unused
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cb18656734c374737f27c10750a3b532ac41ab26 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
simplify result value lowering by splitting the selection of *where* to return
registers out from the logic of *how* to return them.
This changes X86-64 to mark EAX live out when returning a 32-bit value,
where before it marked RAX liveout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d53a1c45eec9deed3b02678c59303d843fc7751 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
make void-return not a special case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5a88b837f2387db7d12365db931e5f3499560c63 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
eliminate a bunch more temporary vectors from X86 lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d96d0723323847156928fd34d3f049311ba948f6 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
eliminate temporary vectors created during X86 lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9cb9626abf26dfcbbe8d02013c5b780c318cb321 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
remove std::vector's in RET lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2ad9f17fee5d6395cd8db81668853e6dbf94060b |
|
22-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Simplify lowering and selection of exception ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 62819f31440fe1b1415473a89b8683b5b690d5fa |
|
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support to provide exception and selector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f46847172afea92d73829147a6d9d18cde45ffd7 |
|
21-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
ELF / PIC requires GOT be in the EBX register during calls via PLT GOT pointer.
Add implicit uses of EBX to calls to ensure liveintervalanalysis does not treat
the GOT in EBX move as dead upon definition.
This should fix PR1207.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b25fe8267182662750dcb76a70a20f4b14a5568d |
|
01-Feb-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fixed uninitialized stuff inside LegalizeDAG. Fortunately, the only
affected part is codegen of "memove" inside x86 backend. This fixes
PR1144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33752 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bcc5f36765e8111c13873a0c0dc874c92385d808 |
|
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Finish off bug 680, allowing targets to custom lower frame and return
address nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 53108978849710fc5a8a5eb0b8ebefd8265b86c3 |
|
28-Jan-2007 |
Nick Lewycky <nicholas@mxc.ca> |
Fix compile error "jump to case label crosses initialization".
What compiler are people using that accepts this code?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b10308e440c80dd6ffb4b478f741ff7e5f30cb48 |
|
28-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
|
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 706535db86868d710ad10ddad4adc4bc8b838f10 |
|
22-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Linux GOT indirect reference is only necessary in PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7f70559bc47877bafc6dfa92b7df6b64650445fb |
|
12-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
* PIC codegen for X86/Linux has been implemented
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 73d6cf12adfd915897cce7e1ba9de00f962502d5 |
|
05-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- FCOPYSIGN custom lowering bug. Clear the sign bit of operand 0 first before
or'ing in the sign bit of operand 1.
- Tweaking: rather than left shift the sign bit, fp_extend operand 1 first
before taking its sign bit if its type is smaller than that of operand 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1722eeeaa41145af182bcd3e77bb0f32e27b4daa |
|
05-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 68c47cba3589b2fc079bab0836d1ae6fc3a6278d |
|
05-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
With SSE2, expand FCOPYSIGN to a series of SSE bitwise operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aff93871683c7888a7c7e112ac1a4904eb7a386b |
|
03-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Fix a comment that referred to the now defunct ubyte type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 317848f4a11f7fe55afdd6d90ded8444069b56fb |
|
03-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Really big cleanup.
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 47857812e29324a9d1560796a05b53d3a9217fd9 |
|
31-Dec-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR950:
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2b2bc688849234b9ee5e0c8704a2984f0e9cbba3 |
|
22-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactored JIT codegen for mingw32. Now we're using standart relocation
type for distinguish JIT & non-JIT instead of "dirty" hacks :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 21b76123e524398ccf55bd51be4b676e45490657 |
|
14-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
f64 <-> i64 bit_convert using movq in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d27a258d2d7691db3731135a448b7654d260cc07 |
|
11-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f3597a13ae66dbe682029f64fb1a7f2b65ff6536 |
|
05-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
If we have ScalarSSE, we can select bitconvert into single instructions.
This compiles bitcast.ll:test3/test4 into:
_test3:
movd %xmm0, %eax
ret
_test4:
movd %edi, %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 399610a2e601214520df42351b1287a142130058 |
|
05-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Fix PR1033 and CodeGen/X86/bitcast.ll, by expanding bitcast to a load/store pair.
This could be better, readme entry pending.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af21f4f6f9d6ef5085d927900a2aae364444d64e |
|
05-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Fix typo noticed by Lauro Ramos Venancio, thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 19f2ffce4598c4c70f32eed7c6740b43185200b1 |
|
05-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 98ae09ca5dba69cd9e5933ceea27d08b901907c6 |
|
04-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for 64-bit 'r' constraint. Patch by by Rafael ~Avila de EspÃÂndol!
This fixes PR1029 and Regression/CodeGen/X86/x86-64-asm.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0085a28d13f86b09ba0c83e8dce81de3ba15ca2d |
|
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Use a different wrapper node for RIP-relative GV, etc.
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c8306bde15c37592084602e28308fc5a2cd14ef8 |
|
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
In PIC mode, GV not requiring an extra load can be used as address immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d0ff02cf6ff3019dc97d49636a055e13d20a0774 |
|
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR1018 - Better support for X86-64 Linux in small code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3fa9dff2c97778f3c3c3c7a0e69f3543a03041d3 |
|
29-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Custom lower READCYCLECOUNTER for x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c0f64ffab93d11fb27a3b8a0707b77400918a20e |
|
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 12c49af81e370df835ca1b72cdcefcadafcede4b |
|
21-Nov-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactored *GVRequiresExtraLoad() to Subtarget method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31887 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a59868519b385e0b77eca6510b6a875056189a9a |
|
20-Nov-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
We should perform extra load for dllimported calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 |
|
14-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Matches MachineInstr changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5cd3e9f4b7caa5a79c6c05633b11144d0ae41771 |
|
11-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add implicit use / def operands to created MI's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8ca29326e19201075f6dc95781560ea9ad41ecec |
|
10-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Don't dag combine floating point select to max and min intrinsics. Those
take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.
This fixes PR996.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| df78611726ec38a582b3c13034c49c3d2a4eb280 |
|
10-Nov-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fixing PR990: http://llvm.org/PR990.
This should unbreak csretcc on Linux & mingw targets. Several tests from
llvm-test should be also restored (fftbench, bigfib).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6e56e2c602084bd7ab4af54e3c1a8700a9320f97 |
|
07-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixed a bug which causes x86 be to incorrectly match
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3ed469ccd7b028a030b550d84b7336d146f5d8fa |
|
02-Nov-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR786:
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 22aaf1d61c6a752d66f7ee10a7a5d99c7160e007 |
|
31-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
allow the address of a global to be used with the "i" constraint when in
-static mode. This implements PR882.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31326 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1a60aa7bc1e48150785402e0ae69276f78080d33 |
|
31-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
handle "st" as "st(0)"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ab4022f196059745c0ca0780b71a80fa67e896be |
|
31-Oct-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
1. Clean up code due to changes in SwitchTo*Section(2)
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 02b8511364a61b559369d8dc36e82a486f42fec3 |
|
30-Oct-2006 |
Reid Spencer <rspencer@reidspencer.com> |
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c35497fc2a8b984dbacede5b75b7be74c6756948 |
|
30-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
All targets expand BR_JT for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f686d9b71f0aa99578dac9a4dd50b57ece6945fa |
|
27-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixed a significant bug where unpcklpd is incorrectly used to extract element 1 from a v2f64 value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6bdb3f6c8f7400ea956d80cb44c3a5f5c872ef82 |
|
27-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR968: expand vector sdiv, udiv, srem, urem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9eca5e814da3490ae889a75c93c0191f510b9f1c |
|
25-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
During vector shuffle lowering, we sometimes commute a vector shuffle to try
to match MOVL (movss, movsd, etc.). Don't forget to commute it back and try
unpck* and shufp* if that doesn't pan out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9bbbb98a6092f403cdbb4903e1d9c5bdbcf4f8ad |
|
25-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove -disable-x86-shuffle-opti
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7fbe9723e32ff35c4ad765c88209ef9321475a1b |
|
20-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Implement branch analysis/xform hooks required by the branch folding pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d9b8e40ab3b51fa49f0c35cccb2bd795a786162b |
|
16-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Avoid getting into an infinite loop when -disable-x86-shuffle-opti is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8b2794aeff151be8cdbd44786c1d0f94f8f2e427 |
|
13-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cf12ec4897e82cdfd69948abea8d4b7d8edf788f |
|
12-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Some X86ISD::CMP were created with wrong ValueType's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 23425f5c7430818b060227a88fa4a93456040a0b |
|
09-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Don't convert to MOVLP if using shufps etc. may allow load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 466685d41a9ea4905b9486fea38e83802e46f196 |
|
09-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 786225adf09e606c795ef68a1f789c12f37869f2 |
|
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make use of getStore().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1907a7b37b867d015d49601ce65476ed7aaeceb0 |
|
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Lower some min/max idioms to minss/maxss when unsafe fp math is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e11130340898467ab6f46503455a6956995c259b |
|
04-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added option -disable-x86-shuffle-opti to disable X86 specific vector shuffle optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 83e6c9925e86cc6d89cf31ae536ec8eee20e72eb |
|
04-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Pattern match min/max nodes when we have sse. This implements
CodeGen/X86/scalar_sse_minmax.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c548428c5d7328592f4db6f6cd815af18b3152a3 |
|
04-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 13bf6c1350dc2ffc96aa48cc865a5b0d9ea1ffe4 |
|
03-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Fix PR933 and CodeGen/X86/2006-10-02-BoolRetCrash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f38f543e01e50a38599b7fd718ca4480613ac611 |
|
27-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
silence warnings in release build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e87e1154a12b91f3c7a5dec8b946c7c9829deb16 |
|
26-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Various random and minor code cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 70084fd53a3aed60b8c53b47d44d95cc3a268017 |
|
21-Sep-2006 |
Nick Lewycky <nicholas@mxc.ca> |
Fix compile error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f824868ed9d2cc756a797f6dbd67732f75e31cd6 |
|
21-Sep-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Adding codegeneration for StdCall & FastCall calling conventions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bcb9770efe409f3291ce21269904744e7bf3397b |
|
17-Sep-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Added some eye-candy for Subtarget type checking
Added X86 StdCall & FastCall calling conventions. Codegen will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 93c2b373409661798b7e191427a33791616a8ef6 |
|
17-Sep-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Small fixes for supporting dll* linkage types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b74ed07bfd3af42331b1964c24c39912610a08f4 |
|
14-Sep-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Adding dllimport, dllexport and external weak linkage types.
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bfd68a785810fcc4dfc82f583c4f2bea192d59f4 |
|
13-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Turn X < 0 -> TEST X,X js
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7a6366de86cca1a5a84f767675ddcb603e03f8ef |
|
13-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
The sense of this branch was inverted :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f95705163f45648fa58b1c481847b2c10bcb470f |
|
13-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Compile X > -1 -> text X,X; js dest
This implements CodeGen/X86/jump_sign.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c356a572e34131bf767f35e3fecefae36fab744a |
|
12-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects MachineConstantPoolEntry changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 734503be5965237e7eed978837ff280a9fadf403 |
|
11-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
operand of a conditional branch to allow load folding into CMP / TEST
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 25ab690a43cbbb591b76d49e3595b019c32f4b3f |
|
08-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8cf723d8ebaddbf02ab176f41e6b51981c4d7f85 |
|
08-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Identify a vector_shuffle that can be turned into an undef, e.g.
shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
optimal code by failing to identify MOVL (move to lowest element of a
vector).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ffc0b2663e4beaea1b584db607efd60660f5a74e |
|
07-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5ea7a68e15c8601b2806f84a0fb422918539f66a |
|
17-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Revert this patch, the front-end has been fixed to make it unneccesary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29752 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b5bc04d38aba1f86e9bc38b876eb7e3ea3aa0369 |
|
17-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
'g' is handled by the front-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ad1ed016ce722a6a9b27473dbf8a6e5d75ce46b1 |
|
17-Aug-2006 |
Andrew Lenharth <andrewl@lenharth.org> |
Fix handling of 'g'. Closes 883
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d337295fb0f724d9da1e029260f68ef09b25e1fe |
|
17-Aug-2006 |
Andrew Lenharth <andrewl@lenharth.org> |
Add the 'c' constraint as needed by the linux kernel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c63e56ee5f00da39563c174262872ec5e96a4bb5 |
|
17-Aug-2006 |
Andrew Lenharth <andrewl@lenharth.org> |
Add support for S and D constraints, as needed to compile the linux kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e219945348207453a2d5e21021ba3211f8f94e25 |
|
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Eliminate use of getNode that takes a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 64a752f7c7cf160f2887d0a16d5922359832c9c2 |
|
11-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 311ace039123f901cfe063cd1e0c4f2b6341078c |
|
11-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Convert more calls of getNode() that takes a vector to pass in the start of an array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bd564bfc63163e31f320c3da9749db70992dc35e |
|
08-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f76d180c9595d34641f4b5d2fbba2f2c175197d8 |
|
01-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll.
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 35d86fef1f1fc5845366c7c36803a6a3334d8a2e |
|
26-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 625518002de57fb9e5e95856b7554372ac6f0210 |
|
21-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
This opt is now handled in DAG combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1e1a88e8cc6c51d0f00ecdbdbcf40bd23e124d27 |
|
21-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
A splat of a vector constant of all zero or all one is the vector constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6d3465793f45f4d40e24cabf1f5867cc6c0db90a |
|
12-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Add information preventing several register class constraints from working.
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f4dff84c8614fc2106d821e4687c933d8d4b9420 |
|
11-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the inline asm 'A' constraint. This implements PR825 and
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1e60c098cc045f9b183b752625fe61bda97b8f0a |
|
10-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixed stack objects do not specify alignments, but their offsets are known.
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5c5f4ca6f153441e4a674c9d0ffa8f8241d2951d |
|
10-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Mark internal function static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 206ee9d86cd4e78176fad6bfa2b016023edf5df7 |
|
07-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 60c07e1aeadd332c5e000449df2a487831209fa8 |
|
06-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reorg. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| da08d2c39af6aceaa0230f699c4b53de0e97c2b9 |
|
24-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 015188ffbc148cb90184814fba51c4939c05a7e2 |
|
15-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Type of vector extract / insert index operand should be iPTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28796 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b69d113201a60d0ada9f9e7e1a855acb7a6dfc96 |
|
14-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add argument registers to the end of call operand list (partial fix).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b12223e284ff73dfeae5a41da74aa51c2d36cb2f |
|
09-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Minor compilation speed improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e8bd0a332ab43c30a7745381075a9749070b6a50 |
|
07-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added X86FunctionInfo subclass of MachineFunction to record whether the
function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2675534b7f3a7652e2a0040f415c60557a84e3a8 |
|
01-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 04b25625023ccfea24ab1fadfaf077f8505eb207 |
|
01-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8f692e2457d24973e1a257083a8590d2a76d877f |
|
31-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6848be1a27e08a89dcd4dd69f746471a608012cd |
|
27-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3fddf241d835f6b0c8866f010194b6b97b849427 |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Vector argument must be passed in memory location aligned on 16-byte boundary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1d6a9b3b6c30c0c85ebdd1aa6d1c7484d8bca841 |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Mac OS X ABI document lied. The first four XMM registers are used to pass
vector arguments, not three.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 052fb5110fd9b461cbb140364068268df8465bf4 |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Minor update to make the code more clear
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f9d62dc6e5e17ae237689725047b08ecd70b57f6 |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Update more comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f9ff7c54be6a946f0845dd8a8f648e86e68d29bb |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6f707999a1d066fd00fb7bb9ab5eaf7182d30762 |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
No need to handle illegal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cc1fc220a0f634943fb23ce471e965ea835cd98f |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 25e71d10a06ce5947a61e7c3ffa6f58642ea3b4c |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Some clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a9bb445db09db8762bf22d74b8d8b9cddc145ae7 |
|
26-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b5783d0b17abffe6665a95e3168642d5f465cef |
|
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Build breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 32fe1035a708d16d67e632f21d8ec2d1b437a225 |
|
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Switch X86 over to a call-selection model where the lowering code creates
the copyto/fromregs instead of making the X86ISD::CALL selection code create
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28463 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c6d0567324950c536029e7ef09581d9837ae6be9 |
|
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix file header comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4db3af35117521643d0c1323c99f1fd00e1acf5d |
|
23-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Better way to check for vararg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 25caf63cd2befc2c4d18ce0316af853988b48224 |
|
23-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove PreprocessCCCArguments and PreprocessFastCCArguments now that
FORMAL_ARGUMENTS nodes include a token operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2d2970905cf745771d9c4f23293ca3de6659ab4f |
|
23-May-2006 |
Chris Lattner <sabre@nondot.org> |
Implement an annoying part of the Darwin/X86 abi: the callee of a struct
return argument pops the hidden struct pointer if present, not the caller.
For example, in this testcase:
struct X { int D, E, F, G; };
struct X bar() {
struct X a;
a.D = 0;
a.E = 1;
a.F = 2;
a.G = 3;
return a;
}
void foo(struct X *P) {
*P = bar();
}
We used to emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
addl $28, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
ret
This is correct on Linux/X86 but not Darwin/X86. With this patch, we now
emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
*** addl $24, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
*** ret $4
For the record, GCC emits (which is functionally equivalent to our new code):
_bar:
movl 4(%esp), %eax
movl $3, 12(%eax)
movl $2, 8(%eax)
movl $1, 4(%eax)
movl $0, (%eax)
ret $4
_foo:
pushl %esi
subl $40, %esp
movl 48(%esp), %esi
leal 16(%esp), %eax
movl %eax, (%esp)
call _bar
subl $4, %esp
movl 16(%esp), %eax
movl %eax, (%esi)
movl 20(%esp), %eax
movl %eax, 4(%esi)
movl 24(%esp), %eax
movl %eax, 8(%esi)
movl 28(%esp), %eax
movl %eax, 12(%esi)
addl $40, %esp
popl %esi
ret
This fixes SingleSource/Benchmarks/CoyoteBench/fftbench with LLC and the
JIT, and fixes the X86-backend portion of PR729. The CBE still needs to
be updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cdbaeb52ae36bb4a94cc2101e0babbaf5c148eb1 |
|
19-May-2006 |
Chris Lattner <sabre@nondot.org> |
CSRet allows varargs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4ac8974d0220a382c8d0c4a4ae8e69c4e5864d56 |
|
17-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Should pass by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aa9406b0c44379de438f3626d5b391df7130e73c |
|
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the custom lowering hook right, returning values for all of the
arguments at once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e7746c9084bbd04a37a38571bfc289b40b71cc63 |
|
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a bug I introduced yesterday, which broke functions with *no* arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28326 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 069287d460321af43b7c88b816da5c778e5f46d1 |
|
16-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8c0c10c2b9fef21dcbabac81fffa32f4407a0b7f |
|
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 03ea4c8326164f61e8b0ac48289c9e00dc56a3b3 |
|
12-May-2006 |
Chris Lattner <sabre@nondot.org> |
Dead variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 80a7ecc9233ed65908437472657180044b824365 |
|
06-May-2006 |
Chris Lattner <sabre@nondot.org> |
Teach the X86 backend about non-i32 inline asm register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bd04aa57964a37d8e7bfd51a168e27ca4dd666af |
|
05-May-2006 |
Chris Lattner <sabre@nondot.org> |
Teach the code generator to use cvtss2sd as extload f32 -> f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a69571c7991813c93cba64e88eced6899ce93d81 |
|
03-May-2006 |
Owen Anderson <resistor@mac.com> |
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
This fixes PR 759.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 347d5f789a35670dd262a39444dd50b53f05e70c |
|
28-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Initial caller side support (for CCC only, not FastCC) of 128-bit vector
passing by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 43f3bd310b2e41335571ee10953ffaeeef16d2e3 |
|
28-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Implement four-wide shuffle with 2 shufps if no more than two elements come
from each vector. e.g.
shuffle(G1, G2, 7, 1, 5, 2)
==>
movaps _G2, %xmm0
shufps $151, _G1, %xmm0
shufps $216, %xmm0, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 020c41f21e8b6b01bc40db69e660c3c6e29b0978 |
|
28-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
TargetLowering::LowerArguments should return a VBIT_CONVERT of
FORMAL_ARGUMENTS SDOperand in the return result vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fea89c14ecf5e61c627942940fa5a9cde6b28a51 |
|
27-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make x86 isel lowering produce tailcall nodes. They are match to normal calls
for now.
Patch contributed by Alexander Friedman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2fdd95eee79b66c9ae3cbe43c0db48eba48e116d |
|
27-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for passing 128-bit vector arguments via XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5fb03ce9054e6db44673eec141494ad071b13233 |
|
27-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Oops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 85e3800e427fd5367df7a46ce4ad37ad901f894c |
|
27-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Bug fix: not updating NumIntRegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eda65fa20ba99e520d7f171d5b536458eea6e9c7 |
|
27-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Clean up formal argument lowering code. Prepare for vector pass by value work.
- Fixed vararg support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9191dbba8e5740bbd32a1baf835726acf327c1e9 |
|
26-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix fastcc failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1bc7804e4c8747fd99b119e8f88686c9610c5d4e |
|
26-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Switching over FORMAL_ARGUMENTS mechanism to lower call arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0db9fe6775853d62632ad299dd734b6ba6c6b336 |
|
25-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Separate LowerOperation() into multiple functions, one per opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37d1d9bc6661c03d980ad9c73bc02349b82ac248 |
|
25-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Special case handling two wide build_vector(0, x).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c78d3b43f5156f2a2718886337bc27aac83e8e93 |
|
24-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
A little bit more build_vector enhancement for v8i16 cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9293451e3f42aba03676dbbb029032e286cac4dd |
|
23-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
MOVL shuffle (i.e. movd or movss / movsd from memory) of undef, V2 == V2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 37efe6764568a3829fee26aba532283131d1a104 |
|
22-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1900c012f5f15063a9349f6646d7dd1654df38f9 |
|
22-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Don't do all the lowering stuff for 2-wide build_vector's. Also, minor optimization for shuffle of undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a083af14c8130e7cb1f4812b6d6fdcf2cc21882f |
|
22-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix a performance regression. Use {p}shuf* when there are only two distinct elements in a build_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ba05f728b57264836aa0837de1744355f3237572 |
|
22-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Revamp build_vector lowering to take advantage of movss and movd instructions.
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 017dcc6e556f3f89dd3e3881696084af694718ac |
|
21-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 39623daef67090025be5cd8af7d172fd1c9e6418 |
|
20-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added support to turn "vector clear elements", e.g. pand V, <-1, -1, 0, -1>
to a vector shuffle.
- VECTOR_SHUFFLE lowering change in preparation for more efficient codegen
of vector shuffle with zero (or any splat) vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 72cd9a9439ceeb662a6a6c3665120b4aadf1b51b |
|
20-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle v2i64 BUILD_VECTOR custom lowering correctly. v2i64 is a legal type,
but i64 is not. If possible, change a i64 op to a f64 (e.g. load, constant)
and then cast it back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 94fe5eb14a6e9854d5adb9029014e944103971f9 |
|
20-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
isSplatMask() bug: first element can be an undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 80d428c3706a38347663f2185cd99eae97d0c8a1 |
|
20-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added support to do aribitrary 4 wide shuffle with no more than three
instructions.
- Fixed a commute vector_shuff bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 533a0aa9ba8653e2a0219be442eebae02f371c88 |
|
19-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Commute vector_shuffle to match more movlhps, movlp{s|d} cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| cdfc3c82a72eeaa604a50426ffc51c21587e0406 |
|
18-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use movss to insert_vector_elt(v, s, 0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5edb8d270cd7566514187ec53f8ab3f6bf306965 |
|
18-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use two pinsrw to insert an element into v4i32 / v4f32 vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c575ca22eaf8a656f3fa2c3f0f75264c4c4fcd21 |
|
17-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Implement v8i16, v16i8 splat using unpckl + pshufd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b2be4032c5f1431f8867baae7d0721d49c32995c |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
implement returns of a vector, testcase here: CodeGen/X86/vec_return.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5001ea1078e300fab8d26d183249522b4c4edd98 |
|
17-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
FP SETOLT, SETOLT, SETUGE, SETUGT conditions were implemented incorrectly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 57ebe9fbf067422a267b5d46b0b0282e437c15c3 |
|
15-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Silly bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 39fc1459953040a480e58142fb6adbfcc4082fe8 |
|
15-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Do not use movs{h|l}dup for a shuffle with a single non-undef node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d953947d26da373b3b4e5ff66b60883fb78c0dd5 |
|
14-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Last few SSE3 intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f99898453dc287627f8a0373e4ebbdb523683611 |
|
13-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 SSE2 supports v8i16 multiplication
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c3ae37213c320b64048091820628c6af1991aa3 |
|
12-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
All "integer" logical ops (pand, por, pxor) are now promoted to v2i64.
Clean up and fix various logical ops issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 91b740da12b1152e740fadc6789a3d2a596dbabe |
|
12-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Promote v4i32, v8i16, v16i8 load to v2i64 load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d6d1cbd692dd519263e30d97d6c4c9e453b5c5d5 |
|
11-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added support for _mm_move_ss and _mm_move_sd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f7c378e9ea3c6c9ab267915057634aa2e318a732 |
|
10-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Conditional move of vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c5cdff234149596361d6175d57c3e76e864c9455 |
|
07-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5ced1d812e1de885b568ddfa6da008895d3f7ce7 |
|
07-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
- movlp{s|d} and movhp{s|d} support.
- Normalize shuffle nodes so result vector lower half elements come from the
first vector, the rest come from the second vector. (Except for the
exceptions :-).
- Other minor fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6be2c58c8c4d2b8dede9e3d6920a18f04164388b |
|
06-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for comi / ucomi intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1d5a8cca004c29d99526b3c327d948f8ab197c90 |
|
05-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 865f0606f7191281456e13fddc49b21d18a4a890 |
|
05-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Bogus assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 278158b4877c64b741fd37b2eb9ca1bdbc2eb3d7 |
|
05-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c21a0537299e9fc18d8592b2fda5950f3c4731e8 |
|
05-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 20e3ed102ba0794b09a894b41254738a59eb30f4 |
|
04-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use movlpd to: store lower f64 extracted from v2f64.
Use movhpd to: store upper f64 extracted from v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 11e15b38e965731e5bfff6c73d8d269196e5048c |
|
03-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
- Some bug fixes and naming inconsistency fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 653159f4aac61a7ad796e406a4899d27ffe5a789 |
|
31-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b067a1e7e68c4446d3512c25d3a5ac55c6dd76f8 |
|
31-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add support to use pextrw and pinsrw to extract and insert a word element
from a 128-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 33e85ca7b614270319842524b0c57073ae208da6 |
|
31-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Expand all INSERT_VECTOR_ELT (obviously bad) for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| fb47a9b1c86201529f25a6b8b0c2145eb7a24cca |
|
31-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ef698ca30d96baf4ec843740396187b722a63e69 |
|
31-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Ok for vector_shuffle mask to contain undef elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27271 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7d9061e3009af718544fde64ea88343fa9cd2ada |
|
30-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make sure all possible shuffles are matched.
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 506d3dfa90cfee6ab4736a6a2c892e9059a7864d |
|
30-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added some SSE2 128-bit packed integer ops.
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 691c923e471c3c2bef59bcff5fa77664857432a6 |
|
29-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Need to special case splat after all. Make the second operand of splat
vector_shuffle undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 475aecf467aa63623e5840ac896faef496eaca8c |
|
29-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- More shuffle related bug fixes.
- Whenever possible use ops of the right packed types for vector shuffles /
splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4f5633883b2e9ba187885e09e81564a53e549d60 |
|
29-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Only use pshufd for v4i32 vector shuffles.
- Other shuffle related fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 36b27f3cdef57c5b483428f98ddaf6b9aa8ef3f6 |
|
29-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixing buggy code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2d2a6131da021ec307f253e3915b2a80d07ae093 |
|
28-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Added missing paren on behalf of Ramana Radhakrishnan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ed4ca7f6c3d299aa8060507a88f1a67a8c10ca40 |
|
28-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Missed X86::isUNPCKHMask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2064a2b47eb10ae9a63a8b9db19a8990c9cea7e4 |
|
28-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
* Bug fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4fcb922c70b67bbd74ff77a9b831bd3699839b6d |
|
28-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Clean up / consoladate various shuffle masks.
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0038e598037f76c2dce8b55ebb5e9147fd786330 |
|
28-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Model unpack lower and interleave as vector_shuffle so we can lower the
intrinsics as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a0b3afbe14216884b66c867af23eb81f21399365 |
|
27-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use pcmpeq to generate vector of all ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| f15485a8d0dff5f720b7ad27346129ac5c3ec503 |
|
27-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
SelectionDAGISel can now natively handle Switch instructions, in the same
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ffea91e522a8d969a3c0810ec231b1179137d575 |
|
26-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c60bd97b94261366800c2eb57e95ddd44092e6f8 |
|
25-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Build arbitrary vector with more than 2 distinct scalar elements with a
series of unpack and interleave ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7b1d34bc6c27b7ba26c270ca3c434a640e7f7c7f |
|
25-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added 128-bit packed integer subtraction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bc4832bc648f9cfb99a43e01852e0f2c7632f16c |
|
25-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for scalar to vector with zero extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 386031a06f06626d9d94927af754da6d44dcb5fb |
|
24-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle BUILD_VECTOR with all zero elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9d5da1d96cc90cc04a57c1cb1aa6f47e6bb99ef7 |
|
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Gabor points out that we can't spell. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5217a5b58cf0c34982671ce823634daf8e2460bb |
|
24-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
All v2f64 shuffle cases can be handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2c0dbd01d240f80e5517773d8e2f77924c69a6ec |
|
24-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 14aed5e66b606ab3ba39e1effd2a0a17790d6f19 |
|
24-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle more shuffle cases with SHUFP* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8fc23cd0e90966f534761f0252d7fbae57c40f91 |
|
23-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a971f6f967db2edc027bb5c1e59e5c9c3ab0b13b |
|
23-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add 128-bit integer vector load and add (for testing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ca6e8eafd2dfb13b89875405c54613b9cea1ca2e |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
64-bit vector shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a88973f8262d93f4902e220e34cb44444992b858 |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Some clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26957 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1bffadd7fb1edc89c4d171075dd1de954955ea70 |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Supposely movlhps is faster / better than unpcklpd.
- Don't forget pshufd is only available with sse2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0188ecba85c7139f237baa4ce5612fdfc83e1b84 |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 63d3300da1ec6403fbf11f62d6404c7f87bffdba |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6df1154644a0044636022a2ec9810bbacd5f8d30 |
|
22-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
fix a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b9df0ca67b9a59c75685a72ee50b1b471aa9d1bf |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Some splat and shuffle support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 48090aa8145640c023563751a8a1e1bcc09125e5 |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Use movaps to store 128-bit vector integers.
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9b3bd467d02e73a02afed6d50aaaa149a6a69701 |
|
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 39afef31502186bcb976ccb345d98dd50e852c4e |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add a build_vector node
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a064d28843b425905ed981e693b7730a183ee31b |
|
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
rename these nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| df57fa0c7d44a90ed8c0271a4a78fd5de8eea995 |
|
17-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 89fad2c3b27f62c53a807839c752626f2b11142f |
|
17-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Disable x86 fastcc from passing args in registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1c636e9d9894a2942d2b0980b8cf48bdec3afeed |
|
17-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Parameterize the number of integer arguments to pass in registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 81e8097377529dc3b666f33bb525c49cfbac3f51 |
|
17-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2221de9cc18c0192619032454febe8e28b64f6ff |
|
16-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Bug fix: condition inverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 714554d70717c73e0542ca93df36fa78765f87af |
|
16-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a way for TargetLowering to specify what values can be used as the
scale component of the target addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 30b37b5f29991874648d839d018aa2921b39355f |
|
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add LSR hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ff909926e2f1e65c12ec5262f36e44f9ec03adc7 |
|
08-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest.
and variable value.
Similarly for memcpy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 3c992d291bc67d9ce9d742d586d24ade9a577c99 |
|
07-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Enable Dwarf debugging info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9601a86a644fa036168ff173d3539550b2e9206e |
|
05-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
implement copysign as a native op if they have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 62bec2ca4c227a61fd9a38b23da81035e83f5733 |
|
04-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
rep/stos and rep/mov if the count is not a constant. We could do
rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.
Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8df346b4e871864c8006eab69badba2aaeb44bcd |
|
04-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 41edaa0529997e41a2bd64efd5f3e8027c67d99f |
|
03-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
remove the read/write port/io intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d30bf01e9064a668eaa896a3e9c79d8f0290b6a7 |
|
01-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Vector op lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| bbbb2fbbde673d2e23b83722510c03bc8c67c70a |
|
25-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a common about the need for X86ISD::Wrapper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 020d2e8e7aa36692af13c1215fdd6248a6d9e950 |
|
23-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a0ea0539e359f6d82218e5aa4cdf3b50b17d6fbd |
|
23-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
PIC related bug fixes.
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c1aa866578f7a358407a22fe55b454f52a24325 |
|
22-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added option -relocation-model to set relocation model. Valid values include static, pic,
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 470a6adc784ad2e4194272b24f5ec50ee32aeb49 |
|
22-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1efa40f6a4b561cf8f80fe018684236010645cd0 |
|
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
split register class handling from explicit physreg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4217ca8dc175f7268a4335c8406dedd901e8e631 |
|
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Updates to match change of getRegForInlineAsmConstraint prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 45af8fd8c2394fdc92ce3b528cc03dd1eb8c5b45 |
|
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
advantage of fisttpll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 7ccced634ae0ecdc1c4f599fd3abf188c367e231 |
|
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 / Darwin PIC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c2fe97e726407566871341337c3a11fa08491ab6 |
|
17-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
unbreak the build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5298bcc722ede52db376542438c48f01f31f0e47 |
|
17-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak x86 be
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 551bf3f80058a026b6a128dffd5530019e1df1b9 |
|
17-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4c5dcf54ff927d377655d673ac5d560b39008e37 |
|
17-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Kill the x86 pattern isel. boom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 368e18d56a87308045d341e85584597bfe7426e9 |
|
16-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 18a8452f3d2cc0bbfea427b10e2c7dccc86f2188 |
|
16-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
A bit more memset / memcpy optimization.
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a03a5dc7ce876dac4b3b91bae14216de4233bacd |
|
14-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87ed716d21bec7ea29674b4b010aa051ad2b7193 |
|
14-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and
maxStoresPerMemMove. Although the last one is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 94dd29216cfcc2719be1cb8b7baa8cc19434e3ce |
|
13-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
CALLSEQ_START nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2338c5cb0e7c102ae2269d9a6b6e3d620ed206da |
|
07-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete.
Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e3de85b447b0a94c82f147159a0c903ea47e0069 |
|
04-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
flag so it can be flagged to a FST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d25e9e8294b913f235253cf9e22dd5ee28cbe5d8 |
|
02-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix a erroneous comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 750ac1bdfa6f09bddfd9efce1d6360dde8fa74c0 |
|
01-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix some of the stuff in the PPC README file, and clean up legalization
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 760df2988190552252ca7860b31aab49d058453a |
|
01-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Return's chain should be matching either the chain produced by the
value or the chain going into the load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0d084c9e4aabb33df7f566de91a16df77c657c9a |
|
01-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
When folding a load into a return of SSE value, check the chain to
ensure the memory location has not been clobbered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0e8671bf4acbd27f759c14e9cc0271b544979283 |
|
01-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Be smarter about whether to store the SSE return value in memory. If
it is already available in memory, do a fld directly from there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 223547ab3101f32252cb704a67bd757e00fdbd16 |
|
31-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
- Use XORP* to implement fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 259e97cc725011a3c138563d421a4654b082a64c |
|
31-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
* Fix 80-column violations
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ef6ffb17c71232af5962f9926b31508eb942cddc |
|
31-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added custom lowering of fabs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6dfa999c01103c7a8e08ed0fc1d5f8abd0fb4d40 |
|
31-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 02568ff48daf3081ab1d18f4158cd907abafb0a9 |
|
30-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
i64 -> f32, f32 -> i64 and some clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6dab05363f94b279a3877fd79d68649b865e10d9 |
|
30-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
conversions. SSE does not have instructions to handle these tasks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| c6fd6cd65c88ef1f11da43c11be0152cb69013a7 |
|
30-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 87c890a9c2a8f9818772f3b9e359d301b246e3a4 |
|
30-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
adjust prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 44d9b9bb86cad2185b9229d67f84e57994f57a04 |
|
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
instead of lying and saying we have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a54aa94197d5af9a72c0de422a58e938da80b2a4 |
|
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Targets all now request ConstantFP to be legalized into TargetConstantFP.
'fpimm' in .td files is now TargetConstantFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6b2469c1ad9bdb0183658df9130af1edbe84912c |
|
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
silence a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8e44f0756ffdcba4aeddee00dd643b3839acd434 |
|
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Bye bye Pattern ISel, hello DAG ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| ee625573b5b39b91441fc6ea23f3ba415abdc71f |
|
27-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 559806f575297866609c7bef0e5c1084dcdda9a5 |
|
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 CPU detection and proper subtarget support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9bba894596bf658761c4f4feaa2532c5c3b6cfa0 |
|
26-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
When trying to fold X86::SETCC into a Select, make a copy if it has more than
one use. This allows more CMOV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| acc398c195a697795bff3245943d104eb19192b9 |
|
25-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
First part of bug 680:
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0b2afbd58ad189f0db0bfd88ef2ed19bd9330e2a |
|
25-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 prefer scheduling for reduced register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0d718e9afca29b047ae1c77f8c6afc1b70759e0b |
|
25-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 91cacc810bed09917222182542e0427a4f571d38 |
|
24-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
use ESP directly, not a copy of ESP into some other register for fastcc calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| af63bb03c51231d81f6890dcaec7f71cb60b51de |
|
24-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1f16ff6f0ad3e4cc0cd95e5244bd9feb50fef369 |
|
20-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
LowerReturn now doesn't have to handle f32 returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dc8d2ab3e9ab9e26e6bf5a4e9943033870b379f7 |
|
19-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Avoid generating a redundant setcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b7b5706340785a97d4c59559adba1a8784d8102d |
|
19-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
A obvious typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 99fa0a102ae59e2fa489982157dd508cd32caad7 |
|
18-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
SRA shift amount must be in i8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 68e5d084f1a51e71b38aceb8ccc12734adcce9ef |
|
18-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
If a call return type is i1, insert a truncate from X86::AL to i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 357c58efdeb4eef9bf220795ba89a873709486c9 |
|
17-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix lowering of calls which return f32 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 6892f28e99f0d6e85f7be1d802231471cfd82839 |
|
17-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom
expand it), so ask legalizer to expand i32 UINT_TO_FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25386 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 2059f884aaf62b85db25dd3e7a0cf8375a448dd4 |
|
17-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a FIXME comment about why FST is currently flagged to fpGETRESULT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 42ef0bc6fb41a5002510ea9c7e684f415e86d650 |
|
17-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
read a flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 0cc3945efe8702c1244a31d2d355b4b64e25a8b7 |
|
16-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix FP_TO_INT**_IN_MEM lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e112552b5a5c1086aeabe590ab651cbf1178393f |
|
15-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d88fc03602947b5baa35c8b09fe8bcfa2b4a03c1 |
|
14-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
bswap implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e90da97f3ef0dab5c97976ce227a4407918bf5a7 |
|
13-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be
flipped around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 9edba7605e48aaf2b99cf0c8204db3fa1bd4d2f8 |
|
13-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Enable X86 support for savestack/restorestack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| b99329e8a0ec3b5a0004dd649e3546939f5c31e7 |
|
13-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
expand unsupported stacksave/stackrestore nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 80ebe38118de06b4f5b3ecb102742eb2871c189e |
|
13-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
More typo's. I need new eye glasses...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 189d01e8cc32767afa84e5cb3b25e0a51becf600 |
|
13-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Oops. Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 1bcee3602e8017ebe255b30800a43d62f16edffd |
|
13-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix a SETCC / BRCOND folding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| a3195e86439896ecba9b3f2afce40919b20a987a |
|
12-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix sint_to_fp (fild*) support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 5ee4ccce5b88d639c3fa8929496daac45b25048e |
|
12-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
linked together).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25247 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 002fe9baf2bdc50532c6238b92ac46191fd01c38 |
|
12-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Materialize GlobalAddress and ExternalSym with MOV32ri rather than
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| eb422a723425ce338c083bcfac96114a018aec13 |
|
12-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added ROTL and ROTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 67f92a76497d1f50e0dd6279c81b45689bd463f5 |
|
11-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for MEMCPY and MEMSET.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 35ef913ec21de0f4f1b39c811b4335438717a9b8 |
|
11-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Add bswap, rotl, and rotr nodes
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 8700e14ba10abeef4a8a2cf396e5e98ff81b9de3 |
|
11-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Add special entry code main() (to set x87 to 64-bit precision).
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 4a46080fe0133c71b511805c63abfb158dcd56a5 |
|
11-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
SSE cmov support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| aaca22ca918585173f55e926bc050fb0696fc28b |
|
10-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
FP_TO_INT*_IN_MEM and x87 FP Select support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 910cd3cfa2286baa683180a0d888f6d3c77f9d54 |
|
09-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
More typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 82a24b98135027b50147cedd56e80720f06c61d3 |
|
09-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e3413160ca2fb42854b2a23be6b2114c1da2778c |
|
09-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| d9558e0ba6ddcf2798cfb88cc56e5f1c8135eb0d |
|
06-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Fast call support.
* FP cmp, setcc, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| e0bce71c42a021d897b51425dab16841a0ebc5bd |
|
05-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Had expand logic backward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| abf6d1784b2d4bbcb7d20ab64881f77d755059f6 |
|
05-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Added initial support for DEBUG_LABEL allowing debug specific labels to be
inserted in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| d90eb7fb2435e2abedb4694edc44fa45642edbe9 |
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05-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
DAG based isel call support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| f31d193cce7c2df2708cacbaae123222116320a0 |
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27-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| 38bcbaf23e8836c8f64e7fd66ebebc44a2b921a1 |
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23-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
More X86 floating point patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| 21f66859e4338c40d29cf54123bab7bfa0a182d0 |
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23-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
make sure bit_convert's are expanded
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| 3a03ebb37747c2b3fd9b4f8b44f1124f53727894 |
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22-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Fix a GlobalAddress lowering bug.
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| e81aecbae69d4b3bd24523ec87673632d3b0beec |
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21-Dec-2005 |
Jim Laskey <jlaskey@mac.com> |
Disengage DEBUG_LOC from non-PPC targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| d5781fca4f8f98863560338d4f8d017389428119 |
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21-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Added support for X86 RET with an additional operand to specify number of
bytes to pop off stack.
* Added support for X86 SETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| b077b842b64af39c8e2e9aaad327b3be446790dd |
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21-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Added lowering hook for external weak global address. It inserts a load
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| 7226158d7e3986e55b58214a749aa4eabb3fb6d5 |
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20-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added a hook to print out names of target specific DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| 898101c15fa11a896deb4e2fcb73b4727e1dcc1f |
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20-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
X86 conditional branch support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| 433dbdaa636d1c6e06acb2de22bcc83721cacac8 |
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17-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Remove a few lines of dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| 7df96d66729d1f33934de7b52553e5f071686041 |
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17-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
X86 lowers SELECT to a cmp / test followed by a conditional move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| cb17bac3a39546a186e0b0eb53b5916dff54c564 |
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15-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Promote all 1 bit entities to 8 bit.
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| e80242a948c77651c7da128a1cebd346523bbcef |
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07-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
X86 doesn't support sextinreg for 8-bit things either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| f73bae1b73211c77238f64029ee2bec7ce90bba2 |
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29-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
No targets support line number info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| 81f803df801776aa9354833fd94fc496ea054185 |
|
20-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Lower READCYCLECOUNTER correctly, preserving the chain result
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| 81363c387124a8788b2f8b469d357638a690708c |
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20-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
use chain operands to ensure the copies don't wander from the rdtsc instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
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| b873ff322c28ce097762355921100b677c71238d |
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20-Nov-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
The second patch of X86 support for read cycle counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|
| dbdbf0ce2eef7b6585397121f56d3845e04866d1 |
|
15-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch
contributed by Evan Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.cpp
|