| 512119770e9c32eb0b9e6196ce51917fb2e30d9f |
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05-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Schedule copy from phys register at beginning of block
It allows regalloc pass to remove them by trivially assigning associated reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/floor.ll
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| 96fe0be43b3163ee9a9fd2e9f1a6ed2753bd7596 |
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03-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: use capital letter for PV channel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/floor.ll
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| 76fc2d077f955174c14e658bf179620ef49dd792 |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Use bottom up scheduling algorithm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/floor.ll
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| 92f24d403f16ab2ee4598e32c926acc9c2344140 |
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02-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Prettier asmPrint of Alu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/floor.ll
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| f98f2ce29e6e2996fa58f38979143eceaa818335 |
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11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/floor.ll
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