| e0bbf7288c00c377a97a9d4bf5fb0bf20c44cd1c |
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07-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add floating-point load-and-test instructions
These instructions can also be used as comparisons with zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| ccdf5cc7bc443726425dd1ad498d44768332d49c |
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05-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add definitions for BRCT and BRCTG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| 0e4044c233d10596578df35bae2483fbe4e8a507 |
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05-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add LOAD AND TEST instructions
Just the definitions and MC support. The next patch uses them for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| eddfaad1ef9a208a8a9ee23c26fac4d980caa99a |
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19-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Start adding z196 and zEC12 support
This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.
insn-bad.s tests that some form of error is reported when using these
instructions on z10. More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| c25d21e05b76e9c542e3bea6a9a12a77772beb14 |
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16-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add MC support for R[NOX]SBG
CodeGen support will come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| 3ee0673e4f5f0324ecd0a65507009b0748ed072c |
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11-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Allow 8-bit operands to RISBG
RISBG has three 8-bit operands (I3, I4 and I5). I'd originally
restricted all three to 6 bits, since that's the only range we intended
to use at the time. However, the top bit of I4 acts as a "zero" flag for
RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co.
This patch therefore allows them to have the full 8-bit range.
I've left the fifth operand as a 6-bit value for now since the
upper 2 bits have no defined meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| 9188443a2d35352c4e8a2cffd1b4d31d47843b26 |
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02-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add the MVC instruction
This is the first use of D(L,B) addressing, which required a fair bit
of surgery. For that reason, the patch just adds the instruction
definition and the associated assembler and disassembler support.
A later patch will actually make use of it for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| 2d664abbfca8b9fa3d99e8a2f74bd52faf007f12 |
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29-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Immediate compare-and-branch support
This patch adds support for the CIJ and CGIJ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| d50bcb2162a529534da42748ab4a418bfc9aaf06 |
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28-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Register compare-and-branch support
This patch adds support for the CRJ and CGRJ instructions. Support for
the immediate forms will be a separate patch.
The architecture has a large number of comparison instructions. I think
it's generally better to concentrate on using the "best" comparison
instruction first and foremost, then only use something like CRJ if
CR really was the natual choice of comparison instruction. The patch
therefore opportunistically converts separate CR and BRC instructions
into a single CRJ while emitting instructions in ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| ddbf053a4cad58393a389f264c51923111eba3db |
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15-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Make use of SUBTRACT HALFWORD
Thanks to Ulrich Weigand for noticing that this instruction was missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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| 8580e79fba028e6d6085033617c0c566034cad54 |
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15-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Consolidate assembler tests into 4 big tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/SystemZ/insn-good.s
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