| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 8b23755ce978247a92c00e390de2e459c0a9d5ad |
|
22-Sep-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove some dead metaops code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 5d7f3ae15c62d46e8857c159978c1c75e07cc59b |
|
24-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: remove unneeded #includes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 35fd72756a05463568d94862f4fcd234903e1204 |
|
08-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track move of bo_exec from drivers to bufmgr.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| d76545de5730f52328a81b8371d3b08cd7511e05 |
|
06-Mar-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Fix double free issue to pass glean/maskedClear test
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 20b8bff49cba3e8246e29004c5ff38f231d589ff |
|
26-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
i965: Setup framebuffer texture in meta_draw_region.
With DRI2 we there is no screen region until a drawable is bound to
the context. Set up the framebuffer texture in meta_draw_region instead
which should also handle the case where the draw region changes as a
result of resizing a redirected window or resizing the screen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| a04b632350e5d0e9994fc667afc59407a39da0ba |
|
10-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Add more cliprect modes to cover other meanings for batch emits.
The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:
- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
(copybuffers, clears).
All callers should now be fixed to use one of these states for any batchbuffer
emits. Thanks to Keith Whitwell for pointing out the failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 93c98a466947570e0589b662df49095b2f4bc43c |
|
05-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace 965 texture format code with common code.
The only functional difference should be that 965 now gets the optimization
where textures default to 16bpp when the screen is 16bpp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| db928291dcbda2a820dbb1668c43d2fb4266be7c |
|
10-Aug-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: roland's DXTn format texture patch(bug10347)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 246d1d2522858a1bcf525d64ad165f9af11a2b4d |
|
02-Aug-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Fix previous commit
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 6bf81a5edfa287a396f30188b107ff1761039f3f |
|
02-Aug-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
EXT_texture_sRGB support on i965
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| cf4272d2569940fa4ac2ffaf3afbdc2aa3e5cc06 |
|
20-Mar-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
fix for bug#10347
not sure which brw surface for DXT3 & DXT5, so restore
the previous choice.(changed in commit
84081774e62a8af18e6bf894ea69f63b97dcfe96)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 84081774e62a8af18e6bf894ea69f63b97dcfe96 |
|
18-Mar-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fix for FXT1 & S3TC texture format
choose the right mesa texformat for FXT1 & S3TC
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 3cd06cf8c5ef6a27e36c584e12ba79ed8dacbf28 |
|
29-Nov-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add accelerated CopyPixels for non-overlapping, 1:1 blits.
Submitted by Gary Wong <gtw@gnu.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| cac5974bf9385f8c9bd46f9c90bfa8144f0c33d6 |
|
21-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Do a better job of choosing texture formats to avoid image conversions.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| afd244d4e8dc36895676c1b3bdbdba59f03a6962 |
|
21-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
use the requested internal texture format where possible
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| e38114a5e4492684333251eb22bc60ee1038de55 |
|
20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Support ARB_texture_rectangle.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex.c
|