Cross Reference: /external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines Matching defs:NumVecs
205   /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
208   /// For NumVecs <= 2, QOpcodes1 is not used.
209   SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
213   /// SelectVST - Select NEON store intrinsics.  NumVecs should
216   /// For NumVecs <= 2, QOpcodes1 is not used.
217   SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
221   /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
225                           bool isUpdating, unsigned NumVecs,
228   /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
231   SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
234   /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
237   SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
284   SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1665 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1667   unsigned NumRegs = NumVecs;
1668   if (!is64BitVector && NumVecs < 3)
1730 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1734   assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1745   Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1762     assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1767   if (NumVecs == 1)
1770     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1787   if (is64BitVector || NumVecs <= 2) {
1796       if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode()))
1800       if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
1845   if (NumVecs == 1)
1853   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1856   ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1858     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1862 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1866   assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1881   Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1898     assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1912   if (is64BitVector || NumVecs <= 2) {
1914     if (NumVecs == 1) {
1920       if (NumVecs == 2)
1926         SDValue V3 = (NumVecs == 3)
1946       if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1950       if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
1973   SDValue V3 = (NumVecs == 3)
2008                                          bool isUpdating, unsigned NumVecs,
2011   assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2025     cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2030   if (NumVecs != 3) {
2032     unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2060     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2084   if (NumVecs == 2) {
2091     SDValue V3 = (NumVecs == 3)
2117   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2120   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2122     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2127                                       unsigned NumVecs,
2129   assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2143   if (NumVecs != 3) {
2145     unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2180     else if (NumVecs > 2)
2187   unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2200   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2203   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2205     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2209 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2211   assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2220   if (NumVecs == 2)
2226     SDValue V3 = (NumVecs == 3)
2236   Ops.push_back(N->getOperand(FirstTblReg + NumVecs));