History log of /external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
fd79485dfa4fee67467299720efac2d0c21d846c 29-Jul-2013 Silviu Baranga <silviu.baranga@arm.com> Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2f438131f115a3860ee344a827a091790d6dc13d 16-Jul-2013 Tim Northover <tnorthover@apple.com> ARM: implement ldrex, strex and clrex intrinsics

Intrinsics already existed for the 64-bit variants, so these support operations
of size at most 32-bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
881b0b5c77ec3f6849e32b7763b6c75057b81501 08-Jul-2013 Joey Gouly <joey.gouly@arm.com> Add a comment to this change, requested by Eric Christopher.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
00d9fe2de7f0b8f9d1ea19ae30cc78b1a1e1fb92 05-Jul-2013 Joey Gouly <joey.gouly@arm.com> PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.

In the SelectionDAG immediate operands to inline asm are constructed as
two separate operands. The first is a constant of value InlineAsm::Kind_Imm
and the second is a constant with the value of the immediate.

In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we
should skip over the next operand too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f52578c08c71dc356428c25b0ba8759fd7ee2c66 28-Jun-2013 Eric Christopher <echristo@gmail.com> Remove unused variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
10ddc4d7f232507933c266180d0052f12e65c4ab 28-Jun-2013 Weiming Zhao <weimingz@codeaurora.org> Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARM

This patch assigns paired GPRs for inline asm with
64-bit data on ARM. It's enabled for both ARM and Thumb to support modifiers
like %H, %Q, %R.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ba54bca472a15d0657e1b88776f7069042b60b4e 19-Jun-2013 Bill Wendling <isanbard@gmail.com> Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6a2e7ac0b6647a409394e58b385e579ea62b5cba 06-Jun-2013 Bill Wendling <isanbard@gmail.com> Cache the TargetLowering info object as a pointer.

Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ac6d9bec671252dd1e596fa71180ff6b39d06b5d 25-May-2013 Andrew Trick <atrick@apple.com> Track IR ordering of SelectionDAG nodes 2/4.

Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c6af2432c802d241c8fffbe0371c023e6c58844e 25-May-2013 Michael J. Spencer <bigcheesegs@gmail.com> Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 20-Apr-2013 Michael Liao <michael.liao@intel.com> ArrayRefize getMachineNode(). No functionality change.



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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f793de7a2331edea161eae20f9bdfa86b0d7fd3c 09-Mar-2013 Lang Hames <lhames@gmail.com> Don't glue users to extract_subreg when selecting the llvm.arm.ldrexd
intrinsic - it can cause impossible-to-schedule subgraphs to be
introduced.

PR15053.



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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3853f74aba301ef08b699bac2fa8e53230714a58 07-Mar-2013 Benjamin Kramer <benny.kra@googlemail.com> ArrayRefize some code. No functionality change.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7248451c4307c05cf3ddfa8133f0c5334bab6455 14-Feb-2013 Weiming Zhao <weimingz@codeaurora.org> Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c0c2816fb3d137c096d0bd20b8ad2d92ce25a976 14-Feb-2013 Weiming Zhao <weimingz@codeaurora.org> temporarily revert the patch due to some conflicts

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3019fbbe6ab4c23a5a580f0cc6ba1ba1b124e1da 13-Feb-2013 Weiming Zhao <weimingz@codeaurora.org> Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0b8c9a80f20772c3793201ab5b251d3520b9cea3 02-Jan-2013 Chandler Carruth <chandlerc@gmail.com> Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
733c6b1db1a9a3f78da4fece933ccc7e509bfba0 19-Dec-2012 Evan Cheng <evan.cheng@apple.com> LLVM sdisel normalize bit extraction of the form:
((x & 0xff00) >> 8) << 2
to
(x >> 6) & 0x3fc

This is general goodness since it folds a left shift into the mask. However,
the trailing zeros in the mask prevents the ARM backend from using the bit
extraction instructions. And worse since the mask materialization may require
an addition instruction. This comes up fairly frequently when the result of
the bit twiddling is used as memory address. e.g.

= ptr[(x & 0xFF0000) >> 16]

We want to generate:
ubfx r3, r1, #16, #8
ldr.w r3, [r0, r3, lsl #2]

vs.
mov.w r9, #1020
and.w r2, r9, r1, lsr #14
ldr r2, [r0, r2]

Add a late ARM specific isel optimization to
ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the
'base + offset' address computation; change the mask to one which doesn't have
trailing zeros and enable the use of ubfx.

Note the optimization has to be done late since it's target specific and we
don't want to change the DAG normalization. It's also fairly restrictive
as shifter operands are not always free. It's only done for lsh 1 / 2. It's
known to be free on some cpus and they are most common for address
computation.

This is a slight win for blowfish, rijndael, etc.

rdar://12870177


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d04a8d4b33ff316ca4cf961e06c9e312eff8e64f 03-Dec-2012 Chandler Carruth <chandlerc@gmail.com> Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
35b3df6e31f9aac70fb471d74e39f899dfbd689f 29-Nov-2012 Silviu Baranga <silviu.baranga@arm.com> Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8b149cbfc6cb420016eff52f6380d1eba5daea20 17-Nov-2012 Weiming Zhao <weimingz@codeaurora.org> Rename methods like PairSRegs() to createSRegpairNode() to meet our coding
style requirement.



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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e56764bad10621ac9dcf9d3541533ff2cb0f88b4 16-Nov-2012 Weiming Zhao <weimingz@codeaurora.org> Remove hard coded registers in ARM ldrexd and strexd instructions

This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.



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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
eb1641d54a7eda7717304bc4d55d059208d8ebed 29-Sep-2012 Bob Wilson <bob.wilson@apple.com> Add LLVM support for Swift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
94c22716d60ff5edf6a98a3c67e0faa001be1142 27-Sep-2012 Sylvestre Ledru <sylvestre@debian.org> Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7e2c793a2b5c746344652b6579e958ee42fafdcc 27-Sep-2012 Sylvestre Ledru <sylvestre@debian.org> Fix a typo 'iff' => 'if'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c5252da873d547a19069eaf9030fec203f128f66 14-Sep-2012 Dmitri Gribenko <gribozavr@gmail.com> Fix Doxygen issues:
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
people want -- it starts a new paragraph);
* use \param instead of \arg to document parameters in order to be consistent
with the rest of the codebase.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
616471d4bfe4717fa86259ff4534703357b3b723 13-Sep-2012 Silviu Baranga <silviu.baranga@arm.com> This patch introduces A15 as a target in LLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
67514e90669ec9ffd954c1fcb6f8979bafcabe8a 04-Sep-2012 Arnold Schwaighofer <arnolds@codeaurora.org> Patch to implement UMLAL/SMLAL instructions for the ARM architecture

This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.

Bug 12213

Patch by Yin Ma!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0a8f8980000b753ef77dfc64cc7d9803d5dcc8ce 18-Aug-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the CAND/COR/CXOR custom ISD nodes and their select code.

These nodes are no longer needed because the peephole pass can fold
CMOV+AND into ANDCC etc.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
65bf80e2b7d3c839331be63cdd28a8d101936bca 15-Aug-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add missing Rfalse operand to the predicated pseudo-instructions.

When predicating this instruction:

Rd = ADD Rn, Rm

We need an extra operand to represent the value given to Rd when the
predicate is false:

Rd = ADDCC Rfalse, Rn, Rm, pred

The Rd and Rfalse operands are different registers while in SSA form.
Rfalse is tied to Rd to make sure they get the same register during
register allocation.

Previously, Rd and Rn were tied, but that is not required.

Compare to MOVCC:

Rd = MOVCC Rfalse, Rtrue, pred

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a7016d6fc1c9935ede7b3dc2f39c8cdab14e40e0 12-Aug-2012 Arnold Schwaighofer <arnolds@codeaurora.org> Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM
architecture

It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7
thumb O3.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
bcc4c1d2d1b6877418de92835c537d79d44363a6 09-Aug-2012 Arnold Schwaighofer <arnolds@codeaurora.org> Patch to implement UMLAL/SMLAL instructions for the ARM architecture

This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.

Bug 12213

Patch by Yin Ma!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
046eea5247b62c9c8b230800d224c0be48fd75e0 01-Aug-2012 Jim Grosbach <grosbach@apple.com> Clean up formatting.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2769028ab4732ce6083a71c67dc19b8901f55d5a 01-Aug-2012 Jim Grosbach <grosbach@apple.com> Tidy up.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
51f50c110651cedebdb7194e5e686d3a27dcce4e 24-May-2012 Craig Topper <craig.topper@gmail.com> Make some opcode tables static and const. Allows code to avoid making copies to pass the tables around.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e38993f89288f8dd96451fe3ba514950520757ad 26-Apr-2012 Tim Northover <Tim.Northover@arm.com> Test commit.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1835547ec195c35b3a59bf834f4df942c61a5c53 11-Apr-2012 Jim Grosbach <grosbach@apple.com> ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.

While there is an encoding for it in VUZP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.

rdar://11222366

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6073b30b053da2c2ac6150dd67cecb304bc614f1 11-Apr-2012 Jim Grosbach <grosbach@apple.com> ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.

While there is an encoding for it in VZIP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.

rdar://11221911

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c0fc450f0754508871bc70f21e528bf2f1520da1 06-Mar-2012 Jim Grosbach <grosbach@apple.com> ARM refactor more NEON VLD/VST instructions to use composite physregs

Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
28f08c93e75d291695ea89b9004145103292e85b 05-Mar-2012 Jim Grosbach <grosbach@apple.com> ARM refactor away a bunch of VLD/VST pseudo instructions.

With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1b14f20ef7b35b9209ba6ab394773278936babe9 23-Feb-2012 Duncan Sands <baldrick@free.fr> Remove unused variable.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c892aeb26601cc5109490d30c7e170cb07f84428 23-Feb-2012 Evan Cheng <evan.cheng@apple.com> Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4

should be:
cmp r9, r4
orreq lr, lr, #1

That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).

It's possible to extend this to ADD and SUB but I don't think they are common.

rdar://8659097


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
bc2198133a1836598b54b943420748e75d5dea94 07-Feb-2012 Craig Topper <craig.topper@gmail.com> Convert assert(0) to llvm_unreachable

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 20-Jan-2012 David Blaikie <dblaikie@gmail.com> More dead code removal (using -Wunreachable-code)

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f1f16c832f92829f47573620c20d8420c47bde6c 10-Jan-2012 Jim Grosbach <grosbach@apple.com> ARM updating VST2 pseudo-lowering fixed vs. register update.

rdar://10663487

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e6949b13997e6d31aa4719a0e80c4b6b405e42a9 21-Dec-2011 Jim Grosbach <grosbach@apple.com> ARM NEON assmebly parsing for VLD2 to all lanes instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
bb3a2e4d0defc6854d37384d80858037dbbc5f20 14-Dec-2011 Jim Grosbach <grosbach@apple.com> ARM NEON refactor VST2 w/ writeback instructions.

In addition to improving the representation, this adds support for assembly
parsing of these instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a4e3c7fc4ba2d55695b0484480685698132eba20 09-Dec-2011 Jim Grosbach <grosbach@apple.com> ARM assembly parsing and encoding for VLD2 with writeback.

Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4c7edb3ad8bd513c59190f6ebee9bee34af7d247 29-Nov-2011 Jim Grosbach <grosbach@apple.com> ARM assembly parsing and encoding for four-register VST1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d5ca201891d238ca2185831524a1e3f2670224df 29-Nov-2011 Jim Grosbach <grosbach@apple.com> ARM assembly parsing and encoding for three-register VST1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4334e032525d6c9038605f3871b945e8cbe6fab7 31-Oct-2011 Jim Grosbach <grosbach@apple.com> ARM VST1 w/ writeback assembly parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b0117eed84b7899c677a1da5e074fe3a2b7046dd 28-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Also set addrmode6 alignment when align==size.

Previously, we were only setting the alignment bits on over-aligned
loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
55dabaa73a7a0be4398fae58443f3ad8264e537e 28-Oct-2011 Jim Grosbach <grosbach@apple.com> ARM isel for vld1, opcode selection for register stride post-index pseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
10b90a9bbf7dcae1568c03a03f9606f5395f2144 24-Oct-2011 Jim Grosbach <grosbach@apple.com> ARM refactor am6offset usage for VLD1.

Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0851a29b6d592f6510b5ff17e7607bb3f492fca1 18-Oct-2011 Eli Friedman <eli.friedman@gmail.com> Fix misc warnings. Patch by Joe Abbey.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ef2c86f8760f717882821987664bf5e7604ffe20 11-Oct-2011 Bill Wendling <isanbard@gmail.com> Reapply r141365 now that PR11107 is fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
eba564ceace5861a321c230acf5df32e55ed9be5 10-Oct-2011 Bill Wendling <isanbard@gmail.com> Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
hang, and possibly SPEC/CINT2006/464_h264ref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2d4b60f3a40d4a1d60d43f5bb94c3c3dd19a6fc5 08-Oct-2011 Anton Korobeynikov <asl@math.spbu.ru> Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
244455e6d6bb95c5e556ace66adb148dbcd16a27 07-Oct-2011 Anton Korobeynikov <asl@math.spbu.ru> Peephole optimization for ABS on ARM.
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8f8aa815b46143e2e84a62dadf6f57daf25a4e24 06-Oct-2011 Cameron Zwarich <zwarich@apple.com> Always merge profitable shifts on A9, not just when they have a single use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d78ebe1e12a9aae01cb11d4d10a3d0600407e5ca 06-Oct-2011 Cameron Zwarich <zwarich@apple.com> Remove a check from ARM shifted operand isel helper methods, which were blocking
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
fb77752253717bc9c26cd2f6915925dc19edb8a3 05-Oct-2011 Cameron Zwarich <zwarich@apple.com> Add braces around something that throws me for a loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5ee02620146bda648a191da6323c34887b987a8a 05-Oct-2011 Cameron Zwarich <zwarich@apple.com> There is no point in setting out-parameters for a ComplexPattern function when
it returns false, at least as far as I could tell by reading the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
11ebe3d7c11521b2f092165ac712c9ea0f4c462f 24-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Also match negative offsets for addrmode3 and addrmode5.

Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b04546ff5b1a7a03eec1076900c945223bf494cc 13-Sep-2011 Jim Grosbach <grosbach@apple.com> Tidy up a few 80 column violations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d84192fe4f6495e43ee0ff2ac591c14ba36e1e9d 31-Aug-2011 Owen Anderson <resistor@mac.com> When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
<rdar://problem/10046188>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4d3f3294535a3b622c715f2d9675d4f3e86c3378 31-Aug-2011 Eli Friedman <eli.friedman@gmail.com> 64-bit atomic cmpxchg for ARM.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2bdffe488203a08a2ca98548a157e0eaf39d4b2d 31-Aug-2011 Eli Friedman <eli.friedman@gmail.com> Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c4e16de7652128545c252affa357c3a105ed59a3 29-Aug-2011 Owen Anderson <resistor@mac.com> addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2b568fb3ce0fa7a7ff3a01c83a0d04765214275c 26-Aug-2011 Owen Anderson <resistor@mac.com> Fix ARM codegen breakage caused by r138653.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9ab0f25fc194b4315db1b87d38d4024054120bf6 26-Aug-2011 Owen Anderson <resistor@mac.com> invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5b81584f7403ffdb9cc6babaaeb0411c080e0f81 24-Aug-2011 Jim Grosbach <grosbach@apple.com> Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.

Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
19dec207fcc0f04902b7f097b7771ba7abba43fb 05-Aug-2011 Jim Grosbach <grosbach@apple.com> ARM refactor indexed store instructions.

Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
fb8989e64024547e4ad5ab6fe4d94fe146a7899f 27-Jul-2011 Jim Grosbach <grosbach@apple.com> ARM parsing and encoding of SBFX and UBFX.

Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
793e79601f0fd68ba082fa2016018f80b2379460 26-Jul-2011 Owen Anderson <resistor@mac.com> Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e0a03143df398c17a435c136b14316fd43f27fb7 22-Jul-2011 Owen Anderson <resistor@mac.com> Fix test failures caused by my so_reg refactoring.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
152d4a4bb6b75de740b4b8a9f48abb9069d50c17 22-Jul-2011 Owen Anderson <resistor@mac.com> Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
92a202213bb4c20301abf6ab64e46df3695e60bf 21-Jul-2011 Owen Anderson <resistor@mac.com> Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ee04a6d3a40c3017124e3fd89a0db473a2824498 21-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e837dead3c8dc3445ef6a0e2322179c57e264a13 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1300f3019e5d590231bbc3d907626708515d3212 16-Jun-2011 Owen Anderson <resistor@mac.com> Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a0112d0c39aa31fe555ecf7296923ca30f68f811 28-May-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b451770b264f9ef58d9565fdcd13551a89606cd4 30-Apr-2011 Eli Friedman <eli.friedman@gmail.com> Zap a couple now-unused functions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
84c5eed15baa3710d7fb8522c7a28c8e0b732c2b 19-Apr-2011 Bob Wilson <bob.wilson@apple.com> This patch combines several changes from Evan Cheng for rdar://8659675.

Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.

Enable these fp vmlx codegen changes for Cortex-A9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b58a340fa2affa0da27a46c94dd49ba079c9343c 19-Apr-2011 Evan Cheng <evan.cheng@apple.com> Do not lose mem_operands while lowering VLD / VST intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
099e5553ebb868c06379ef05e56aae2346eaaa38 18-Mar-2011 Owen Anderson <resistor@mac.com> Reduce code duplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
69a05a7b9205fd4628ed614d1845f3879f6be949 15-Mar-2011 Bill Wendling <isanbard@gmail.com> Generate a VTBL instruction instead of a series of loads and stores when we
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:

_shuf:
@ BB#0: @ %entry
push {r4, r7, lr}
add r7, sp, #4
sub sp, #12
mov r4, sp
bic r4, r4, #7
mov sp, r4
mov r2, sp
vmov d16, r0, r1
orr r0, r2, #6
orr r3, r2, #7
vst1.8 {d16[0]}, [r3]
vst1.8 {d16[5]}, [r0]
subs r4, r7, #4
orr r0, r2, #5
vst1.8 {d16[4]}, [r0]
orr r0, r2, #4
vst1.8 {d16[4]}, [r0]
orr r0, r2, #3
vst1.8 {d16[0]}, [r0]
orr r0, r2, #2
vst1.8 {d16[2]}, [r0]
orr r0, r2, #1
vst1.8 {d16[1]}, [r0]
vst1.8 {d16[3]}, [r2]
vldr.64 d16, [sp]
vmov r0, r1, d16
mov sp, r4
pop {r4, r7, pc}

The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3c5edaaf59dc051c6d540dd1041cf6bbbb12854f 12-Mar-2011 Jim Grosbach <grosbach@apple.com> Remove dead code. These ARM instruction definitions no longer exist.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4faa0e19521f700ad10bfea69e141fc46c45f78b 05-Mar-2011 Bob Wilson <bob.wilson@apple.com> Remove unused conditional negate operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
da52506792f1791682eda34d6319f5967116eb65 25-Feb-2011 Bob Wilson <bob.wilson@apple.com> Add patterns to use post-increment addressing for Neon VST1-lane instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0a9481f44fe4fc76e59109992940a76b2a3f9b3b 13-Feb-2011 Chris Lattner <sabre@nondot.org> Enhance ComputeMaskedBits to know that aligned frameindexes
have their low bits set to zero. This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.

Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively. Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST). The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1c3ef90cab9a563427bdd3c2fcd875c717750562 07-Feb-2011 Bob Wilson <bob.wilson@apple.com> Add codegen support for using post-increment NEON load/store instructions.

The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7de6814405ab02591235f0826b8e6d98fd76c8ba 07-Feb-2011 Bob Wilson <bob.wilson@apple.com> Change VLD3/4 and VST3/4 for quad registers to not update the address register.

These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used. In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 20-Jan-2011 Evan Cheng <evan.cheng@apple.com> Sorry, several patches in one.

TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
to re-materialize the instruction, allow machine LICM to hoist the set of
instructions out of the loop and make it possible to CSE them. It's a bit
hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ec91d52a77abfe3cf56413a11f47b3ee8e67e41e 19-Jan-2011 Daniel Dunbar <daniel@zuster.org> ARM/ISel: Factor out isScaledConstantInRange() helper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5de5d4b6d0eb3fd379fa571d82f6fa764460b3b8 17-Jan-2011 Evan Cheng <evan.cheng@apple.com> Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4d7286083537833880901953d29786cf831affc4 01-Jan-2011 Anton Korobeynikov <asl@math.spbu.ru> Model operand restrictions of mul-like instructions on ARMv5 via
earlyclobber stuff. This should fix PRs 2313 and 8157.

Unfortunately, no testcase, since it'd be dependent on register
assignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6e8f4c404825b79f9b9176483653f1aa927dfbde 24-Dec-2010 Andrew Trick <atrick@apple.com> whitespace


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 21-Dec-2010 Chris Lattner <sabre@nondot.org> rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a1f544b62e5d9eae0311dfb3a0b0e72f25e041d4 17-Dec-2010 Bob Wilson <bob.wilson@apple.com> Use PairDRegs to implement ConcatVectors. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3e333637f172c30adf5c8333b592fbde17ff9f78 16-Dec-2010 Jim Grosbach <grosbach@apple.com> Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
bc4224bc6bc078b249b030c54f532215f61935c5 15-Dec-2010 Bill Wendling <isanbard@gmail.com> Reapply r121808 now that the missing patterns have been supplied.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7d1d8db54a8257bc6d954ff73f35171d757beafc 15-Dec-2010 Bill Wendling <isanbard@gmail.com> Revert r121808 until I can fix the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2af0fd3fee1f65f11ff6ca003c51ac9c640328a4 15-Dec-2010 Bill Wendling <isanbard@gmail.com> Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
particular, we want

ldr r2, [r3]

to be equivalent to

ldr r2, [r3, #0]

and not

ldr r2, [r3, r0]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f4caf69720d807573c50d41aa06bcec1c99bdbbd 14-Dec-2010 Bill Wendling <isanbard@gmail.com> The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a92bac64cb75853c65a6146e015c2bf60c710869 10-Dec-2010 Bob Wilson <bob.wilson@apple.com> Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions.
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed. Add tests for this, too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
48575f6ea7d5cd21ab29ca370f58fcf9ca31400b 05-Dec-2010 Evan Cheng <evan.cheng@apple.com> Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6c4c982f83eea655e0f14610d2689fad722aeb7d 30-Nov-2010 Bob Wilson <bob.wilson@apple.com> Add support for NEON VLD3-dup instructions.
The encoding for alignment in VLD4-dup instructions is still a work in progress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
86c6d80a7a20fa7decc3e914be5d1cb0f7f29a6f 29-Nov-2010 Bob Wilson <bob.wilson@apple.com> Add support for NEON VLD3-dup instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b1dfa7a8e0c1972231bee636afd5239b009ba4da 28-Nov-2010 Bob Wilson <bob.wilson@apple.com> Add support for NEON VLD2-dup instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ff96b63d6fb0b6e6eccdabcbdc4eeeb69e54c648 20-Nov-2010 Evan Cheng <evan.cheng@apple.com> Fix a cut-n-paste-error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6b19491468e44249a35d869642e7302aaacb220b 17-Nov-2010 Evan Cheng <evan.cheng@apple.com> Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
63f3544a7f6ca09e7515d6b0e1bf9e8e884131e2 13-Nov-2010 Evan Cheng <evan.cheng@apple.com> Add conditional move of large immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e5e0ef180ea1d0d7b482f998db12defde96cbf4f 13-Nov-2010 Evan Cheng <evan.cheng@apple.com> Fix an obvious typo which inverted an immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
875a6ac09a2a4ae2d83dfe262a81d6eb33c24022 12-Nov-2010 Evan Cheng <evan.cheng@apple.com> Add conditional mvn instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
cdfad36b401be6fc709ea4051f9de58e1a30bcc9 03-Nov-2010 Duncan Sands <baldrick@free.fr> Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e6913600c723a10ab1f06a43c93d82ee8e26c71c 03-Nov-2010 Jim Grosbach <grosbach@apple.com> Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
665814b6be3e44fdb84bcf1b7e5c933b60fbf280 02-Nov-2010 Bob Wilson <bob.wilson@apple.com> Add support for alignment operands on VLD1-lane instructions.
This is another part of the fix for Radar 8599955.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f40deed62f4f0126459ed7bfd1799f4e09b1aaa7 28-Oct-2010 Evan Cheng <evan.cheng@apple.com> Shifter ops are not always free. Do not fold them (especially to form
complex load / store addressing mode) when they have higher cost and
when they have more than one use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3e5561247202bae994dd259a2d8dc4eff8f799f3 27-Oct-2010 Jim Grosbach <grosbach@apple.com> First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3ab5658a127d78c4bcf2b4a69fb838f14f833f0a 21-Oct-2010 Jim Grosbach <grosbach@apple.com> trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3454ed9545d10064d84e45ad9a9ea26dddc255ba 19-Oct-2010 Bob Wilson <bob.wilson@apple.com> Support alignment for NEON vld-lane and vst-lane instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a4257162be84d9d606a42e9db5ce2163426949e3 07-Oct-2010 Jim Grosbach <grosbach@apple.com> Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3bbdcea49abddea69d124e7ef055c9fdaa8d12f6 07-Oct-2010 Jim Grosbach <grosbach@apple.com> Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
828916203a731c5031fbe440f1fc6cdf82b2e711 29-Sep-2010 Jim Grosbach <grosbach@apple.com> Add specializations of addrmode2 that allow differentiating those forms
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
be91232900776c23d4b327be7bc3f03f711d11a8 29-Sep-2010 Jim Grosbach <grosbach@apple.com> Add braces for legibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2a6e6161422154ea44f9e653e2d0bbfc3942af2b 24-Sep-2010 Bob Wilson <bob.wilson@apple.com> Set alignment operand for NEON VST instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
40ff01a0305403541353ac83f9f498ab67ebe944 23-Sep-2010 Bob Wilson <bob.wilson@apple.com> Set alignment operand for NEON VLD instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
52a261b3c1391c5fec399ddeb3fc6ee9541e8790 21-Sep-2010 Chris Lattner <sabre@nondot.org> fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
23da0b23a3f01d9a46e54a4ba6fc6e4b42eda7c1 14-Sep-2010 Eric Christopher <echristo@apple.com> Fix QOpcode assignment to Opc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
bd916c54b7989ddbab373c61eb1ed2556ca44d27 14-Sep-2010 Bob Wilson <bob.wilson@apple.com> Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8466fa1842ad4f2d6fadcf5c23c15319ae96b972 14-Sep-2010 Bob Wilson <bob.wilson@apple.com> Switch all the NEON vld-lane and vst-lane instructions over to the new
pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
979b0618192cd99058a7a21c04341c47801dd688 06-Sep-2010 Chris Lattner <sabre@nondot.org> remove some dead code. t2addrmode_imm8s4 is never used in a
pattern, so there is no need to define a matching function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f572191fe43025bd85ab5d398a5b53305fdc6b8b 03-Sep-2010 Bob Wilson <bob.wilson@apple.com> Finish converting the rest of the NEON VLD instructions to use pseudo-
instructions prior to regalloc. Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ffde080ae615906545eb33dab30e7bc47c2ac838 02-Sep-2010 Bob Wilson <bob.wilson@apple.com> Convert VLD1 and VLD2 instructions to use pseudo-instructions until
after regalloc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5bcb8a6112eca5fb72b39b6b4e608ab1b41e94de 01-Sep-2010 Chris Lattner <sabre@nondot.org> temporarily revert r112664, it is causing a decoding conflict, and
the testcases should be merged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
43a6c5e2fccadb299c35cb3147d112f706922acd 01-Sep-2010 Bill Wendling <isanbard@gmail.com> We have a chance for an optimization. Consider this code:

int x(int t) {
if (t & 256)
return -26;
return 0;
}

We generate this:

tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0

while gcc generates this:

ands r0, r0, #256
it ne
mvnne r0, #25
bx lr

Scandalous really!

During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):

%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]

All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e5ce4f68c786696a96acf1f1aa5431652abb6ce7 28-Aug-2010 Bob Wilson <bob.wilson@apple.com> Use pseudo instructions for VST1 and VST2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
fd7fd940c33ee48265cb8947d99f21a6711bd9d6 28-Aug-2010 Bob Wilson <bob.wilson@apple.com> We don't need to custom-select VLDMQ and VSTMQ anymore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d4bfd54ec2947e73ab152c3c548e4dd4beb700ba 28-Aug-2010 Bob Wilson <bob.wilson@apple.com> Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
01ba461af7eafc9d181a5c349487691f2e801438 26-Aug-2010 Bob Wilson <bob.wilson@apple.com> Use pseudo instructions for VST3.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
70e48b23a3455e4689ee24cec4eb153d67223e86 26-Aug-2010 Bob Wilson <bob.wilson@apple.com> Use pseudo instructions for VST1d64Q.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
709d59255a3100c7d440c93069efa1f726677a27 26-Aug-2010 Bob Wilson <bob.wilson@apple.com> Start converting NEON load/stores to use pseudo instructions, beginning here
with the VST4 instructions. Until after register allocation, we want to
represent sets of adjacent registers by a single super-register. These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands. Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
00d3dda86f825f32277eba8c4206f48fbfc9f584 17-Aug-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Don't call tablegen'ed Predicate_* functions in the ARM target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a2c519bd0bdb19d4bb1f2377fcf429653af95960 31-Jul-2010 Evan Cheng <evan.cheng@apple.com> Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
78dfbc380d685c59b9321e43c10677a179850e29 07-Jul-2010 Bob Wilson <bob.wilson@apple.com> Also use REG_SEQUENCE for VTBX instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d491d6ecd2debd444451f07e6e947685d1e02217 07-Jul-2010 Bob Wilson <bob.wilson@apple.com> Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
allocated to consecutive registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
978189e090e809c1a6efcf2677e785a06f71029e 29-Jun-2010 Duncan Sands <baldrick@free.fr> Remove an unused and a pointless variable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e368b460a206fafa0d31d5d059b1779b94f7df8c 18-Jun-2010 Dan Gohman <gohman@apple.com> Eliminate unnecessary uses of getZExtValue().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
07f6e805b1e832a2c34a83862cec27736bb471bf 16-Jun-2010 Bob Wilson <bob.wilson@apple.com> Remove the hidden "neon-reg-sequence" option. The reg sequences are working
now, so there's no need to disable them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
40cbe7d5d41d22d32e8ce773548f510fd1ee0ed9 04-Jun-2010 Bob Wilson <bob.wilson@apple.com> For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
51e28e634880849ed9f7c02e93c08d25dd70291b 03-Jun-2010 Dale Johannesen <dalej@apple.com> Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
18f30e6f5e80787808fe1455742452a5210afe07 02-Jun-2010 Jim Grosbach <grosbach@apple.com> Clean up 80 column violations. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
13ef8408073e00d3ae04067deee79721c62af209 28-May-2010 Bob Wilson <bob.wilson@apple.com> Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7bb31e3187c0ba5a076313e5fe9dd869500a6ecf 24-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Fix a few places that depended on the numeric value of subreg indices.
Add assertions in places that depend on consecutive indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
558661d2718cf5750907c449d36ff1231924a2d1 24-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3c3195cbf19030ae3b1c854f3a3cd5fcef520e07 19-May-2010 Evan Cheng <evan.cheng@apple.com> Target instruction selection should copy memoperands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
620612425082ab5d6c6016ae59f8ae9afc6c5776 17-May-2010 Evan Cheng <evan.cheng@apple.com> Turn on -neon-reg-sequence by default.

Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8f6de385d64922b6d42b91a4d63f862b33ca13e8 16-May-2010 Evan Cheng <evan.cheng@apple.com> Model vst lane instructions with REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7189fd03fa66642b58b1e88be385bedeff0ac91d 15-May-2010 Evan Cheng <evan.cheng@apple.com> Model 128-bit vld lane with REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7092c2bfcb91c367b091e037f0568e249e1b0a57 15-May-2010 Evan Cheng <evan.cheng@apple.com> Model 64-bit lane vld with REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
12c24690c7dc53cf6e6ca8cb062255e82d568edf 15-May-2010 Evan Cheng <evan.cheng@apple.com> Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5c6aba2e3ac2239a3de85a77f09cdac9eef68467 14-May-2010 Evan Cheng <evan.cheng@apple.com> Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7f687195175f01d820eea70e8a647a61d5b99fce 14-May-2010 Evan Cheng <evan.cheng@apple.com> Fix comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0ce537a9db2da085ab50b15d2454cb7cac460eb7 11-May-2010 Evan Cheng <evan.cheng@apple.com> Model some vst3 and vst4 with reg_sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e9e2ba05de573f926f1d054add7ddbf15eab178a 10-May-2010 Evan Cheng <evan.cheng@apple.com> Model some vld3 instructions with REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
603afbfe2ac8ccc21283b149a76a81eb44b956b0 10-May-2010 Evan Cheng <evan.cheng@apple.com> Model vld2 / vst2 with reg_sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
429009b0f1bef035b8ad1705edb7f1741ddaa427 06-May-2010 Bob Wilson <bob.wilson@apple.com> Add a missing break statement to fix unintentional fall-through
(replacing the previous patch for the same issue).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d31f00b7f78aff0aaec8322a1a9eccca915b88f4 06-May-2010 Jim Grosbach <grosbach@apple.com> Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
de8aa4ed9c8d3654e08eda3973e0500ddc7ac0fd 05-May-2010 Evan Cheng <evan.cheng@apple.com> Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
94cc6d3a2b0a424527edcddd1875ed649e8b84f0 04-May-2010 Evan Cheng <evan.cheng@apple.com> With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3a1287b470bde29d10e7c6998fb69b74d2265b6c 23-Apr-2010 Jim Grosbach <grosbach@apple.com> Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
extraction. This fixes PR5998.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d858e90f039f5fcdc2fa93035e911a5a9505cc50 17-Apr-2010 Dan Gohman <gohman@apple.com> Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
47b7b9f228435a7b570ab6fc9f3a9c44ff301ef2 16-Apr-2010 Evan Cheng <evan.cheng@apple.com> Use getAL() rather than a major constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3a1588a2e38d57de3c4277f071f2316fb3dbc37a 16-Apr-2010 Evan Cheng <evan.cheng@apple.com> Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0ea7d219ec5bb45a0b3e96c01070cfc21227291d 15-Apr-2010 Evan Cheng <evan.cheng@apple.com> ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908

llvm is generating poor code for dynamic alloca, I'll fix that later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101383 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6b 23-Mar-2010 Bob Wilson <bob.wilson@apple.com> Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
11d98997590a1d636b04c4f0756eded6b2d037f3 23-Mar-2010 Bob Wilson <bob.wilson@apple.com> Change VST1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
621f1952430ee8b01b21ac94404e52500d79838b 23-Mar-2010 Bob Wilson <bob.wilson@apple.com> Change VLD1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a6979754da61adbf1e7e21b5fc22a52d9074887e 22-Mar-2010 Bob Wilson <bob.wilson@apple.com> Rename some VLD1/VST1 instructions to match the implementation, i.e., the
corresponding NEON instructions, instead of operation they are currently
used for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
226036ee731a2041f37f28f958d2b6a50373f4f4 20-Mar-2010 Bob Wilson <bob.wilson@apple.com> Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
95ffecd4fe404b622c3f984995bc9e849be297a0 20-Mar-2010 Bob Wilson <bob.wilson@apple.com> Rename some instructions for consistency and sanity: use "_UPD" suffix for
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a43e6bf69093b9870548e7d782ea148e2ddd6449 17-Mar-2010 Bob Wilson <bob.wilson@apple.com> Revert 98683. It is breaking something in the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
bb6c77e6b9be405fb4d57c8ee4cddc2018df392c 16-Mar-2010 Bob Wilson <bob.wilson@apple.com> Remove redundant writeback flag from ARM address mode 6. Also remove the
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7c306da505e2d7f64e160890b274a47fa0740962 02-Mar-2010 Chris Lattner <sabre@nondot.org> Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

17 files changed, 114 insertions(+), 430 deletions(-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
014bf215c3457bb34fee348265e8f63a70b4d503 15-Feb-2010 Evan Cheng <evan.cheng@apple.com> Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
518bb53485df640d7b7e3f6b0544099020c42aa7 09-Feb-2010 Chris Lattner <sabre@nondot.org> move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f609bb8466e28ef63eb4db9de485583c6d5b8bc9 19-Jan-2010 Evan Cheng <evan.cheng@apple.com> Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3482c8003ad0c88469b7333aaf658036e3fd0468 18-Jan-2010 Jim Grosbach <grosbach@apple.com> Patch by David Conrad:

"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
507d32aad2152a9b889df085feca2f653925456c 17-Jan-2010 Bob Wilson <bob.wilson@apple.com> Fix an off-by-one error that caused the chain operand to be dropped from Neon
vector load-lane and store-lane instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
eeb3a00b84b7767d236ec8cf0619b9217fc247b9 05-Jan-2010 Dan Gohman <gohman@apple.com> Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5cdc3a949af0cef7f2163f8a7acbf3049c226321 24-Nov-2009 Anton Korobeynikov <asl@math.spbu.ru> Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ac0869dc8a7986855c5557cc67d4709600158ef5 21-Nov-2009 Evan Cheng <evan.cheng@apple.com> Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9ef4835bd879e1baa5f59619b958cae57d516481 20-Nov-2009 Evan Cheng <evan.cheng@apple.com> Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
07ba906413ed0e8e196a6795665f349ba8fdca4c 19-Nov-2009 Evan Cheng <evan.cheng@apple.com> Refactor cmov selection code out to a separate function. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ed54de40a712ab6471a6c369e30d827017a67757 19-Nov-2009 Evan Cheng <evan.cheng@apple.com> 80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5 09-Nov-2009 Jim Grosbach <grosbach@apple.com> Use Unified Assembly Syntax for the ARM backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8a5ec86a3d4d599984e52c0c5a3a6a436607cf3e 07-Nov-2009 Jim Grosbach <grosbach@apple.com> Support alignment specifier for NEON vld/vst instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
73bb251cd7a535fb93bb3a52eda61555fb253f41 05-Nov-2009 Dan Gohman <gohman@apple.com> Remove uninteresting and confusing debug output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
69e8445ced222d856c850963586800f9385d110a 02-Nov-2009 Bob Wilson <bob.wilson@apple.com> Prune unnecessary include.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6a3b5eec8919da6c45addb6254ffb929af243378 27-Oct-2009 Johnny Chen <johnny.chen@apple.com> Test commit. Added '.' to the comment line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8000c6c535c5a1d8515299072b51fd1baa8b632f 22-Oct-2009 Evan Cheng <evan.cheng@apple.com> Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2095659a8551fb222d145bc8dfa6cf5d15048e42 21-Oct-2009 Evan Cheng <evan.cheng@apple.com> Match more patterns to movt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
681a2ad40357fbf0415977d76323e9a03ada84ae 14-Oct-2009 Bob Wilson <bob.wilson@apple.com> Remove unused variables to fix build warning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
24f995d84b1fcb556f07ee40983f287cd13b2aa2 14-Oct-2009 Bob Wilson <bob.wilson@apple.com> Refactor code to select NEON VST intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3e36f13ba738d9ab9123aadd486ab919f517387f 14-Oct-2009 Bob Wilson <bob.wilson@apple.com> Refactor code to select NEON VLD intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9649344cb5e919f0d251c8b5b966259f3e7445bb 14-Oct-2009 Bob Wilson <bob.wilson@apple.com> More refactoring. NEON vst lane intrinsics can share almost all the code for
vld lane intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a7c397c9c30df38901751abdcfa2c1c5e310d2e5 14-Oct-2009 Bob Wilson <bob.wilson@apple.com> Refactor code for selecting NEON load lane intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e72142aa5b8bcd9266a5a2f88e4e227dd178f233 14-Oct-2009 Bob Wilson <bob.wilson@apple.com> More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
by creating TargetConstants during instruction selection instead of during
legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
765cc0b9d59bf63dfcb02e3d126ea1c63e16f86f 13-Oct-2009 Bob Wilson <bob.wilson@apple.com> Revise ARM inline assembly memory operands to require the memory address to
be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4e1ed88026dadbb508930b3dd30f84bffd01da7e 13-Oct-2009 Sandeep Patel <deeppatel1987@gmail.com> Fix method name in comment, per Bob Wilson.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
47eedaa8fa597e3302012b0ef8f24c4886ef6188 13-Oct-2009 Sandeep Patel <deeppatel1987@gmail.com> Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5631139a699578e3281a1ae09f2cdf4d332179c8 09-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8cdb26968669692e88ee0e4a444032bbd52da0d2 09-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c5c6edb74f5586f2436d8aafe638703ab56dd5f1 09-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
62e053e5a1e36ce8b59bf3311e84b619356da96c 09-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
Also fix some copy-and-paste errors in previous changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0bf7d998b4e8a3edd2495bae6c35083a535b461a 09-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
30aea9d96ef8226749ff1eb73c2f3cb19668e077 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
cd7e327cdf6f3b6171905dec615cc7bf3b24f1ac 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Clean up some unnecessary initializations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
af4a891273b82798e97ad3e59359d93f3c8d6c19 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Clean up a comment (indentation was wrong).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
deb3141cf522cdd9f9330c8100280031ba5e0d9d 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5adf60c03bcc72dd5462bdc4a5c72c1247a7879d 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
24e04c535f528c27955664a8f4524ae33213e453 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0ea38bb93955a64477a66f9adca7eadab6635050 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c67160c010b9aae5e7f912eaeee42cd0da6880c5 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a4288080e62c6ecf94ebeafe84ab33a3b627d209 08-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
63c906343468dca4ac67ed85242d5a9fee95d57f 07-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst4 intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
66a70639dae4cbead3f9799406d98cb4293f2af5 07-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst3 intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d285575f87f1315a38bd23f89e75a776e102cd39 07-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vst2 intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7708c22baafcbfa407fc3441d73f6f3533ccf455 07-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld4 intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ff8952e8a9dc01bba9605e90bd3b823d3cf43619 07-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld3 intrinsics with 128-bit vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
228c08b8ddff75a9d5d617ab12eb683a25fe17a8 07-Oct-2009 Bob Wilson <bob.wilson@apple.com> Rearrange code for selecting vld2 intrinsics. No functionality change.
This is just to be more consistent with the forthcoming code for vld3/4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3bf12ab860751a55fc8c16517a992497b98be11b 07-Oct-2009 Bob Wilson <bob.wilson@apple.com> Add codegen support for NEON vld2 operations on quad registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
522ce975327e1aeba8317b233cdb54366e2645b5 28-Sep-2009 Bob Wilson <bob.wilson@apple.com> Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel. Radar 7250345.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6a2fa325c1763a0fb27eceaa78b3a9bf683416bf 28-Sep-2009 Anton Korobeynikov <asl@math.spbu.ru> Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
602b0c8c17f458d2c80f2deb3c8e554d516ee316 25-Sep-2009 Dan Gohman <gohman@apple.com> Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8a3198b770c9fa7e8319a96bcbcfd85202342eef 01-Sep-2009 Bob Wilson <bob.wilson@apple.com> Add support for generating code for vst{234}lane intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
243fcc5a6901e75e7ca5c374e706a634593ec17f 01-Sep-2009 Bob Wilson <bob.wilson@apple.com> Generate code for vld{234}_lane intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
31fb12f93a30cca700a20088e97d8b05d13d5fca 26-Aug-2009 Bob Wilson <bob.wilson@apple.com> Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
24f20e083280d979e8fa1bc88959ae9e8339ee99 22-Aug-2009 Devang Patel <dpatel@apple.com> Record variable debug info at ISel time directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
051cfd683f698b0061656fbff01d3971d2f3d58c 21-Aug-2009 Anton Korobeynikov <asl@math.spbu.ru> Fix some typos and use type-based isel for VZIP/VUZP/VTRN

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
62e84f177d4519bf719d188496faf8b6c247e3a7 21-Aug-2009 Anton Korobeynikov <asl@math.spbu.ru> Add nodes & dummy matchers for some v{zip,uzp,trn} instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d4b4cf524b8afc342b618254d69f48f214b60093 21-Aug-2009 Bob Wilson <bob.wilson@apple.com> Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
bba9f5f37859f1d53ff061695bfc8c22133c6f0e 14-Aug-2009 Evan Cheng <evan.cheng@apple.com> Indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0ce371082565330672c276f76297f46b362d74b7 14-Aug-2009 Bob Wilson <bob.wilson@apple.com> During legalization, change Neon vdup_lane operations from shuffles to
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78993 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1d0be15f89cb5056e20e2d24faa8d6afb1573bca 13-Aug-2009 Owen Anderson <resistor@mac.com> Push LLVMContexts through the IntegerType APIs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
007ea274f4ab85bfc7698240eb5afd5a779ec330 12-Aug-2009 Evan Cheng <evan.cheng@apple.com> Shrink Thumb2 movcc instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
dbd3c0e06dcd4b94c291388b365a93a3710335af 12-Aug-2009 Bob Wilson <bob.wilson@apple.com> Add missing chain operands for VLD* and VST* instructions.
Set "mayLoad" and "mayStore" on the load/store instructions.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b89030ab6554d84de4331c2853edac4dbf8da9b9 12-Aug-2009 Evan Cheng <evan.cheng@apple.com> Shrinkify Thumb2 r = add sp, imm.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
825b72b0571821bf2d378749f69d6c4cfb52d2f9 11-Aug-2009 Owen Anderson <resistor@mac.com> Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
764ab52dd80310a205c9888bf166d09dab858f90 11-Aug-2009 Jim Grosbach <grosbach@apple.com> Whitespace cleanup. Remove trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3a21425dbe09c7ac85e6b156f82184dd6132435a 11-Aug-2009 Evan Cheng <evan.cheng@apple.com> Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78658 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b0abb4dc4203b903d8d0b48a952ba0a6312eeeb7 11-Aug-2009 Bob Wilson <bob.wilson@apple.com> Use vAny type to get rid of Neon intrinsics that differed only in whether
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a407ca16c29b4e91ef3cf9e188ac2e3ab6920cd8 11-Aug-2009 Dan Gohman <gohman@apple.com> Fix a bug where DAGCombine was producing an illegal ConstantFP
node after legalize, and remove the workaround code from the
ARM backend.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e50ed30282bb5b4a9ed952580523f2dda16215ac 11-Aug-2009 Owen Anderson <resistor@mac.com> Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e2b861f7d91c09115cd637614b1bc5f5154bce1d 10-Aug-2009 Evan Cheng <evan.cheng@apple.com> Handle the constantfp created during post-legalization dag combiner phase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
baf31088f1472f48ea5ae81f0b93636cc44ca444 08-Aug-2009 Anton Korobeynikov <asl@math.spbu.ru> Use VLDM / VSTM to spill/reload 128-bit Neon registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b6ab51e8297281888b85eee8c38215eab2649c4b 08-Aug-2009 Bob Wilson <bob.wilson@apple.com> Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
so I generalized the class for VTRN in the .td file to handle all 3 of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
64efd90f8c878214abc29afa3d1c1e7bfe854a49 08-Aug-2009 Bob Wilson <bob.wilson@apple.com> Implement Neon VTRN instructions. For now, anyway, these are selected
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
861986401e05e437cb33bfd8320d510b956fe41e 07-Aug-2009 Evan Cheng <evan.cheng@apple.com> It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.

This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b36ec86c01e3c3238dca621648f017aef96dda60 06-Aug-2009 Bob Wilson <bob.wilson@apple.com> Implement Neon VST[234] operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0cedab9a0d5127049ac1da54e2891d91796e5c61 06-Aug-2009 Bob Wilson <bob.wilson@apple.com> Neon does not actually have VLD{234}.64 instructions.
These operations will have to be synthesized from other instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4a3d35abefa3a1f6558ef88b25f2a320c76d5328 05-Aug-2009 Bob Wilson <bob.wilson@apple.com> Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a6d658620f1b8803825d3d3adc5d5ed9b36dc422 03-Aug-2009 Bob Wilson <bob.wilson@apple.com> Lower CONCAT_VECTOR during legalization instead of matching it during isel.
Add a testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
13f8b36205607ff87ad0c4daf28f63b2660e7c0f 01-Aug-2009 Evan Cheng <evan.cheng@apple.com> Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
07337c0fcf04fff3f62d3727097347f8be299c9e 31-Jul-2009 David Goodwin <david_goodwin@apple.com> Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d8c95b5ac2ae0619c22434dbdd993196ea82489b 30-Jul-2009 David Goodwin <david_goodwin@apple.com> Cleanup and include code selection for some frame index cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d83360694a6d82772cf31a0be8a64570c2e5cb88 27-Jul-2009 Evan Cheng <evan.cheng@apple.com> Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
eed707b1e6097aac2bb6b3d47271f6300ace7f2e 25-Jul-2009 Owen Anderson <resistor@mac.com> Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5ff58b5c3ab6df332600678798ea5c69c5e943d3 24-Jul-2009 David Goodwin <david_goodwin@apple.com> Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
eadf04992aea8d3efbc89d8e5920044d7a652e22 23-Jul-2009 Evan Cheng <evan.cheng@apple.com> Use getTargetConstant instead of getConstant since it's meant as an constant operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
78dd9dbdfb55f1f1878e5000bd1f4ab1a0607f01 22-Jul-2009 Evan Cheng <evan.cheng@apple.com> Eliminate a redudant check Eli pointed out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
af9e7a7c20d541cfaaaed9dfa21046ac6652cc03 21-Jul-2009 Evan Cheng <evan.cheng@apple.com> Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
31e7eba06fdd74d72501b82fbedfb9724346c2ce 20-Jul-2009 David Goodwin <david_goodwin@apple.com> Use t2LDRri12 for frame index loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7ecc850cf19b365a88f30c3f300d3979b960fe8b 15-Jul-2009 David Goodwin <david_goodwin@apple.com> Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9adc0abad3c3ed40a268ccbcee0c74cb9e1359fe 15-Jul-2009 Owen Anderson <resistor@mac.com> Move EVER MORE stuff over to LLVMContext.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4cb73525a943d69da0f2b0c31c1a1d7f3cdd879d 14-Jul-2009 David Goodwin <david_goodwin@apple.com> Check for PRE_INC and POST_INC.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
419c6150877bb35bd3a95a3101e47f6615c8e390 14-Jul-2009 David Goodwin <david_goodwin@apple.com> hasThumb2() does not mean we are compiling for thumb, must also check isThumb().


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2f297df02eac140de4e2f85e56bd79abf883360c 11-Jul-2009 Evan Cheng <evan.cheng@apple.com> Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.

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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
446c428bf394b7113b0f18cbacb5e87b4efd1e14 11-Jul-2009 Evan Cheng <evan.cheng@apple.com> Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.

A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5c874172ac8fd563867efc54022ac4c1571e1313 10-Jul-2009 Evan Cheng <evan.cheng@apple.com> Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.

Note, we are not yet generating these instructions.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f1daf7d8abebd6e0104a6b41a774ccbb19a51c60 09-Jul-2009 David Goodwin <david_goodwin@apple.com> Use common code for both ARM and Thumb-2 instruction and register info.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e7cbe4118b7ddf05032ff8772a98c51e1637bb5c 08-Jul-2009 Evan Cheng <evan.cheng@apple.com> Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
dac237e18209b697a8ba122d0ddd9cad4dfba1f8 08-Jul-2009 Torok Edwin <edwintorok@gmail.com> Implement changes from Chris's feedback.
Finish converting lib/Target.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e253c951b38e47f14a097db6ac7731c857837ae2 07-Jul-2009 Evan Cheng <evan.cheng@apple.com> Add Thumb2 movcc instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5b9fcd1c8e9f2b7964a82cd383441f568890b561 07-Jul-2009 Evan Cheng <evan.cheng@apple.com> Add some more Thumb2 multiplication instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4fbb9960adcd79888acda1869d26032b9ab44a10 03-Jul-2009 Evan Cheng <evan.cheng@apple.com> Sign extending pre/post indexed loads.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e88d5cee9d6b02bc786df806395a718464908064 02-Jul-2009 Evan Cheng <evan.cheng@apple.com> Thumb2 pre/post indexed loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
af4550f8265885bdf99b3b3f129f3e6fd24a41e5 02-Jul-2009 Evan Cheng <evan.cheng@apple.com> Factor out ARM indexed load matching code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8b024a5eb5b64b482f7d92aad7a3f0e6cac93f12 02-Jul-2009 Bob Wilson <bob.wilson@apple.com> Add a new addressing mode for NEON load/store instructions.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6647cea111ab4d83483b28712b5ba8244e6612f2 01-Jul-2009 David Goodwin <david_goodwin@apple.com> Thumb-2 load and store double description. But nothing yet creates them.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5e47a9a6e46bd271eba058fb831da1a1edf8707c 30-Jun-2009 David Goodwin <david_goodwin@apple.com> Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
055b0310f862b91f33699037ce67d3ab8137c20c 29-Jun-2009 Evan Cheng <evan.cheng@apple.com> Implement Thumb2 ldr.

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.


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/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9cb9e6778c7d458eee7f3e25d304697ad10d8d46 27-Jun-2009 Evan Cheng <evan.cheng@apple.com> Renaming for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d49ea77cbc24776142615fecf75f41e191c765bd 26-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Split thumb-related stuff into separate classes.
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e870af483799beab9ec95adf89047a37e97b301a 23-Jun-2009 Evan Cheng <evan.cheng@apple.com> Code clean up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e499f970585c2462e2de8a38f67f6d11683a6bb0 23-Jun-2009 Evan Cheng <evan.cheng@apple.com> Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5bafff36c798608a189c517d37527e4a38863071 23-Jun-2009 Bob Wilson <bob.wilson@apple.com> Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e64e3cf9adb18c9c6711e69e975d098a513ee8f8 22-Jun-2009 Bob Wilson <bob.wilson@apple.com> Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops
predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73887 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
52237119a9b41d6d714c96e730d651300b171298 17-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Initial support for some Thumb2 instructions.
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
dada95b5b3acbce56440124c242673f30f596f92 09-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Revert hunk commited by accident

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0eebf653a7b2978e7761f8d068b6fbec22aea0f6 09-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
224c244f56025c10e70e4204daceadfb3cdd2c06 19-May-2009 Bob Wilson <bob.wilson@apple.com> Fix pr4091: Add support for "m" constraint in ARM inline assembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
30eae3c02244e18747f9f0dca6946d86d0ccb7f5 07-Apr-2009 Jim Grosbach <grosbach@apple.com> PR2985 / <rdar://problem/6584986>

When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9d7b5309c267048114f1438ec0366923c99ca34d 26-Mar-2009 Evan Cheng <evan.cheng@apple.com> tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8c4d1b2bcfa63d064a7bcbd9cd23ebe3b282f853 12-Feb-2009 Chris Lattner <sabre@nondot.org> fix PR3538 for ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f5f5dce897269885754fc79adeb809194da52942 06-Feb-2009 Dale Johannesen <dalej@apple.com> Eliminate remaining non-DebugLoc version of getTargetNode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f90b2a7742ddeddc448586cc050818a664419e74 06-Feb-2009 Dale Johannesen <dalej@apple.com> get rid of some non-DebugLoc getTargetNode variants.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63909 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ed2eee63a6858312ed17582d8cb85a6856d8eb34 06-Feb-2009 Dale Johannesen <dalej@apple.com> Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
79ce276083ced01256a0eb7d80731e4948ca6e87 15-Jan-2009 Dan Gohman <gohman@apple.com> Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e5ad88e97fea74dd55675fa3ded89f01fb18f363 10-Dec-2008 Evan Cheng <evan.cheng@apple.com> Preliminary ARM debug support based on patch by Mikael of FlexyCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f033b5a393c1f0af68a2e93ef73bf0a3d788ae6e 03-Dec-2008 Dan Gohman <gohman@apple.com> Update a comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8be6bbe5bfd50945ac6c5542e0f54a0924a5db8d 05-Nov-2008 Dan Gohman <gohman@apple.com> Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8ad4c00c00233acb8a3395098e2b575cc34de46b 27-Oct-2008 David Greene <greened@obbligato.org> Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
da8ac5fd9130b70b61be61e4819faa8d842d708f 03-Oct-2008 Dan Gohman <gohman@apple.com> Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3f7eb8eba083677d38cc8c96f00a945399421aaf 18-Sep-2008 Evan Cheng <evan.cheng@apple.com> Cosmetic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f5aeb1a8e4cf272c7348376d185ef8d8267653e0 12-Sep-2008 Dan Gohman <gohman@apple.com> Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ba36cb5242eb02b12b277f82b9efe497f7da4d7f 28-Aug-2008 Gabor Greif <ggreif@gmail.com> erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
99a6cb92d173c142073416c81efe6d3daeb80b49 27-Aug-2008 Gabor Greif <ggreif@gmail.com> disallow direct access to SDValue::ResNo, provide a getter instead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f350b277f32d7d47f86c0e54f4aec4d470500618 23-Aug-2008 Dan Gohman <gohman@apple.com> Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ad3460c3c968e33c5b9a07104b9fe5a5c27ff55b 21-Aug-2008 Dan Gohman <gohman@apple.com> Simplify SelectRoot's interface, and factor out some common code
from all targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
475871a144eb604ddaf37503397ba0941442e5fb 27-Jul-2008 Dan Gohman <gohman@apple.com> Rename SDOperand to SDValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e8be6c63915e0389f1eef6b53c64300d13b2ce99 17-Jul-2008 Dan Gohman <gohman@apple.com> Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1002c0203450620594a85454c6a095ca94b87cb2 07-Jul-2008 Dan Gohman <gohman@apple.com> Add explicit keywords.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
db8d56b825efeb576d67b9dbe39d736d93306222 30-Jun-2008 Evan Cheng <evan.cheng@apple.com> Split scheduling from instruction selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb 06-Jun-2008 Duncan Sands <baldrick@free.fr> Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4e3f5a4e9c13f216856515e6f000881f2c850736 05-Feb-2008 Evan Cheng <evan.cheng@apple.com> Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3d62d780abbe0c2dd8edd7dd37a27365b2032d73 03-Feb-2008 Chris Lattner <sabre@nondot.org> explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a47b9bcbdec16c2fa7cee84e72b5d0a306519a7a 03-Feb-2008 Chris Lattner <sabre@nondot.org> don't do ReplaceUses on a result that doesn't exist.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a844bdeab31ef04221e7ef59a8467893584cc14d 02-Feb-2008 Evan Cheng <evan.cheng@apple.com> SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b625f2f8960de32bc973092aaee8ac62863006fe 30-Jan-2008 Dan Gohman <gohman@apple.com> Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
84bc5427d6883f73cfeae3da640acd011d35c006 31-Dec-2007 Chris Lattner <sabre@nondot.org> Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4ee451de366474b9c228b4e5fa573795a715216d 29-Dec-2007 Chris Lattner <sabre@nondot.org> Remove attribution from file headers, per discussion on llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
525178cdbf00720ea8bce297a7d65b0cca0ab439 08-Oct-2007 Dan Gohman <gohman@apple.com> Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
13ab020ea08826f1b87db6ec3da63889a12e3d9d 10-Jul-2007 Evan Cheng <evan.cheng@apple.com> Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ee568cf7948230b78303b86c92722c177d3a5673 05-Jul-2007 Evan Cheng <evan.cheng@apple.com> Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
44bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4 15-May-2007 Evan Cheng <evan.cheng@apple.com> Add PredicateOperand to all ARM instructions that have the condition field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
72939126d43901e3d922535be4e12ef8ebf31611 03-May-2007 Chris Lattner <sabre@nondot.org> match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5 19-Mar-2007 Evan Cheng <evan.cheng@apple.com> Fix naming inconsistencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
fa775d09c6bb506cf0696e0d688cafcb74955702 19-Mar-2007 Evan Cheng <evan.cheng@apple.com> Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a13fd108f2c77adc60045859f1df4923b59a9d10 13-Mar-2007 Evan Cheng <evan.cheng@apple.com> AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8fdbe560a0bc600121f1f2de10638c7b5d58a47a 07-Feb-2007 Evan Cheng <evan.cheng@apple.com> Get rid of references to iostream.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8c1a73ad3ffbc121a251b93b0fb4e64187f90645 06-Feb-2007 Evan Cheng <evan.cheng@apple.com> Select add FI, c correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ad0e465889d49f423436dc56d50c838df2672133 06-Feb-2007 Evan Cheng <evan.cheng@apple.com> - Store val, [sp, c] must be selected to tSTRsp.
- If c does not fit in the offset field, materialize sp + c into a register
using tADDhirr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
cea117d2de0bfe422641e2ada4fef160e099a6b4 30-Jan-2007 Evan Cheng <evan.cheng@apple.com> Change the operand orders to t_addrmode_s* to make it easier to morph
instructions that use these address modes to instructions that use
t_addrmode_sp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
012f2d97b78e4eb9128f1d491f2c177768dbe527 24-Jan-2007 Evan Cheng <evan.cheng@apple.com> Use PC relative ldr to load from a constantpool in Thumb mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e966d6415ce3a9a6ef113ea4382131f46eb55540 24-Jan-2007 Evan Cheng <evan.cheng@apple.com> Allow [ fi#c, imm ] as ARM load / store addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
79d4326b00e35359d38dd9b616840b27e4fc270e 24-Jan-2007 Evan Cheng <evan.cheng@apple.com> Various Thumb mode load / store isel bug fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c38f2bc3c29337f777c48b33daa8b1d6c76c27bf 23-Jan-2007 Evan Cheng <evan.cheng@apple.com> - Reorg Thumb load / store instructions. Combine each rr and ri pair of
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a8e2989ece6dc46df59b0768184028257f913843 19-Jan-2007 Evan Cheng <evan.cheng@apple.com> ARM backend contribution from Apple.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a38bbf7dd3b824aab6c290aec9e03e5cfdd028f5 12-Jan-2007 Lauro Ramos Venancio <lauro.venancio@gmail.com> Build constants using instructions mov/orr or mvn/eor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ca1f66db0d151a721a18039082afa54f5d454124 04-Jan-2007 Lauro Ramos Venancio <lauro.venancio@gmail.com> Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9985f9f61e1dcffcd28caa2b6a42a1347624158d 31-Dec-2006 Rafael Espindola <rafael.espindola@gmail.com> implement missing compares
patch by Lauro
bug fixed by me


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
47857812e29324a9d1560796a05b53d3a9217fd9 31-Dec-2006 Reid Spencer <rspencer@reidspencer.com> For PR950:
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0cc2bd12d22562acaeb3813250de2fcd30bd9e0e 29-Dec-2006 Rafael Espindola <rafael.espindola@gmail.com> fix comment


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
301009a0fca8dea601d54954eaaa8fae1e055c75 28-Dec-2006 Lauro Ramos Venancio <lauro.venancio@gmail.com> Implement SELECT_CC (f32/f64) for ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8897a7b02e6ccd50bbcb68133e55b54ec8a2e4e0 14-Dec-2006 Rafael Espindola <rafael.espindola@gmail.com> avoid using a constant table when a constant can be used inline


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a898ce687a3a835ae47548101fe847ca17d85f48 12-Dec-2006 Rafael Espindola <rafael.espindola@gmail.com> more general matching of the MVN instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2426775c81b32ab0f12eb15e45001303737060c8 12-Dec-2006 Rafael Espindola <rafael.espindola@gmail.com> don't use "ordinary" addressing mode 1 when mvn is appropriate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f64945d83c61e540a448de0d0d23cda67c92ebe5 12-Dec-2006 Rafael Espindola <rafael.espindola@gmail.com> use MVN to handle small negative constants


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 07-Dec-2006 Bill Wendling <isanbard@gmail.com> What should be the last unnecessary <iostream>s in the library.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
97815c6b9c789ba741106d300f94f0c10ba6d978 05-Dec-2006 Rafael Espindola <rafael.espindola@gmail.com> expand memmove and memcpy


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
462af9a2e0e3667bc35203be2d14086bf14f0a02 05-Dec-2006 Rafael Espindola <rafael.espindola@gmail.com> add support for the "r" asm constraint
patch by Lauro Ramos Venancio


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f819a4999aedd00368c850c1707e7ed0d59b4ace 09-Nov-2006 Rafael Espindola <rafael.espindola@gmail.com> implement load effective address similar to the alpha backend
remove lea_addri and the now unused memri addressing mode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0d53826f3653a789cf1491c3c40a1f4a993992b6 08-Nov-2006 Evan Cheng <evan.cheng@apple.com> Match tblegen changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6e8c6493f0db238d06549368bd647e29ff3c7821 08-Nov-2006 Rafael Espindola <rafael.espindola@gmail.com> initial implementation of addressing mode 2
TODO: fix lea_addri


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e931a37a4eb3e46d73ab0379dd84173dca1214f2 02-Nov-2006 Rafael Espindola <rafael.espindola@gmail.com> move ARMCondCodeToString to ARMAsmPrinter.cpp
remove unused variables from lowerCall


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c35497fc2a8b984dbacede5b75b7be74c6756948 30-Oct-2006 Evan Cheng <evan.cheng@apple.com> All targets expand BR_JT for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362 26-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> initial support for frame pointers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0e5e3aacbe5dc069187b94896f5844f8dfbb44c5 24-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand ISD::VACOPY


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d8ed7f8cde5e56eff4692303af97aa6495c41ca4 23-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand ISD::MEMSET


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b83eb6447ba155342598f0fabe1f08f5baa9164a 20-Oct-2006 Reid Spencer <rspencer@reidspencer.com> For PR950:
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6495bdd8d2702e23092a55bc82446db1768f3cf7 19-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand SIGN_EXTEND_INREG


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4749aa4ea373e2928444974a761e14cf8c3b3f90 19-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand brind so that we don't have to implement jump tables right now


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5f1b698aebbb5bb3dc349d287d5c85ab542860ec 18-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> implement CallingConv::Fast as CallingConv::C


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
226f8bc38c7d1916518602126c7091812265bf6b 17-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
32bd5f4f6a374f9ab0fcbd2cf6a8561019a6fd56 17-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> initial implementation of addressing mode 5


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0505be03adf561afbd8307516125da10dba8f0c4 16-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d2b5668208ac9c699be39408f68f4dee9deb90f0 14-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand ISD::BRCOND


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6c5ae3edd3c32704991793f1ba7703d87df4f06d 14-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> fix some fp condition codes
use non trapping comparison instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8b2794aeff151be8cdbd44786c1d0f94f8f2e427 13-Oct-2006 Evan Cheng <evan.cheng@apple.com> Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
26a76d1024e944669a80dd86bcd0b81d7394a4f5 13-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> implement calls to functions that return long


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
42b62f3f81b0c38954dd64b37cbb3c995f84073c 13-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> implement unordered floating point compares


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
493a7fc5c301faca1f5cd042c5f546bd008c282e 10-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> uint <-> double conversion


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
b47e1d033cd3519d4a50779e07563a8dc2c0a21a 10-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> add double <-> int conversion


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
0d9fe764dfcacf9978680cd8bc91cc27191f8546 10-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> compare doubles


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4b20fbc01d6a298bb3c8c22cb76c33b366c1c1b9 10-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> initial support for fp compares. Unordered compares not implemented yet


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
466685d41a9ea4905b9486fea38e83802e46f196 09-Oct-2006 Evan Cheng <evan.cheng@apple.com> Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
48bc9fbf191057abfa42e26517cef61a241c7516 09-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand ISD::SELECT


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ad557f9d11b942efe858a27e330a15d9f0af5dad 09-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> expand ISD::EXTLOAD


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e5bbd6d75353103f0053af2f6686e70c58abe340 07-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> implement FUITOS and FUITOD


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
935b1f8fce78d1a33251aec02dcd0108b8dd0366 06-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> add optional input flag to FMRRD


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30774 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
614057b843e5b27963095c42042a232e85527f02 06-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> add support for calling functions that return double


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
af1dabef358895da483617b6f5cbd25b60b6f410 06-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> fix some bugs affecting functions with no arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4a408d46d4c2d9a7e5598c9a96886374ca7044f6 06-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> add support for calling functions that have double arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
786225adf09e606c795ef68a1f789c12f37869f2 06-Oct-2006 Evan Cheng <evan.cheng@apple.com> Make use of getStore().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
39b5a2125922810233c0c1fd52a9621a979c8c19 05-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> use a const ref for passing the vector to ArgumentLayout


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a284584352df145da085b11db7891b67c0f09430 05-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
implement FMDRR
add support for f64 function arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
cd71da5cf05cd023d2082e2a13a2524ee7d5af3f 03-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> Implement floating point constants


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9e071f0ae3eb92c61de4860fdb12d4499b50e392 02-Oct-2006 Rafael Espindola <rafael.espindola@gmail.com> fix the names of the 64bit fp register
initial support for returning 64bit floating point numbers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
27185190e6652d4c6d70bdf1202a518e5d3f3053 29-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> add floating point registers
implement SINT_TO_FP


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ebdabda708348d54d86719a1af30e2410b5bcc0a 21-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> more condition codes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7246d33e2a99c3060089e550775403f6779662e7 21-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> if a constant can't be an immediate, add it to the constant pool


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3ad5e5cf998841681e9d11e08eb82a94ddffd1f8 13-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> add shifts to addressing mode 1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c356a572e34131bf767f35e3fecefae36fab744a 12-Sep-2006 Evan Cheng <evan.cheng@apple.com> Reflects MachineConstantPoolEntry changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1b3956b516e28d634e48a12074b94acca5bcc679 11-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7cca7c531773f763c1bddc3fefecc99ba56ed10a 11-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> partial implementation of the ARM Addressing Mode 1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3a02f020eb72cb10f7f794532ddc35e478f7e86b 04-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> add support for returning 64bit values


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
bc4cec9a62113dc7d12caa03f1a1e8a31ce60b9c 03-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> add the SETULT condition code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
5f450d2948ac5bd83a31fbfff89e17b0e2536a80 02-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> add more condition codes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
9ade218533429146731213eacb7e12060e65ff58 26-Aug-2006 Evan Cheng <evan.cheng@apple.com> Select() no longer require Result operand by reference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
755be9b3debb5ffdb21759c0213d51116a522e1b 25-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> use @ for comments
store LR in an arbitrary stack slot
add support for writing varargs functions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
cdda88cd1216c146d9ea095561467a9c83f65908 24-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> add the "eq" condition code
implement a movcond instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6f602de3b68cc63d12554ad6ae3c98a4c436c32d 24-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> create a generic bcond instruction that has a conditional code argument


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
687bc49d1ada3fe0a2cd3fb5c044f12d267f259f 24-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> initial support for branches


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3c000bf817f90212c8e5585f7c1981e68ee393fc 22-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> initial support for select


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3717ca965bcfb6c66d7e9016566be842a9cc5629 20-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> call computeRegisterProperties


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f3a335cedff423438789c593d58be068b124dc1e 17-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> add a "load effective address"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
ec46ea34dcc615558294e9e0dbd0dd0f2894f574 16-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> Declare the callee saved regs
Remove the hard coded store and load of the link register
Implement ARMFrameInfo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
61369da0e5461047adce93f3c3f5ca1ff49707fc 14-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> select code like
ldr rx, [ry, #offset]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
e219945348207453a2d5e21021ba3211f8f94e25 11-Aug-2006 Chris Lattner <sabre@nondot.org> Eliminate use of getNode that takes a vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
8742867f958221d4a8cbbba7eef309bfe037653c 11-Aug-2006 Chris Lattner <sabre@nondot.org> elimiante use of getNode that takes vector of operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
64a752f7c7cf160f2887d0a16d5922359832c9c2 11-Aug-2006 Evan Cheng <evan.cheng@apple.com> Match tablegen changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7a53bd0890b0529c6dd95e97611dca7a8c4d6077 09-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> fix the spill code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1a009468175a6e123cc3f1e847c10e3e126a44db 08-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> initial support for variable number of arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2ef88a09b71f458ad415b35a1fb431c3d15d7eb1 08-Aug-2006 Evan Cheng <evan.cheng@apple.com> Match tablegen isel changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
341b864c8d3868a17d5dbcdb4bac40c6586b60cf 04-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> use a 'register pressure reducing' scheduler
make sure only one move is used in a hello world


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6312da0fc7b5cbefba2243775ed9de5c405274be 04-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> Bug fix: always generate a RET_FLAG in LowerRET
fixes ret_null.ll and call.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
f4fda804038e8f98b597e82a8df607321369db2b 03-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> add and use ARMISD::RET_FLAG


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
06c1e7eacb11edd1671eabfc11291b7716be2608 01-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> implement LowerConstantPool and LowerGlobalAddress


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
2641cad180e94c0d26630d4ed455352f19be3d3e 28-Jul-2006 Evan Cheng <evan.cheng@apple.com> Remove InFlightSet hack. No longer needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
fac00a93a98d43ac0d4ca514aa5a720debbd6c8b 25-Jul-2006 Rafael Espindola <rafael.espindola@gmail.com> implement function calling of functions with up to 4 arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
84b19be6ab9544f72eafb11048a1121f5ea77c95 16-Jul-2006 Rafael Espindola <rafael.espindola@gmail.com> skeleton of a lowerCall implementation for ARM


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
a4e64359aafaf23e440e9dc171859daef1995f1b 11-Jul-2006 Rafael Espindola <rafael.espindola@gmail.com> add the memri memory operand
this makes it possible for ldr instructions with non-zero immediate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
aefe14299a05621864e6372639f372173a96bf38 10-Jul-2006 Rafael Espindola <rafael.espindola@gmail.com> create the raddr addressing mode that matches any register and the frame index
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
49e441558760cc1708778b5d0ded05d639c1e5ed 27-Jun-2006 Rafael Espindola <rafael.espindola@gmail.com> handle the "mov reg1, reg2" case in isMoveInstr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
337c4ad6e7726555b61a6a75d5172a77fe12c029 12-Jun-2006 Rafael Espindola <rafael.espindola@gmail.com> lower more then 4 formal arguments. The offset is currently hard coded.
implement SelectFrameIndex


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4b02367d542c7eaa429d1ff73119ae44ddb252a8 06-Jun-2006 Rafael Espindola <rafael.espindola@gmail.com> add R0 to liveout
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
85ede37ca90b5d1846f37631ed2e8b8f96000db8 30-May-2006 Rafael Espindola <rafael.espindola@gmail.com> Expand ret into "CopyToReg;BRIND"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28559 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6848be1a27e08a89dcd4dd69f746471a608012cd 27-May-2006 Evan Cheng <evan.cheng@apple.com> Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
c3c1a86aa0fe3ccda2de383330b90b77aaccd710 25-May-2006 Rafael Espindola <rafael.espindola@gmail.com> port the ARM backend to use ISD::CALL instead of LowerCallTo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
6a3d5a62f09d4093468525a07a0143cae0e9df41 25-May-2006 Evan Cheng <evan.cheng@apple.com> Assert if InflightSet is not cleared after instruction selecting a BB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
afe358e7d46da9d29ba02fbbf81bdfb4ac4a4520 24-May-2006 Evan Cheng <evan.cheng@apple.com> Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
non-deterministic behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
d74ea2bbd8bb630331f35ead42d385249bd42af8 24-May-2006 Chris Lattner <sabre@nondot.org> Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
4b442b528a50ef06cd75f0e7c41ad57426175bcc 23-May-2006 Rafael Espindola <rafael.espindola@gmail.com> implement minimal versions of
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
dc124a234a02ea6fc1061a51ade1bb7b817ddb61 18-May-2006 Rafael Espindola <rafael.espindola@gmail.com> implement movri
add a stub LowerFORMAL_ARGUMENTS


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1c8f0536b3a19c0ff9f5a8ba039a771c4bb2bfbc 16-May-2006 Rafael Espindola <rafael.espindola@gmail.com> add an abort after every assert(0)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
7bc59bc3952ad7842b1e079753deb32217a768a3 15-May-2006 Rafael Espindola <rafael.espindola@gmail.com> added a skeleton of the ARM backend


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp