ARMISelDAGToDAG.cpp revision 32bd5f4f6a374f9ab0fcbd2cf6a8561019a6fd56
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the ARM target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMTargetMachine.h" 16#include "llvm/CallingConv.h" 17#include "llvm/DerivedTypes.h" 18#include "llvm/Function.h" 19#include "llvm/Constants.h" 20#include "llvm/Intrinsics.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/SelectionDAGISel.h" 26#include "llvm/CodeGen/SSARegMap.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Support/Debug.h" 29#include <iostream> 30#include <vector> 31using namespace llvm; 32 33namespace { 34 class ARMTargetLowering : public TargetLowering { 35 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 36 public: 37 ARMTargetLowering(TargetMachine &TM); 38 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 39 virtual const char *getTargetNodeName(unsigned Opcode) const; 40 }; 41 42} 43 44ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 45 : TargetLowering(TM) { 46 addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass); 47 addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass); 48 addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass); 49 50 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 51 52 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 53 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 54 55 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 56 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 57 58 setOperationAction(ISD::RET, MVT::Other, Custom); 59 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 60 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 61 62 setOperationAction(ISD::SELECT, MVT::i32, Expand); 63 64 setOperationAction(ISD::SETCC, MVT::i32, Expand); 65 setOperationAction(ISD::SETCC, MVT::f32, Expand); 66 setOperationAction(ISD::SETCC, MVT::f64, Expand); 67 68 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 69 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 70 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 71 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 72 73 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 74 75 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 76 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 77 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 78 79 setOperationAction(ISD::VASTART, MVT::Other, Custom); 80 setOperationAction(ISD::VAEND, MVT::Other, Expand); 81 82 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 83 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 84 85 setSchedulingPreference(SchedulingForRegPressure); 86 computeRegisterProperties(); 87} 88 89namespace llvm { 90 namespace ARMISD { 91 enum NodeType { 92 // Start the numbering where the builting ops and target ops leave off. 93 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END, 94 /// CALL - A direct function call. 95 CALL, 96 97 /// Return with a flag operand. 98 RET_FLAG, 99 100 CMP, 101 102 SELECT, 103 104 BR, 105 106 FSITOS, 107 FTOSIS, 108 109 FSITOD, 110 FTOSID, 111 112 FUITOS, 113 FTOUIS, 114 115 FUITOD, 116 FTOUID, 117 118 FMRRD, 119 120 FMDRR, 121 122 FMSTAT 123 }; 124 } 125} 126 127/// DAGFPCCToARMCC - Convert a DAG fp condition code to an ARM CC 128// Unordered = !N & !Z & C & V = V 129// Ordered = N | Z | !C | !V = N | Z | !V 130static ARMCC::CondCodes DAGFPCCToARMCC(ISD::CondCode CC) { 131 switch (CC) { 132 default: 133 assert(0 && "Unknown fp condition code!"); 134// SETOEQ = (N | Z | !V) & Z = Z = EQ 135 case ISD::SETEQ: 136 case ISD::SETOEQ: return ARMCC::EQ; 137// SETOGT = (N | Z | !V) & !N & !Z = !V &!N &!Z = (N = V) & !Z = GT 138 case ISD::SETGT: 139 case ISD::SETOGT: return ARMCC::GT; 140// SETOGE = (N | Z | !V) & !N = (Z | !V) & !N = !V & !N = GE 141 case ISD::SETGE: 142 case ISD::SETOGE: return ARMCC::GE; 143// SETOLT = (N | Z | !V) & N = N = MI 144 case ISD::SETLT: 145 case ISD::SETOLT: return ARMCC::MI; 146// SETOLE = (N | Z | !V) & (N | Z) = N | Z = !C | Z = LS 147 case ISD::SETLE: 148 case ISD::SETOLE: return ARMCC::LS; 149// SETONE = (N | Z | !V) & !Z = (N | !V) & Z = !V & Z = Z = NE 150 case ISD::SETNE: 151 case ISD::SETONE: return ARMCC::NE; 152// SETO = N | Z | !V = Z | !V = !V = VC 153 case ISD::SETO: return ARMCC::VC; 154// SETUO = V = VS 155 case ISD::SETUO: return ARMCC::VS; 156// SETUEQ = V | Z = ?? 157// SETUGT = V | (!Z & !N) = !Z & !N = !Z & C = HI 158 case ISD::SETUGT: return ARMCC::HI; 159// SETUGE = V | !N = !N = PL 160 case ISD::SETUGE: return ARMCC::PL; 161// SETULT = V | N = ?? 162// SETULE = V | Z | N = ?? 163// SETUNE = V | !Z = !Z = NE 164 case ISD::SETUNE: return ARMCC::NE; 165 } 166} 167 168/// DAGIntCCToARMCC - Convert a DAG integer condition code to an ARM CC 169static ARMCC::CondCodes DAGIntCCToARMCC(ISD::CondCode CC) { 170 switch (CC) { 171 default: 172 assert(0 && "Unknown integer condition code!"); 173 case ISD::SETEQ: return ARMCC::EQ; 174 case ISD::SETNE: return ARMCC::NE; 175 case ISD::SETLT: return ARMCC::LT; 176 case ISD::SETLE: return ARMCC::LE; 177 case ISD::SETGT: return ARMCC::GT; 178 case ISD::SETGE: return ARMCC::GE; 179 case ISD::SETULT: return ARMCC::CC; 180 case ISD::SETULE: return ARMCC::LS; 181 case ISD::SETUGT: return ARMCC::HI; 182 case ISD::SETUGE: return ARMCC::CS; 183 } 184} 185 186const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 187 switch (Opcode) { 188 default: return 0; 189 case ARMISD::CALL: return "ARMISD::CALL"; 190 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 191 case ARMISD::SELECT: return "ARMISD::SELECT"; 192 case ARMISD::CMP: return "ARMISD::CMP"; 193 case ARMISD::BR: return "ARMISD::BR"; 194 case ARMISD::FSITOS: return "ARMISD::FSITOS"; 195 case ARMISD::FTOSIS: return "ARMISD::FTOSIS"; 196 case ARMISD::FSITOD: return "ARMISD::FSITOD"; 197 case ARMISD::FTOSID: return "ARMISD::FTOSID"; 198 case ARMISD::FUITOS: return "ARMISD::FUITOS"; 199 case ARMISD::FTOUIS: return "ARMISD::FTOUIS"; 200 case ARMISD::FUITOD: return "ARMISD::FUITOD"; 201 case ARMISD::FTOUID: return "ARMISD::FTOUID"; 202 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 203 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 204 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 205 } 206} 207 208class ArgumentLayout { 209 std::vector<bool> is_reg; 210 std::vector<unsigned> pos; 211 std::vector<MVT::ValueType> types; 212public: 213 ArgumentLayout(const std::vector<MVT::ValueType> &Types) { 214 types = Types; 215 216 unsigned RegNum = 0; 217 unsigned StackOffset = 0; 218 for(std::vector<MVT::ValueType>::const_iterator I = Types.begin(); 219 I != Types.end(); 220 ++I) { 221 MVT::ValueType VT = *I; 222 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64); 223 unsigned size = MVT::getSizeInBits(VT)/32; 224 225 RegNum = ((RegNum + size - 1) / size) * size; 226 if (RegNum < 4) { 227 pos.push_back(RegNum); 228 is_reg.push_back(true); 229 RegNum += size; 230 } else { 231 unsigned bytes = size * 32/8; 232 StackOffset = ((StackOffset + bytes - 1) / bytes) * bytes; 233 pos.push_back(StackOffset); 234 is_reg.push_back(false); 235 StackOffset += bytes; 236 } 237 } 238 } 239 unsigned getRegisterNum(unsigned argNum) { 240 assert(isRegister(argNum)); 241 return pos[argNum]; 242 } 243 unsigned getOffset(unsigned argNum) { 244 assert(isOffset(argNum)); 245 return pos[argNum]; 246 } 247 unsigned isRegister(unsigned argNum) { 248 assert(argNum < is_reg.size()); 249 return is_reg[argNum]; 250 } 251 unsigned isOffset(unsigned argNum) { 252 return !isRegister(argNum); 253 } 254 MVT::ValueType getType(unsigned argNum) { 255 assert(argNum < types.size()); 256 return types[argNum]; 257 } 258 unsigned getStackSize(void) { 259 int last = is_reg.size() - 1; 260 if (last < 0) 261 return 0; 262 if (isRegister(last)) 263 return 0; 264 return getOffset(last) + MVT::getSizeInBits(getType(last))/8; 265 } 266 int lastRegArg(void) { 267 int size = is_reg.size(); 268 int last = 0; 269 while(last < size && isRegister(last)) 270 last++; 271 last--; 272 return last; 273 } 274 int lastRegNum(void) { 275 int l = lastRegArg(); 276 if (l < 0) 277 return -1; 278 unsigned r = getRegisterNum(l); 279 MVT::ValueType t = getType(l); 280 assert(t == MVT::i32 || t == MVT::f32 || t == MVT::f64); 281 if (t == MVT::f64) 282 return r + 1; 283 return r; 284 } 285}; 286 287// This transforms a ISD::CALL node into a 288// callseq_star <- ARMISD:CALL <- callseq_end 289// chain 290static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { 291 SDOperand Chain = Op.getOperand(0); 292 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 293 assert(CallConv == CallingConv::C && "unknown calling convention"); 294 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 295 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 296 SDOperand Callee = Op.getOperand(4); 297 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 298 SDOperand StackPtr = DAG.getRegister(ARM::R13, MVT::i32); 299 static const unsigned regs[] = { 300 ARM::R0, ARM::R1, ARM::R2, ARM::R3 301 }; 302 303 std::vector<MVT::ValueType> Types; 304 for (unsigned i = 0; i < NumOps; ++i) { 305 MVT::ValueType VT = Op.getOperand(5+2*i).getValueType(); 306 Types.push_back(VT); 307 } 308 ArgumentLayout Layout(Types); 309 310 unsigned NumBytes = Layout.getStackSize(); 311 312 Chain = DAG.getCALLSEQ_START(Chain, 313 DAG.getConstant(NumBytes, MVT::i32)); 314 315 //Build a sequence of stores 316 std::vector<SDOperand> MemOpChains; 317 for (unsigned i = Layout.lastRegArg() + 1; i < NumOps; ++i) { 318 SDOperand Arg = Op.getOperand(5+2*i); 319 unsigned ArgOffset = Layout.getOffset(i); 320 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 321 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 322 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 323 } 324 if (!MemOpChains.empty()) 325 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 326 &MemOpChains[0], MemOpChains.size()); 327 328 // If the callee is a GlobalAddress node (quite common, every direct call is) 329 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 330 // Likewise ExternalSymbol -> TargetExternalSymbol. 331 assert(Callee.getValueType() == MVT::i32); 332 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 333 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 334 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 335 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 336 337 // If this is a direct call, pass the chain and the callee. 338 assert (Callee.Val); 339 std::vector<SDOperand> Ops; 340 Ops.push_back(Chain); 341 Ops.push_back(Callee); 342 343 // Build a sequence of copy-to-reg nodes chained together with token chain 344 // and flag operands which copy the outgoing args into the appropriate regs. 345 SDOperand InFlag; 346 for (int i = 0, e = Layout.lastRegArg(); i <= e; ++i) { 347 SDOperand Arg = Op.getOperand(5+2*i); 348 unsigned RegNum = Layout.getRegisterNum(i); 349 unsigned Reg1 = regs[RegNum]; 350 MVT::ValueType VT = Layout.getType(i); 351 assert(VT == Arg.getValueType()); 352 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64); 353 354 // Add argument register to the end of the list so that it is known live 355 // into the call. 356 Ops.push_back(DAG.getRegister(Reg1, MVT::i32)); 357 if (VT == MVT::f64) { 358 unsigned Reg2 = regs[RegNum + 1]; 359 SDOperand SDReg1 = DAG.getRegister(Reg1, MVT::i32); 360 SDOperand SDReg2 = DAG.getRegister(Reg2, MVT::i32); 361 362 Ops.push_back(DAG.getRegister(Reg2, MVT::i32)); 363 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 364 SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg, InFlag}; 365 Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, InFlag.Val ? 5 : 4); 366 } else { 367 if (VT == MVT::f32) 368 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg); 369 Chain = DAG.getCopyToReg(Chain, Reg1, Arg, InFlag); 370 } 371 InFlag = Chain.getValue(1); 372 } 373 374 std::vector<MVT::ValueType> NodeTys; 375 NodeTys.push_back(MVT::Other); // Returns a chain 376 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 377 378 unsigned CallOpc = ARMISD::CALL; 379 if (InFlag.Val) 380 Ops.push_back(InFlag); 381 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 382 InFlag = Chain.getValue(1); 383 384 std::vector<SDOperand> ResultVals; 385 NodeTys.clear(); 386 387 // If the call has results, copy the values out of the ret val registers. 388 MVT::ValueType VT = Op.Val->getValueType(0); 389 if (VT != MVT::Other) { 390 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64); 391 392 SDOperand Value1 = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 393 Chain = Value1.getValue(1); 394 InFlag = Value1.getValue(2); 395 NodeTys.push_back(VT); 396 if (VT == MVT::i32) { 397 ResultVals.push_back(Value1); 398 if (Op.Val->getValueType(1) == MVT::i32) { 399 SDOperand Value2 = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, InFlag); 400 Chain = Value2.getValue(1); 401 ResultVals.push_back(Value2); 402 NodeTys.push_back(VT); 403 } 404 } 405 if (VT == MVT::f32) { 406 SDOperand Value = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Value1); 407 ResultVals.push_back(Value); 408 } 409 if (VT == MVT::f64) { 410 SDOperand Value2 = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, InFlag); 411 Chain = Value2.getValue(1); 412 SDOperand Value = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2); 413 ResultVals.push_back(Value); 414 } 415 } 416 417 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 418 DAG.getConstant(NumBytes, MVT::i32)); 419 NodeTys.push_back(MVT::Other); 420 421 if (ResultVals.empty()) 422 return Chain; 423 424 ResultVals.push_back(Chain); 425 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], 426 ResultVals.size()); 427 return Res.getValue(Op.ResNo); 428} 429 430static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 431 SDOperand Copy; 432 SDOperand Chain = Op.getOperand(0); 433 SDOperand R0 = DAG.getRegister(ARM::R0, MVT::i32); 434 SDOperand R1 = DAG.getRegister(ARM::R1, MVT::i32); 435 436 switch(Op.getNumOperands()) { 437 default: 438 assert(0 && "Do not know how to return this many arguments!"); 439 abort(); 440 case 1: { 441 SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32); 442 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 443 } 444 case 3: { 445 SDOperand Val = Op.getOperand(1); 446 assert(Val.getValueType() == MVT::i32 || 447 Val.getValueType() == MVT::f32 || 448 Val.getValueType() == MVT::f64); 449 450 if (Val.getValueType() == MVT::f64) { 451 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 452 SDOperand Ops[] = {Chain, R0, R1, Val}; 453 Copy = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4); 454 } else { 455 if (Val.getValueType() == MVT::f32) 456 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 457 Copy = DAG.getCopyToReg(Chain, R0, Val, SDOperand()); 458 } 459 460 if (DAG.getMachineFunction().liveout_empty()) { 461 DAG.getMachineFunction().addLiveOut(ARM::R0); 462 if (Val.getValueType() == MVT::f64) 463 DAG.getMachineFunction().addLiveOut(ARM::R1); 464 } 465 break; 466 } 467 case 5: 468 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); 469 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 470 // If we haven't noted the R0+R1 are live out, do so now. 471 if (DAG.getMachineFunction().liveout_empty()) { 472 DAG.getMachineFunction().addLiveOut(ARM::R0); 473 DAG.getMachineFunction().addLiveOut(ARM::R1); 474 } 475 break; 476 } 477 478 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 479 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 480} 481 482static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 483 MVT::ValueType PtrVT = Op.getValueType(); 484 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 485 Constant *C = CP->getConstVal(); 486 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 487 488 return CPI; 489} 490 491static SDOperand LowerGlobalAddress(SDOperand Op, 492 SelectionDAG &DAG) { 493 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 494 int alignment = 2; 495 SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment); 496 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr, NULL, 0); 497} 498 499static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 500 unsigned VarArgsFrameIndex) { 501 // vastart just stores the address of the VarArgsFrameIndex slot into the 502 // memory location argument. 503 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 504 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 505 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 506 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 507 SV->getOffset()); 508} 509 510static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 511 int &VarArgsFrameIndex) { 512 MachineFunction &MF = DAG.getMachineFunction(); 513 MachineFrameInfo *MFI = MF.getFrameInfo(); 514 SSARegMap *RegMap = MF.getSSARegMap(); 515 unsigned NumArgs = Op.Val->getNumValues()-1; 516 SDOperand Root = Op.getOperand(0); 517 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 518 static const unsigned REGS[] = { 519 ARM::R0, ARM::R1, ARM::R2, ARM::R3 520 }; 521 522 std::vector<MVT::ValueType> Types(Op.Val->value_begin(), Op.Val->value_end() - 1); 523 ArgumentLayout Layout(Types); 524 525 std::vector<SDOperand> ArgValues; 526 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) { 527 MVT::ValueType VT = Types[ArgNo]; 528 529 SDOperand Value; 530 if (Layout.isRegister(ArgNo)) { 531 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64); 532 unsigned RegNum = Layout.getRegisterNum(ArgNo); 533 unsigned Reg1 = REGS[RegNum]; 534 unsigned VReg1 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass); 535 SDOperand Value1 = DAG.getCopyFromReg(Root, VReg1, MVT::i32); 536 MF.addLiveIn(Reg1, VReg1); 537 if (VT == MVT::f64) { 538 unsigned Reg2 = REGS[RegNum + 1]; 539 unsigned VReg2 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass); 540 SDOperand Value2 = DAG.getCopyFromReg(Root, VReg2, MVT::i32); 541 MF.addLiveIn(Reg2, VReg2); 542 Value = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2); 543 } else { 544 Value = Value1; 545 if (VT == MVT::f32) 546 Value = DAG.getNode(ISD::BIT_CONVERT, VT, Value); 547 } 548 } else { 549 // If the argument is actually used, emit a load from the right stack 550 // slot. 551 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 552 unsigned Offset = Layout.getOffset(ArgNo); 553 unsigned Size = MVT::getSizeInBits(VT)/8; 554 int FI = MFI->CreateFixedObject(Size, Offset); 555 SDOperand FIN = DAG.getFrameIndex(FI, VT); 556 Value = DAG.getLoad(VT, Root, FIN, NULL, 0); 557 } else { 558 Value = DAG.getNode(ISD::UNDEF, VT); 559 } 560 } 561 ArgValues.push_back(Value); 562 } 563 564 unsigned NextRegNum = Layout.lastRegNum() + 1; 565 566 if (isVarArg) { 567 //If this function is vararg we must store the remaing 568 //registers so that they can be acessed with va_start 569 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8, 570 -16 + NextRegNum * 4); 571 572 SmallVector<SDOperand, 4> MemOps; 573 for (unsigned RegNo = NextRegNum; RegNo < 4; ++RegNo) { 574 int RegOffset = - (4 - RegNo) * 4; 575 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8, 576 RegOffset); 577 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 578 579 unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass); 580 MF.addLiveIn(REGS[RegNo], VReg); 581 582 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 583 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 584 MemOps.push_back(Store); 585 } 586 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 587 } 588 589 ArgValues.push_back(Root); 590 591 // Return the new list of results. 592 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 593 Op.Val->value_end()); 594 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 595} 596 597static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS, 598 SelectionDAG &DAG) { 599 MVT::ValueType vt = LHS.getValueType(); 600 assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64); 601 602 SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS); 603 604 if (vt != MVT::i32) 605 Cmp = DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 606 return Cmp; 607} 608 609static SDOperand GetARMCC(ISD::CondCode CC, MVT::ValueType vt, 610 SelectionDAG &DAG) { 611 assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64); 612 if (vt == MVT::i32) 613 return DAG.getConstant(DAGIntCCToARMCC(CC), MVT::i32); 614 else 615 return DAG.getConstant(DAGFPCCToARMCC(CC), MVT::i32); 616} 617 618static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 619 SDOperand LHS = Op.getOperand(0); 620 SDOperand RHS = Op.getOperand(1); 621 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 622 SDOperand TrueVal = Op.getOperand(2); 623 SDOperand FalseVal = Op.getOperand(3); 624 SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG); 625 SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG); 626 return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp); 627} 628 629static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { 630 SDOperand Chain = Op.getOperand(0); 631 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 632 SDOperand LHS = Op.getOperand(2); 633 SDOperand RHS = Op.getOperand(3); 634 SDOperand Dest = Op.getOperand(4); 635 SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG); 636 SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG); 637 return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp); 638} 639 640static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 641 SDOperand IntVal = Op.getOperand(0); 642 assert(IntVal.getValueType() == MVT::i32); 643 MVT::ValueType vt = Op.getValueType(); 644 assert(vt == MVT::f32 || 645 vt == MVT::f64); 646 647 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal); 648 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FSITOS : ARMISD::FSITOD; 649 return DAG.getNode(op, vt, Tmp); 650} 651 652static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 653 assert(Op.getValueType() == MVT::i32); 654 SDOperand FloatVal = Op.getOperand(0); 655 MVT::ValueType vt = FloatVal.getValueType(); 656 assert(vt == MVT::f32 || vt == MVT::f64); 657 658 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOSIS : ARMISD::FTOSID; 659 SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal); 660 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp); 661} 662 663static SDOperand LowerUINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 664 SDOperand IntVal = Op.getOperand(0); 665 assert(IntVal.getValueType() == MVT::i32); 666 MVT::ValueType vt = Op.getValueType(); 667 assert(vt == MVT::f32 || 668 vt == MVT::f64); 669 670 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal); 671 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FUITOS : ARMISD::FUITOD; 672 return DAG.getNode(op, vt, Tmp); 673} 674 675static SDOperand LowerFP_TO_UINT(SDOperand Op, SelectionDAG &DAG) { 676 assert(Op.getValueType() == MVT::i32); 677 SDOperand FloatVal = Op.getOperand(0); 678 MVT::ValueType vt = FloatVal.getValueType(); 679 assert(vt == MVT::f32 || vt == MVT::f64); 680 681 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOUIS : ARMISD::FTOUID; 682 SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal); 683 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp); 684} 685 686SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 687 switch (Op.getOpcode()) { 688 default: 689 assert(0 && "Should not custom lower this!"); 690 abort(); 691 case ISD::ConstantPool: 692 return LowerConstantPool(Op, DAG); 693 case ISD::GlobalAddress: 694 return LowerGlobalAddress(Op, DAG); 695 case ISD::FP_TO_SINT: 696 return LowerFP_TO_SINT(Op, DAG); 697 case ISD::SINT_TO_FP: 698 return LowerSINT_TO_FP(Op, DAG); 699 case ISD::FP_TO_UINT: 700 return LowerFP_TO_UINT(Op, DAG); 701 case ISD::UINT_TO_FP: 702 return LowerUINT_TO_FP(Op, DAG); 703 case ISD::FORMAL_ARGUMENTS: 704 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex); 705 case ISD::CALL: 706 return LowerCALL(Op, DAG); 707 case ISD::RET: 708 return LowerRET(Op, DAG); 709 case ISD::SELECT_CC: 710 return LowerSELECT_CC(Op, DAG); 711 case ISD::BR_CC: 712 return LowerBR_CC(Op, DAG); 713 case ISD::VASTART: 714 return LowerVASTART(Op, DAG, VarArgsFrameIndex); 715 } 716} 717 718//===----------------------------------------------------------------------===// 719// Instruction Selector Implementation 720//===----------------------------------------------------------------------===// 721 722//===--------------------------------------------------------------------===// 723/// ARMDAGToDAGISel - ARM specific code to select ARM machine 724/// instructions for SelectionDAG operations. 725/// 726namespace { 727class ARMDAGToDAGISel : public SelectionDAGISel { 728 ARMTargetLowering Lowering; 729 730public: 731 ARMDAGToDAGISel(TargetMachine &TM) 732 : SelectionDAGISel(Lowering), Lowering(TM) { 733 } 734 735 SDNode *Select(SDOperand Op); 736 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 737 bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base); 738 bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift, 739 SDOperand &ShiftType); 740 bool SelectAddrMode5(SDOperand N, SDOperand &Arg, SDOperand &Offset); 741 742 // Include the pieces autogenerated from the target description. 743#include "ARMGenDAGISel.inc" 744}; 745 746void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 747 DEBUG(BB->dump()); 748 749 DAG.setRoot(SelectRoot(DAG.getRoot())); 750 DAG.RemoveDeadNodes(); 751 752 ScheduleAndEmitDAG(DAG); 753} 754 755static bool isInt12Immediate(SDNode *N, short &Imm) { 756 if (N->getOpcode() != ISD::Constant) 757 return false; 758 759 int32_t t = cast<ConstantSDNode>(N)->getValue(); 760 int max = 1<<12; 761 int min = -max; 762 if (t > min && t < max) { 763 Imm = t; 764 return true; 765 } 766 else 767 return false; 768} 769 770static bool isInt12Immediate(SDOperand Op, short &Imm) { 771 return isInt12Immediate(Op.Val, Imm); 772} 773 774static uint32_t rotateL(uint32_t x) { 775 uint32_t bit31 = (x & (1 << 31)) >> 31; 776 uint32_t t = x << 1; 777 return t | bit31; 778} 779 780static bool isUInt8Immediate(uint32_t x) { 781 return x < (1 << 8); 782} 783 784static bool isRotInt8Immediate(uint32_t x) { 785 int r; 786 for (r = 0; r < 16; r++) { 787 if (isUInt8Immediate(x)) 788 return true; 789 x = rotateL(rotateL(x)); 790 } 791 return false; 792} 793 794bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N, 795 SDOperand &Arg, 796 SDOperand &Shift, 797 SDOperand &ShiftType) { 798 switch(N.getOpcode()) { 799 case ISD::Constant: { 800 uint32_t val = cast<ConstantSDNode>(N)->getValue(); 801 if(!isRotInt8Immediate(val)) { 802 const Type *t = MVT::getTypeForValueType(MVT::i32); 803 Constant *C = ConstantUInt::get(t, val); 804 int alignment = 2; 805 SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment); 806 SDOperand Z = CurDAG->getTargetConstant(0, MVT::i32); 807 SDNode *n = CurDAG->getTargetNode(ARM::ldr, MVT::i32, Z, Addr); 808 Arg = SDOperand(n, 0); 809 } else 810 Arg = CurDAG->getTargetConstant(val, MVT::i32); 811 812 Shift = CurDAG->getTargetConstant(0, MVT::i32); 813 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32); 814 return true; 815 } 816 case ISD::SRA: 817 Arg = N.getOperand(0); 818 Shift = N.getOperand(1); 819 ShiftType = CurDAG->getTargetConstant(ARMShift::ASR, MVT::i32); 820 return true; 821 case ISD::SRL: 822 Arg = N.getOperand(0); 823 Shift = N.getOperand(1); 824 ShiftType = CurDAG->getTargetConstant(ARMShift::LSR, MVT::i32); 825 return true; 826 case ISD::SHL: 827 Arg = N.getOperand(0); 828 Shift = N.getOperand(1); 829 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32); 830 return true; 831 } 832 833 Arg = N; 834 Shift = CurDAG->getTargetConstant(0, MVT::i32); 835 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32); 836 return true; 837} 838 839bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand N, SDOperand &Arg, 840 SDOperand &Offset) { 841 //TODO: detect offset 842 Offset = CurDAG->getTargetConstant(0, MVT::i32); 843 Arg = N; 844 return true; 845} 846 847//register plus/minus 12 bit offset 848bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset, 849 SDOperand &Base) { 850 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) { 851 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 852 Offset = CurDAG->getTargetConstant(0, MVT::i32); 853 return true; 854 } 855 if (N.getOpcode() == ISD::ADD) { 856 short imm = 0; 857 if (isInt12Immediate(N.getOperand(1), imm)) { 858 Offset = CurDAG->getTargetConstant(imm, MVT::i32); 859 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 860 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); 861 } else { 862 Base = N.getOperand(0); 863 } 864 return true; // [r+i] 865 } 866 } 867 868 Offset = CurDAG->getTargetConstant(0, MVT::i32); 869 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) { 870 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); 871 } 872 else 873 Base = N; 874 return true; //any address fits in a register 875} 876 877SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { 878 SDNode *N = Op.Val; 879 880 switch (N->getOpcode()) { 881 default: 882 return SelectCode(Op); 883 break; 884 } 885 return NULL; 886} 887 888} // end anonymous namespace 889 890/// createARMISelDag - This pass converts a legalized DAG into a 891/// ARM-specific DAG, ready for instruction scheduling. 892/// 893FunctionPass *llvm::createARMISelDag(TargetMachine &TM) { 894 return new ARMDAGToDAGISel(TM); 895} 896