ARMISelDAGToDAG.cpp revision 2bdffe488203a08a2ca98548a157e0eaf39d4b2d 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMTargetMachine.h"
18#include "MCTargetDesc/ARMAddressingModes.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static cl::opt<bool>
41DisableShifterOp("disable-shifter-op", cl::Hidden,
42  cl::desc("Disable isel of shifter-op"),
43  cl::init(false));
44
45static cl::opt<bool>
46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47  cl::desc("Check fp vmla / vmls hazard at isel time"),
48  cl::init(true));
49
50//===--------------------------------------------------------------------===//
51/// ARMDAGToDAGISel - ARM specific code to select ARM machine
52/// instructions for SelectionDAG operations.
53///
54namespace {
55
56enum AddrMode2Type {
57  AM2_BASE, // Simple AM2 (+-imm12)
58  AM2_SHOP  // Shifter-op AM2
59};
60
61class ARMDAGToDAGISel : public SelectionDAGISel {
62  ARMBaseTargetMachine &TM;
63  const ARMBaseInstrInfo *TII;
64
65  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66  /// make the right decision when generating code for different targets.
67  const ARMSubtarget *Subtarget;
68
69public:
70  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71                           CodeGenOpt::Level OptLevel)
72    : SelectionDAGISel(tm, OptLevel), TM(tm),
73      TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
74      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
75  }
76
77  virtual const char *getPassName() const {
78    return "ARM Instruction Selection";
79  }
80
81  /// getI32Imm - Return a target constant of type i32 with the specified
82  /// value.
83  inline SDValue getI32Imm(unsigned Imm) {
84    return CurDAG->getTargetConstant(Imm, MVT::i32);
85  }
86
87  SDNode *Select(SDNode *N);
88
89
90  bool hasNoVMLxHazardUse(SDNode *N) const;
91  bool isShifterOpProfitable(const SDValue &Shift,
92                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93  bool SelectRegShifterOperand(SDValue N, SDValue &A,
94                               SDValue &B, SDValue &C,
95                               bool CheckProfitability = true);
96  bool SelectImmShifterOperand(SDValue N, SDValue &A,
97                               SDValue &B, bool CheckProfitability = true);
98  bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
99                                    SDValue &B, SDValue &C) {
100    // Don't apply the profitability check
101    return SelectRegShifterOperand(N, A, B, C, false);
102  }
103  bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
104                                    SDValue &B) {
105    // Don't apply the profitability check
106    return SelectImmShifterOperand(N, A, B, false);
107  }
108
109  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
110  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
111
112  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
113                                      SDValue &Offset, SDValue &Opc);
114  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
115                           SDValue &Opc) {
116    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
117  }
118
119  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
120                           SDValue &Opc) {
121    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
122  }
123
124  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
125                       SDValue &Opc) {
126    SelectAddrMode2Worker(N, Base, Offset, Opc);
127//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
128    // This always matches one way or another.
129    return true;
130  }
131
132  bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
133                             SDValue &Offset, SDValue &Opc);
134  bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
135                             SDValue &Offset, SDValue &Opc);
136  bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
137                             SDValue &Offset, SDValue &Opc);
138  bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
139  bool SelectAddrMode3(SDValue N, SDValue &Base,
140                       SDValue &Offset, SDValue &Opc);
141  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
142                             SDValue &Offset, SDValue &Opc);
143  bool SelectAddrMode5(SDValue N, SDValue &Base,
144                       SDValue &Offset);
145  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
146  bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
147
148  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
149
150  // Thumb Addressing Modes:
151  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
152  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
153                             unsigned Scale);
154  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
155  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
156  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
157  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
158                                SDValue &OffImm);
159  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
160                                 SDValue &OffImm);
161  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
162                                 SDValue &OffImm);
163  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
164                                 SDValue &OffImm);
165  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
166
167  // Thumb 2 Addressing Modes:
168  bool SelectT2ShifterOperandReg(SDValue N,
169                                 SDValue &BaseReg, SDValue &Opc);
170  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
171  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
172                            SDValue &OffImm);
173  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
174                                 SDValue &OffImm);
175  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
176                             SDValue &OffReg, SDValue &ShImm);
177
178  inline bool is_so_imm(unsigned Imm) const {
179    return ARM_AM::getSOImmVal(Imm) != -1;
180  }
181
182  inline bool is_so_imm_not(unsigned Imm) const {
183    return ARM_AM::getSOImmVal(~Imm) != -1;
184  }
185
186  inline bool is_t2_so_imm(unsigned Imm) const {
187    return ARM_AM::getT2SOImmVal(Imm) != -1;
188  }
189
190  inline bool is_t2_so_imm_not(unsigned Imm) const {
191    return ARM_AM::getT2SOImmVal(~Imm) != -1;
192  }
193
194  // Include the pieces autogenerated from the target description.
195#include "ARMGenDAGISel.inc"
196
197private:
198  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
199  /// ARM.
200  SDNode *SelectARMIndexedLoad(SDNode *N);
201  SDNode *SelectT2IndexedLoad(SDNode *N);
202
203  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
204  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
205  /// loads of D registers and even subregs and odd subregs of Q registers.
206  /// For NumVecs <= 2, QOpcodes1 is not used.
207  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
208                    unsigned *DOpcodes,
209                    unsigned *QOpcodes0, unsigned *QOpcodes1);
210
211  /// SelectVST - Select NEON store intrinsics.  NumVecs should
212  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
213  /// stores of D registers and even subregs and odd subregs of Q registers.
214  /// For NumVecs <= 2, QOpcodes1 is not used.
215  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
216                    unsigned *DOpcodes,
217                    unsigned *QOpcodes0, unsigned *QOpcodes1);
218
219  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
220  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
221  /// load/store of D registers and Q registers.
222  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
223                          bool isUpdating, unsigned NumVecs,
224                          unsigned *DOpcodes, unsigned *QOpcodes);
225
226  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
227  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
228  /// for loading D registers.  (Q registers are not supported.)
229  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
230                       unsigned *Opcodes);
231
232  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
233  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
234  /// generated to force the table registers to be consecutive.
235  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
236
237  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
238  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
239
240  /// SelectCMOVOp - Select CMOV instructions for ARM.
241  SDNode *SelectCMOVOp(SDNode *N);
242  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
243                              ARMCC::CondCodes CCVal, SDValue CCR,
244                              SDValue InFlag);
245  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
246                               ARMCC::CondCodes CCVal, SDValue CCR,
247                               SDValue InFlag);
248  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
249                              ARMCC::CondCodes CCVal, SDValue CCR,
250                              SDValue InFlag);
251  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
252                               ARMCC::CondCodes CCVal, SDValue CCR,
253                               SDValue InFlag);
254
255  SDNode *SelectConcatVector(SDNode *N);
256
257  SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
258
259  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
260  /// inline asm expressions.
261  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
262                                            char ConstraintCode,
263                                            std::vector<SDValue> &OutOps);
264
265  // Form pairs of consecutive S, D, or Q registers.
266  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
267  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
268  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
269
270  // Form sequences of 4 consecutive S, D, or Q registers.
271  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
272  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
273  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
274
275  // Get the alignment operand for a NEON VLD or VST instruction.
276  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
277};
278}
279
280/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
281/// operand. If so Imm will receive the 32-bit value.
282static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
283  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
284    Imm = cast<ConstantSDNode>(N)->getZExtValue();
285    return true;
286  }
287  return false;
288}
289
290// isInt32Immediate - This method tests to see if a constant operand.
291// If so Imm will receive the 32 bit value.
292static bool isInt32Immediate(SDValue N, unsigned &Imm) {
293  return isInt32Immediate(N.getNode(), Imm);
294}
295
296// isOpcWithIntImmediate - This method tests to see if the node is a specific
297// opcode and that it has a immediate integer right operand.
298// If so Imm will receive the 32 bit value.
299static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
300  return N->getOpcode() == Opc &&
301         isInt32Immediate(N->getOperand(1).getNode(), Imm);
302}
303
304/// \brief Check whether a particular node is a constant value representable as
305/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
306///
307/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
308static bool isScaledConstantInRange(SDValue Node, unsigned Scale,
309                                    int RangeMin, int RangeMax,
310                                    int &ScaledConstant) {
311  assert(Scale && "Invalid scale!");
312
313  // Check that this is a constant.
314  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
315  if (!C)
316    return false;
317
318  ScaledConstant = (int) C->getZExtValue();
319  if ((ScaledConstant % Scale) != 0)
320    return false;
321
322  ScaledConstant /= Scale;
323  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
324}
325
326/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
327/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
328/// least on current ARM implementations) which should be avoidded.
329bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
330  if (OptLevel == CodeGenOpt::None)
331    return true;
332
333  if (!CheckVMLxHazard)
334    return true;
335
336  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
337    return true;
338
339  if (!N->hasOneUse())
340    return false;
341
342  SDNode *Use = *N->use_begin();
343  if (Use->getOpcode() == ISD::CopyToReg)
344    return true;
345  if (Use->isMachineOpcode()) {
346    const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
347    if (MCID.mayStore())
348      return true;
349    unsigned Opcode = MCID.getOpcode();
350    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
351      return true;
352    // vmlx feeding into another vmlx. We actually want to unfold
353    // the use later in the MLxExpansion pass. e.g.
354    // vmla
355    // vmla (stall 8 cycles)
356    //
357    // vmul (5 cycles)
358    // vadd (5 cycles)
359    // vmla
360    // This adds up to about 18 - 19 cycles.
361    //
362    // vmla
363    // vmul (stall 4 cycles)
364    // vadd adds up to about 14 cycles.
365    return TII->isFpMLxInstruction(Opcode);
366  }
367
368  return false;
369}
370
371bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
372                                            ARM_AM::ShiftOpc ShOpcVal,
373                                            unsigned ShAmt) {
374  if (!Subtarget->isCortexA9())
375    return true;
376  if (Shift.hasOneUse())
377    return true;
378  // R << 2 is free.
379  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
380}
381
382bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
383                                              SDValue &BaseReg,
384                                              SDValue &Opc,
385                                              bool CheckProfitability) {
386  if (DisableShifterOp)
387    return false;
388
389  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
390
391  // Don't match base register only case. That is matched to a separate
392  // lower complexity pattern with explicit register operand.
393  if (ShOpcVal == ARM_AM::no_shift) return false;
394
395  BaseReg = N.getOperand(0);
396  unsigned ShImmVal = 0;
397  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
398  if (!RHS) return false;
399  ShImmVal = RHS->getZExtValue() & 31;
400  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
401                                  MVT::i32);
402  return true;
403}
404
405bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
406                                              SDValue &BaseReg,
407                                              SDValue &ShReg,
408                                              SDValue &Opc,
409                                              bool CheckProfitability) {
410  if (DisableShifterOp)
411    return false;
412
413  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
414
415  // Don't match base register only case. That is matched to a separate
416  // lower complexity pattern with explicit register operand.
417  if (ShOpcVal == ARM_AM::no_shift) return false;
418
419  BaseReg = N.getOperand(0);
420  unsigned ShImmVal = 0;
421  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
422  if (RHS) return false;
423
424  ShReg = N.getOperand(1);
425  if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
426    return false;
427  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
428                                  MVT::i32);
429  return true;
430}
431
432
433bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
434                                          SDValue &Base,
435                                          SDValue &OffImm) {
436  // Match simple R + imm12 operands.
437
438  // Base only.
439  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
440      !CurDAG->isBaseWithConstantOffset(N)) {
441    if (N.getOpcode() == ISD::FrameIndex) {
442      // Match frame index.
443      int FI = cast<FrameIndexSDNode>(N)->getIndex();
444      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
445      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
446      return true;
447    }
448
449    if (N.getOpcode() == ARMISD::Wrapper &&
450        !(Subtarget->useMovt() &&
451                     N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
452      Base = N.getOperand(0);
453    } else
454      Base = N;
455    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
456    return true;
457  }
458
459  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
460    int RHSC = (int)RHS->getZExtValue();
461    if (N.getOpcode() == ISD::SUB)
462      RHSC = -RHSC;
463
464    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
465      Base   = N.getOperand(0);
466      if (Base.getOpcode() == ISD::FrameIndex) {
467        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
468        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
469      }
470      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
471      return true;
472    }
473  }
474
475  // Base only.
476  Base = N;
477  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
478  return true;
479}
480
481
482
483bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
484                                      SDValue &Opc) {
485  if (N.getOpcode() == ISD::MUL &&
486      (!Subtarget->isCortexA9() || N.hasOneUse())) {
487    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
488      // X * [3,5,9] -> X + X * [2,4,8] etc.
489      int RHSC = (int)RHS->getZExtValue();
490      if (RHSC & 1) {
491        RHSC = RHSC & ~1;
492        ARM_AM::AddrOpc AddSub = ARM_AM::add;
493        if (RHSC < 0) {
494          AddSub = ARM_AM::sub;
495          RHSC = - RHSC;
496        }
497        if (isPowerOf2_32(RHSC)) {
498          unsigned ShAmt = Log2_32(RHSC);
499          Base = Offset = N.getOperand(0);
500          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
501                                                            ARM_AM::lsl),
502                                          MVT::i32);
503          return true;
504        }
505      }
506    }
507  }
508
509  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
510      // ISD::OR that is equivalent to an ISD::ADD.
511      !CurDAG->isBaseWithConstantOffset(N))
512    return false;
513
514  // Leave simple R +/- imm12 operands for LDRi12
515  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
516    int RHSC;
517    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
518                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
519      return false;
520  }
521
522  if (Subtarget->isCortexA9() && !N.hasOneUse())
523    // Compute R +/- (R << N) and reuse it.
524    return false;
525
526  // Otherwise this is R +/- [possibly shifted] R.
527  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
528  ARM_AM::ShiftOpc ShOpcVal =
529    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
530  unsigned ShAmt = 0;
531
532  Base   = N.getOperand(0);
533  Offset = N.getOperand(1);
534
535  if (ShOpcVal != ARM_AM::no_shift) {
536    // Check to see if the RHS of the shift is a constant, if not, we can't fold
537    // it.
538    if (ConstantSDNode *Sh =
539           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
540      ShAmt = Sh->getZExtValue();
541      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
542        Offset = N.getOperand(1).getOperand(0);
543      else {
544        ShAmt = 0;
545        ShOpcVal = ARM_AM::no_shift;
546      }
547    } else {
548      ShOpcVal = ARM_AM::no_shift;
549    }
550  }
551
552  // Try matching (R shl C) + (R).
553  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
554      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
555    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
556    if (ShOpcVal != ARM_AM::no_shift) {
557      // Check to see if the RHS of the shift is a constant, if not, we can't
558      // fold it.
559      if (ConstantSDNode *Sh =
560          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
561        ShAmt = Sh->getZExtValue();
562        if (!Subtarget->isCortexA9() ||
563            (N.hasOneUse() &&
564             isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
565          Offset = N.getOperand(0).getOperand(0);
566          Base = N.getOperand(1);
567        } else {
568          ShAmt = 0;
569          ShOpcVal = ARM_AM::no_shift;
570        }
571      } else {
572        ShOpcVal = ARM_AM::no_shift;
573      }
574    }
575  }
576
577  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
578                                  MVT::i32);
579  return true;
580}
581
582
583
584
585//-----
586
587AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
588                                                     SDValue &Base,
589                                                     SDValue &Offset,
590                                                     SDValue &Opc) {
591  if (N.getOpcode() == ISD::MUL &&
592      (!Subtarget->isCortexA9() || N.hasOneUse())) {
593    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
594      // X * [3,5,9] -> X + X * [2,4,8] etc.
595      int RHSC = (int)RHS->getZExtValue();
596      if (RHSC & 1) {
597        RHSC = RHSC & ~1;
598        ARM_AM::AddrOpc AddSub = ARM_AM::add;
599        if (RHSC < 0) {
600          AddSub = ARM_AM::sub;
601          RHSC = - RHSC;
602        }
603        if (isPowerOf2_32(RHSC)) {
604          unsigned ShAmt = Log2_32(RHSC);
605          Base = Offset = N.getOperand(0);
606          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
607                                                            ARM_AM::lsl),
608                                          MVT::i32);
609          return AM2_SHOP;
610        }
611      }
612    }
613  }
614
615  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
616      // ISD::OR that is equivalent to an ADD.
617      !CurDAG->isBaseWithConstantOffset(N)) {
618    Base = N;
619    if (N.getOpcode() == ISD::FrameIndex) {
620      int FI = cast<FrameIndexSDNode>(N)->getIndex();
621      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
622    } else if (N.getOpcode() == ARMISD::Wrapper &&
623               !(Subtarget->useMovt() &&
624                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
625      Base = N.getOperand(0);
626    }
627    Offset = CurDAG->getRegister(0, MVT::i32);
628    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
629                                                      ARM_AM::no_shift),
630                                    MVT::i32);
631    return AM2_BASE;
632  }
633
634  // Match simple R +/- imm12 operands.
635  if (N.getOpcode() != ISD::SUB) {
636    int RHSC;
637    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
638                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
639      Base = N.getOperand(0);
640      if (Base.getOpcode() == ISD::FrameIndex) {
641        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
642        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
643      }
644      Offset = CurDAG->getRegister(0, MVT::i32);
645
646      ARM_AM::AddrOpc AddSub = ARM_AM::add;
647      if (RHSC < 0) {
648        AddSub = ARM_AM::sub;
649        RHSC = - RHSC;
650      }
651      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
652                                                        ARM_AM::no_shift),
653                                      MVT::i32);
654      return AM2_BASE;
655    }
656  }
657
658  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
659    // Compute R +/- (R << N) and reuse it.
660    Base = N;
661    Offset = CurDAG->getRegister(0, MVT::i32);
662    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
663                                                      ARM_AM::no_shift),
664                                    MVT::i32);
665    return AM2_BASE;
666  }
667
668  // Otherwise this is R +/- [possibly shifted] R.
669  ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
670  ARM_AM::ShiftOpc ShOpcVal =
671    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
672  unsigned ShAmt = 0;
673
674  Base   = N.getOperand(0);
675  Offset = N.getOperand(1);
676
677  if (ShOpcVal != ARM_AM::no_shift) {
678    // Check to see if the RHS of the shift is a constant, if not, we can't fold
679    // it.
680    if (ConstantSDNode *Sh =
681           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
682      ShAmt = Sh->getZExtValue();
683      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
684        Offset = N.getOperand(1).getOperand(0);
685      else {
686        ShAmt = 0;
687        ShOpcVal = ARM_AM::no_shift;
688      }
689    } else {
690      ShOpcVal = ARM_AM::no_shift;
691    }
692  }
693
694  // Try matching (R shl C) + (R).
695  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
696      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
697    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
698    if (ShOpcVal != ARM_AM::no_shift) {
699      // Check to see if the RHS of the shift is a constant, if not, we can't
700      // fold it.
701      if (ConstantSDNode *Sh =
702          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
703        ShAmt = Sh->getZExtValue();
704        if (!Subtarget->isCortexA9() ||
705            (N.hasOneUse() &&
706             isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
707          Offset = N.getOperand(0).getOperand(0);
708          Base = N.getOperand(1);
709        } else {
710          ShAmt = 0;
711          ShOpcVal = ARM_AM::no_shift;
712        }
713      } else {
714        ShOpcVal = ARM_AM::no_shift;
715      }
716    }
717  }
718
719  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
720                                  MVT::i32);
721  return AM2_SHOP;
722}
723
724bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
725                                            SDValue &Offset, SDValue &Opc) {
726  unsigned Opcode = Op->getOpcode();
727  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
728    ? cast<LoadSDNode>(Op)->getAddressingMode()
729    : cast<StoreSDNode>(Op)->getAddressingMode();
730  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
731    ? ARM_AM::add : ARM_AM::sub;
732  int Val;
733  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
734    return false;
735
736  Offset = N;
737  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
738  unsigned ShAmt = 0;
739  if (ShOpcVal != ARM_AM::no_shift) {
740    // Check to see if the RHS of the shift is a constant, if not, we can't fold
741    // it.
742    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
743      ShAmt = Sh->getZExtValue();
744      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
745        Offset = N.getOperand(0);
746      else {
747        ShAmt = 0;
748        ShOpcVal = ARM_AM::no_shift;
749      }
750    } else {
751      ShOpcVal = ARM_AM::no_shift;
752    }
753  }
754
755  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
756                                  MVT::i32);
757  return true;
758}
759
760bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
761                                            SDValue &Offset, SDValue &Opc) {
762  int Val;
763  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
764    Offset = CurDAG->getRegister(0, MVT::i32);
765    Opc = CurDAG->getTargetConstant(Val, MVT::i32);
766    return true;
767  }
768
769  return false;
770}
771
772
773bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
774                                            SDValue &Offset, SDValue &Opc) {
775  unsigned Opcode = Op->getOpcode();
776  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
777    ? cast<LoadSDNode>(Op)->getAddressingMode()
778    : cast<StoreSDNode>(Op)->getAddressingMode();
779  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
780    ? ARM_AM::add : ARM_AM::sub;
781  int Val;
782  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
783    Offset = CurDAG->getRegister(0, MVT::i32);
784    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
785                                                      ARM_AM::no_shift),
786                                    MVT::i32);
787    return true;
788  }
789
790  return false;
791}
792
793bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
794  Base = N;
795  return true;
796}
797
798bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
799                                      SDValue &Base, SDValue &Offset,
800                                      SDValue &Opc) {
801  if (N.getOpcode() == ISD::SUB) {
802    // X - C  is canonicalize to X + -C, no need to handle it here.
803    Base = N.getOperand(0);
804    Offset = N.getOperand(1);
805    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
806    return true;
807  }
808
809  if (!CurDAG->isBaseWithConstantOffset(N)) {
810    Base = N;
811    if (N.getOpcode() == ISD::FrameIndex) {
812      int FI = cast<FrameIndexSDNode>(N)->getIndex();
813      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
814    }
815    Offset = CurDAG->getRegister(0, MVT::i32);
816    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
817    return true;
818  }
819
820  // If the RHS is +/- imm8, fold into addr mode.
821  int RHSC;
822  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
823                              -256 + 1, 256, RHSC)) { // 8 bits.
824    Base = N.getOperand(0);
825    if (Base.getOpcode() == ISD::FrameIndex) {
826      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
827      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
828    }
829    Offset = CurDAG->getRegister(0, MVT::i32);
830
831    ARM_AM::AddrOpc AddSub = ARM_AM::add;
832    if (RHSC < 0) {
833      AddSub = ARM_AM::sub;
834      RHSC = -RHSC;
835    }
836    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
837    return true;
838  }
839
840  Base = N.getOperand(0);
841  Offset = N.getOperand(1);
842  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
843  return true;
844}
845
846bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
847                                            SDValue &Offset, SDValue &Opc) {
848  unsigned Opcode = Op->getOpcode();
849  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
850    ? cast<LoadSDNode>(Op)->getAddressingMode()
851    : cast<StoreSDNode>(Op)->getAddressingMode();
852  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
853    ? ARM_AM::add : ARM_AM::sub;
854  int Val;
855  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
856    Offset = CurDAG->getRegister(0, MVT::i32);
857    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
858    return true;
859  }
860
861  Offset = N;
862  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
863  return true;
864}
865
866bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
867                                      SDValue &Base, SDValue &Offset) {
868  if (!CurDAG->isBaseWithConstantOffset(N)) {
869    Base = N;
870    if (N.getOpcode() == ISD::FrameIndex) {
871      int FI = cast<FrameIndexSDNode>(N)->getIndex();
872      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
873    } else if (N.getOpcode() == ARMISD::Wrapper &&
874               !(Subtarget->useMovt() &&
875                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
876      Base = N.getOperand(0);
877    }
878    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
879                                       MVT::i32);
880    return true;
881  }
882
883  // If the RHS is +/- imm8, fold into addr mode.
884  int RHSC;
885  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
886                              -256 + 1, 256, RHSC)) {
887    Base = N.getOperand(0);
888    if (Base.getOpcode() == ISD::FrameIndex) {
889      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
890      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
891    }
892
893    ARM_AM::AddrOpc AddSub = ARM_AM::add;
894    if (RHSC < 0) {
895      AddSub = ARM_AM::sub;
896      RHSC = -RHSC;
897    }
898    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
899                                       MVT::i32);
900    return true;
901  }
902
903  Base = N;
904  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
905                                     MVT::i32);
906  return true;
907}
908
909bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
910                                      SDValue &Align) {
911  Addr = N;
912
913  unsigned Alignment = 0;
914  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
915    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
916    // The maximum alignment is equal to the memory size being referenced.
917    unsigned LSNAlign = LSN->getAlignment();
918    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
919    if (LSNAlign > MemSize && MemSize > 1)
920      Alignment = MemSize;
921  } else {
922    // All other uses of addrmode6 are for intrinsics.  For now just record
923    // the raw alignment value; it will be refined later based on the legal
924    // alignment operands for the intrinsic.
925    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
926  }
927
928  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
929  return true;
930}
931
932bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
933                                            SDValue &Offset) {
934  LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
935  ISD::MemIndexedMode AM = LdSt->getAddressingMode();
936  if (AM != ISD::POST_INC)
937    return false;
938  Offset = N;
939  if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
940    if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
941      Offset = CurDAG->getRegister(0, MVT::i32);
942  }
943  return true;
944}
945
946bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
947                                       SDValue &Offset, SDValue &Label) {
948  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
949    Offset = N.getOperand(0);
950    SDValue N1 = N.getOperand(1);
951    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
952                                      MVT::i32);
953    return true;
954  }
955
956  return false;
957}
958
959
960//===----------------------------------------------------------------------===//
961//                         Thumb Addressing Modes
962//===----------------------------------------------------------------------===//
963
964bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
965                                            SDValue &Base, SDValue &Offset){
966  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
967    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
968    if (!NC || !NC->isNullValue())
969      return false;
970
971    Base = Offset = N;
972    return true;
973  }
974
975  Base = N.getOperand(0);
976  Offset = N.getOperand(1);
977  return true;
978}
979
980bool
981ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
982                                       SDValue &Offset, unsigned Scale) {
983  if (Scale == 4) {
984    SDValue TmpBase, TmpOffImm;
985    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
986      return false;  // We want to select tLDRspi / tSTRspi instead.
987
988    if (N.getOpcode() == ARMISD::Wrapper &&
989        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
990      return false;  // We want to select tLDRpci instead.
991  }
992
993  if (!CurDAG->isBaseWithConstantOffset(N))
994    return false;
995
996  // Thumb does not have [sp, r] address mode.
997  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
998  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
999  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1000      (RHSR && RHSR->getReg() == ARM::SP))
1001    return false;
1002
1003  // FIXME: Why do we explicitly check for a match here and then return false?
1004  // Presumably to allow something else to match, but shouldn't this be
1005  // documented?
1006  int RHSC;
1007  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1008    return false;
1009
1010  Base = N.getOperand(0);
1011  Offset = N.getOperand(1);
1012  return true;
1013}
1014
1015bool
1016ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1017                                          SDValue &Base,
1018                                          SDValue &Offset) {
1019  return SelectThumbAddrModeRI(N, Base, Offset, 1);
1020}
1021
1022bool
1023ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1024                                          SDValue &Base,
1025                                          SDValue &Offset) {
1026  return SelectThumbAddrModeRI(N, Base, Offset, 2);
1027}
1028
1029bool
1030ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1031                                          SDValue &Base,
1032                                          SDValue &Offset) {
1033  return SelectThumbAddrModeRI(N, Base, Offset, 4);
1034}
1035
1036bool
1037ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1038                                          SDValue &Base, SDValue &OffImm) {
1039  if (Scale == 4) {
1040    SDValue TmpBase, TmpOffImm;
1041    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1042      return false;  // We want to select tLDRspi / tSTRspi instead.
1043
1044    if (N.getOpcode() == ARMISD::Wrapper &&
1045        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1046      return false;  // We want to select tLDRpci instead.
1047  }
1048
1049  if (!CurDAG->isBaseWithConstantOffset(N)) {
1050    if (N.getOpcode() == ARMISD::Wrapper &&
1051        !(Subtarget->useMovt() &&
1052          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1053      Base = N.getOperand(0);
1054    } else {
1055      Base = N;
1056    }
1057
1058    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1059    return true;
1060  }
1061
1062  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1063  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1064  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1065      (RHSR && RHSR->getReg() == ARM::SP)) {
1066    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1067    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1068    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1069    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1070
1071    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1072    if (LHSC != 0 || RHSC != 0) return false;
1073
1074    Base = N;
1075    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1076    return true;
1077  }
1078
1079  // If the RHS is + imm5 * scale, fold into addr mode.
1080  int RHSC;
1081  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1082    Base = N.getOperand(0);
1083    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1084    return true;
1085  }
1086
1087  Base = N.getOperand(0);
1088  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1089  return true;
1090}
1091
1092bool
1093ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1094                                           SDValue &OffImm) {
1095  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1096}
1097
1098bool
1099ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1100                                           SDValue &OffImm) {
1101  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1102}
1103
1104bool
1105ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1106                                           SDValue &OffImm) {
1107  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1108}
1109
1110bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1111                                            SDValue &Base, SDValue &OffImm) {
1112  if (N.getOpcode() == ISD::FrameIndex) {
1113    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1114    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1115    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1116    return true;
1117  }
1118
1119  if (!CurDAG->isBaseWithConstantOffset(N))
1120    return false;
1121
1122  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1123  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1124      (LHSR && LHSR->getReg() == ARM::SP)) {
1125    // If the RHS is + imm8 * scale, fold into addr mode.
1126    int RHSC;
1127    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1128      Base = N.getOperand(0);
1129      if (Base.getOpcode() == ISD::FrameIndex) {
1130        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1131        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1132      }
1133      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1134      return true;
1135    }
1136  }
1137
1138  return false;
1139}
1140
1141
1142//===----------------------------------------------------------------------===//
1143//                        Thumb 2 Addressing Modes
1144//===----------------------------------------------------------------------===//
1145
1146
1147bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1148                                                SDValue &Opc) {
1149  if (DisableShifterOp)
1150    return false;
1151
1152  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1153
1154  // Don't match base register only case. That is matched to a separate
1155  // lower complexity pattern with explicit register operand.
1156  if (ShOpcVal == ARM_AM::no_shift) return false;
1157
1158  BaseReg = N.getOperand(0);
1159  unsigned ShImmVal = 0;
1160  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1161    ShImmVal = RHS->getZExtValue() & 31;
1162    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1163    return true;
1164  }
1165
1166  return false;
1167}
1168
1169bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1170                                            SDValue &Base, SDValue &OffImm) {
1171  // Match simple R + imm12 operands.
1172
1173  // Base only.
1174  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1175      !CurDAG->isBaseWithConstantOffset(N)) {
1176    if (N.getOpcode() == ISD::FrameIndex) {
1177      // Match frame index.
1178      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1179      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1180      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1181      return true;
1182    }
1183
1184    if (N.getOpcode() == ARMISD::Wrapper &&
1185               !(Subtarget->useMovt() &&
1186                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1187      Base = N.getOperand(0);
1188      if (Base.getOpcode() == ISD::TargetConstantPool)
1189        return false;  // We want to select t2LDRpci instead.
1190    } else
1191      Base = N;
1192    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1193    return true;
1194  }
1195
1196  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1197    if (SelectT2AddrModeImm8(N, Base, OffImm))
1198      // Let t2LDRi8 handle (R - imm8).
1199      return false;
1200
1201    int RHSC = (int)RHS->getZExtValue();
1202    if (N.getOpcode() == ISD::SUB)
1203      RHSC = -RHSC;
1204
1205    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1206      Base   = N.getOperand(0);
1207      if (Base.getOpcode() == ISD::FrameIndex) {
1208        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1209        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1210      }
1211      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1212      return true;
1213    }
1214  }
1215
1216  // Base only.
1217  Base = N;
1218  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1219  return true;
1220}
1221
1222bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1223                                           SDValue &Base, SDValue &OffImm) {
1224  // Match simple R - imm8 operands.
1225  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1226      !CurDAG->isBaseWithConstantOffset(N))
1227    return false;
1228
1229  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1230    int RHSC = (int)RHS->getSExtValue();
1231    if (N.getOpcode() == ISD::SUB)
1232      RHSC = -RHSC;
1233
1234    if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1235      Base = N.getOperand(0);
1236      if (Base.getOpcode() == ISD::FrameIndex) {
1237        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1238        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1239      }
1240      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1241      return true;
1242    }
1243  }
1244
1245  return false;
1246}
1247
1248bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1249                                                 SDValue &OffImm){
1250  unsigned Opcode = Op->getOpcode();
1251  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1252    ? cast<LoadSDNode>(Op)->getAddressingMode()
1253    : cast<StoreSDNode>(Op)->getAddressingMode();
1254  int RHSC;
1255  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1256    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1257      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1258      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1259    return true;
1260  }
1261
1262  return false;
1263}
1264
1265bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1266                                            SDValue &Base,
1267                                            SDValue &OffReg, SDValue &ShImm) {
1268  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1269  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1270    return false;
1271
1272  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1273  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1274    int RHSC = (int)RHS->getZExtValue();
1275    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1276      return false;
1277    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1278      return false;
1279  }
1280
1281  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1282    // Compute R + (R << [1,2,3]) and reuse it.
1283    Base = N;
1284    return false;
1285  }
1286
1287  // Look for (R + R) or (R + (R << [1,2,3])).
1288  unsigned ShAmt = 0;
1289  Base   = N.getOperand(0);
1290  OffReg = N.getOperand(1);
1291
1292  // Swap if it is ((R << c) + R).
1293  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1294  if (ShOpcVal != ARM_AM::lsl) {
1295    ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1296    if (ShOpcVal == ARM_AM::lsl)
1297      std::swap(Base, OffReg);
1298  }
1299
1300  if (ShOpcVal == ARM_AM::lsl) {
1301    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1302    // it.
1303    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1304      ShAmt = Sh->getZExtValue();
1305      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1306        OffReg = OffReg.getOperand(0);
1307      else {
1308        ShAmt = 0;
1309        ShOpcVal = ARM_AM::no_shift;
1310      }
1311    } else {
1312      ShOpcVal = ARM_AM::no_shift;
1313    }
1314  }
1315
1316  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1317
1318  return true;
1319}
1320
1321//===--------------------------------------------------------------------===//
1322
1323/// getAL - Returns a ARMCC::AL immediate node.
1324static inline SDValue getAL(SelectionDAG *CurDAG) {
1325  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1326}
1327
1328SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1329  LoadSDNode *LD = cast<LoadSDNode>(N);
1330  ISD::MemIndexedMode AM = LD->getAddressingMode();
1331  if (AM == ISD::UNINDEXED)
1332    return NULL;
1333
1334  EVT LoadedVT = LD->getMemoryVT();
1335  SDValue Offset, AMOpc;
1336  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1337  unsigned Opcode = 0;
1338  bool Match = false;
1339  if (LoadedVT == MVT::i32 && isPre &&
1340      SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1341    Opcode = ARM::LDR_PRE_IMM;
1342    Match = true;
1343  } else if (LoadedVT == MVT::i32 && !isPre &&
1344      SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1345    Opcode = ARM::LDR_POST_IMM;
1346    Match = true;
1347  } else if (LoadedVT == MVT::i32 &&
1348      SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1349    Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1350    Match = true;
1351
1352  } else if (LoadedVT == MVT::i16 &&
1353             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1354    Match = true;
1355    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1356      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1357      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1358  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1359    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1360      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1361        Match = true;
1362        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1363      }
1364    } else {
1365      if (isPre &&
1366          SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1367        Match = true;
1368        Opcode = ARM::LDRB_PRE_IMM;
1369      } else if (!isPre &&
1370                  SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1371        Match = true;
1372        Opcode = ARM::LDRB_POST_IMM;
1373      } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1374        Match = true;
1375        Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1376      }
1377    }
1378  }
1379
1380  if (Match) {
1381    if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1382      SDValue Chain = LD->getChain();
1383      SDValue Base = LD->getBasePtr();
1384      SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1385                       CurDAG->getRegister(0, MVT::i32), Chain };
1386      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1387                                    MVT::Other, Ops, 5);
1388    } else {
1389      SDValue Chain = LD->getChain();
1390      SDValue Base = LD->getBasePtr();
1391      SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1392                       CurDAG->getRegister(0, MVT::i32), Chain };
1393      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1394                                    MVT::Other, Ops, 6);
1395    }
1396  }
1397
1398  return NULL;
1399}
1400
1401SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1402  LoadSDNode *LD = cast<LoadSDNode>(N);
1403  ISD::MemIndexedMode AM = LD->getAddressingMode();
1404  if (AM == ISD::UNINDEXED)
1405    return NULL;
1406
1407  EVT LoadedVT = LD->getMemoryVT();
1408  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1409  SDValue Offset;
1410  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1411  unsigned Opcode = 0;
1412  bool Match = false;
1413  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1414    switch (LoadedVT.getSimpleVT().SimpleTy) {
1415    case MVT::i32:
1416      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1417      break;
1418    case MVT::i16:
1419      if (isSExtLd)
1420        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1421      else
1422        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1423      break;
1424    case MVT::i8:
1425    case MVT::i1:
1426      if (isSExtLd)
1427        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1428      else
1429        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1430      break;
1431    default:
1432      return NULL;
1433    }
1434    Match = true;
1435  }
1436
1437  if (Match) {
1438    SDValue Chain = LD->getChain();
1439    SDValue Base = LD->getBasePtr();
1440    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1441                     CurDAG->getRegister(0, MVT::i32), Chain };
1442    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1443                                  MVT::Other, Ops, 5);
1444  }
1445
1446  return NULL;
1447}
1448
1449/// PairSRegs - Form a D register from a pair of S registers.
1450///
1451SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1452  DebugLoc dl = V0.getNode()->getDebugLoc();
1453  SDValue RegClass =
1454    CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1455  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1456  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1457  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1458  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1459}
1460
1461/// PairDRegs - Form a quad register from a pair of D registers.
1462///
1463SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1464  DebugLoc dl = V0.getNode()->getDebugLoc();
1465  SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1466  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1467  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1468  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1469  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1470}
1471
1472/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1473///
1474SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1475  DebugLoc dl = V0.getNode()->getDebugLoc();
1476  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1477  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1478  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1479  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1480  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1481}
1482
1483/// QuadSRegs - Form 4 consecutive S registers.
1484///
1485SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1486                                   SDValue V2, SDValue V3) {
1487  DebugLoc dl = V0.getNode()->getDebugLoc();
1488  SDValue RegClass =
1489    CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1490  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1491  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1492  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1493  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1494  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1495                                    V2, SubReg2, V3, SubReg3 };
1496  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1497}
1498
1499/// QuadDRegs - Form 4 consecutive D registers.
1500///
1501SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1502                                   SDValue V2, SDValue V3) {
1503  DebugLoc dl = V0.getNode()->getDebugLoc();
1504  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1505  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1506  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1507  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1508  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1509  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1510                                    V2, SubReg2, V3, SubReg3 };
1511  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1512}
1513
1514/// QuadQRegs - Form 4 consecutive Q registers.
1515///
1516SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1517                                   SDValue V2, SDValue V3) {
1518  DebugLoc dl = V0.getNode()->getDebugLoc();
1519  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1520  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1521  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1522  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1523  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1524  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1525                                    V2, SubReg2, V3, SubReg3 };
1526  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1527}
1528
1529/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1530/// of a NEON VLD or VST instruction.  The supported values depend on the
1531/// number of registers being loaded.
1532SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1533                                       bool is64BitVector) {
1534  unsigned NumRegs = NumVecs;
1535  if (!is64BitVector && NumVecs < 3)
1536    NumRegs *= 2;
1537
1538  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1539  if (Alignment >= 32 && NumRegs == 4)
1540    Alignment = 32;
1541  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1542    Alignment = 16;
1543  else if (Alignment >= 8)
1544    Alignment = 8;
1545  else
1546    Alignment = 0;
1547
1548  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1549}
1550
1551SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1552                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1553                                   unsigned *QOpcodes1) {
1554  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1555  DebugLoc dl = N->getDebugLoc();
1556
1557  SDValue MemAddr, Align;
1558  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1559  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1560    return NULL;
1561
1562  SDValue Chain = N->getOperand(0);
1563  EVT VT = N->getValueType(0);
1564  bool is64BitVector = VT.is64BitVector();
1565  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1566
1567  unsigned OpcodeIndex;
1568  switch (VT.getSimpleVT().SimpleTy) {
1569  default: llvm_unreachable("unhandled vld type");
1570    // Double-register operations:
1571  case MVT::v8i8:  OpcodeIndex = 0; break;
1572  case MVT::v4i16: OpcodeIndex = 1; break;
1573  case MVT::v2f32:
1574  case MVT::v2i32: OpcodeIndex = 2; break;
1575  case MVT::v1i64: OpcodeIndex = 3; break;
1576    // Quad-register operations:
1577  case MVT::v16i8: OpcodeIndex = 0; break;
1578  case MVT::v8i16: OpcodeIndex = 1; break;
1579  case MVT::v4f32:
1580  case MVT::v4i32: OpcodeIndex = 2; break;
1581  case MVT::v2i64: OpcodeIndex = 3;
1582    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1583    break;
1584  }
1585
1586  EVT ResTy;
1587  if (NumVecs == 1)
1588    ResTy = VT;
1589  else {
1590    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1591    if (!is64BitVector)
1592      ResTyElts *= 2;
1593    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1594  }
1595  std::vector<EVT> ResTys;
1596  ResTys.push_back(ResTy);
1597  if (isUpdating)
1598    ResTys.push_back(MVT::i32);
1599  ResTys.push_back(MVT::Other);
1600
1601  SDValue Pred = getAL(CurDAG);
1602  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1603  SDNode *VLd;
1604  SmallVector<SDValue, 7> Ops;
1605
1606  // Double registers and VLD1/VLD2 quad registers are directly supported.
1607  if (is64BitVector || NumVecs <= 2) {
1608    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1609                    QOpcodes0[OpcodeIndex]);
1610    Ops.push_back(MemAddr);
1611    Ops.push_back(Align);
1612    if (isUpdating) {
1613      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1614      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1615    }
1616    Ops.push_back(Pred);
1617    Ops.push_back(Reg0);
1618    Ops.push_back(Chain);
1619    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1620
1621  } else {
1622    // Otherwise, quad registers are loaded with two separate instructions,
1623    // where one loads the even registers and the other loads the odd registers.
1624    EVT AddrTy = MemAddr.getValueType();
1625
1626    // Load the even subregs.  This is always an updating load, so that it
1627    // provides the address to the second load for the odd subregs.
1628    SDValue ImplDef =
1629      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1630    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1631    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1632                                          ResTy, AddrTy, MVT::Other, OpsA, 7);
1633    Chain = SDValue(VLdA, 2);
1634
1635    // Load the odd subregs.
1636    Ops.push_back(SDValue(VLdA, 1));
1637    Ops.push_back(Align);
1638    if (isUpdating) {
1639      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1640      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1641             "only constant post-increment update allowed for VLD3/4");
1642      (void)Inc;
1643      Ops.push_back(Reg0);
1644    }
1645    Ops.push_back(SDValue(VLdA, 0));
1646    Ops.push_back(Pred);
1647    Ops.push_back(Reg0);
1648    Ops.push_back(Chain);
1649    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1650                                 Ops.data(), Ops.size());
1651  }
1652
1653  // Transfer memoperands.
1654  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1655  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1656  cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1657
1658  if (NumVecs == 1)
1659    return VLd;
1660
1661  // Extract out the subregisters.
1662  SDValue SuperReg = SDValue(VLd, 0);
1663  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1664         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1665  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1666  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1667    ReplaceUses(SDValue(N, Vec),
1668                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1669  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1670  if (isUpdating)
1671    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1672  return NULL;
1673}
1674
1675SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1676                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1677                                   unsigned *QOpcodes1) {
1678  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1679  DebugLoc dl = N->getDebugLoc();
1680
1681  SDValue MemAddr, Align;
1682  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1683  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1684  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1685    return NULL;
1686
1687  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1688  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1689
1690  SDValue Chain = N->getOperand(0);
1691  EVT VT = N->getOperand(Vec0Idx).getValueType();
1692  bool is64BitVector = VT.is64BitVector();
1693  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1694
1695  unsigned OpcodeIndex;
1696  switch (VT.getSimpleVT().SimpleTy) {
1697  default: llvm_unreachable("unhandled vst type");
1698    // Double-register operations:
1699  case MVT::v8i8:  OpcodeIndex = 0; break;
1700  case MVT::v4i16: OpcodeIndex = 1; break;
1701  case MVT::v2f32:
1702  case MVT::v2i32: OpcodeIndex = 2; break;
1703  case MVT::v1i64: OpcodeIndex = 3; break;
1704    // Quad-register operations:
1705  case MVT::v16i8: OpcodeIndex = 0; break;
1706  case MVT::v8i16: OpcodeIndex = 1; break;
1707  case MVT::v4f32:
1708  case MVT::v4i32: OpcodeIndex = 2; break;
1709  case MVT::v2i64: OpcodeIndex = 3;
1710    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1711    break;
1712  }
1713
1714  std::vector<EVT> ResTys;
1715  if (isUpdating)
1716    ResTys.push_back(MVT::i32);
1717  ResTys.push_back(MVT::Other);
1718
1719  SDValue Pred = getAL(CurDAG);
1720  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1721  SmallVector<SDValue, 7> Ops;
1722
1723  // Double registers and VST1/VST2 quad registers are directly supported.
1724  if (is64BitVector || NumVecs <= 2) {
1725    SDValue SrcReg;
1726    if (NumVecs == 1) {
1727      SrcReg = N->getOperand(Vec0Idx);
1728    } else if (is64BitVector) {
1729      // Form a REG_SEQUENCE to force register allocation.
1730      SDValue V0 = N->getOperand(Vec0Idx + 0);
1731      SDValue V1 = N->getOperand(Vec0Idx + 1);
1732      if (NumVecs == 2)
1733        SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1734      else {
1735        SDValue V2 = N->getOperand(Vec0Idx + 2);
1736        // If it's a vst3, form a quad D-register and leave the last part as
1737        // an undef.
1738        SDValue V3 = (NumVecs == 3)
1739          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1740          : N->getOperand(Vec0Idx + 3);
1741        SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1742      }
1743    } else {
1744      // Form a QQ register.
1745      SDValue Q0 = N->getOperand(Vec0Idx);
1746      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1747      SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1748    }
1749
1750    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1751                    QOpcodes0[OpcodeIndex]);
1752    Ops.push_back(MemAddr);
1753    Ops.push_back(Align);
1754    if (isUpdating) {
1755      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1756      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1757    }
1758    Ops.push_back(SrcReg);
1759    Ops.push_back(Pred);
1760    Ops.push_back(Reg0);
1761    Ops.push_back(Chain);
1762    SDNode *VSt =
1763      CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1764
1765    // Transfer memoperands.
1766    cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1767
1768    return VSt;
1769  }
1770
1771  // Otherwise, quad registers are stored with two separate instructions,
1772  // where one stores the even registers and the other stores the odd registers.
1773
1774  // Form the QQQQ REG_SEQUENCE.
1775  SDValue V0 = N->getOperand(Vec0Idx + 0);
1776  SDValue V1 = N->getOperand(Vec0Idx + 1);
1777  SDValue V2 = N->getOperand(Vec0Idx + 2);
1778  SDValue V3 = (NumVecs == 3)
1779    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1780    : N->getOperand(Vec0Idx + 3);
1781  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1782
1783  // Store the even D registers.  This is always an updating store, so that it
1784  // provides the address to the second store for the odd subregs.
1785  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1786  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1787                                        MemAddr.getValueType(),
1788                                        MVT::Other, OpsA, 7);
1789  cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1790  Chain = SDValue(VStA, 1);
1791
1792  // Store the odd D registers.
1793  Ops.push_back(SDValue(VStA, 0));
1794  Ops.push_back(Align);
1795  if (isUpdating) {
1796    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1797    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1798           "only constant post-increment update allowed for VST3/4");
1799    (void)Inc;
1800    Ops.push_back(Reg0);
1801  }
1802  Ops.push_back(RegSeq);
1803  Ops.push_back(Pred);
1804  Ops.push_back(Reg0);
1805  Ops.push_back(Chain);
1806  SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1807                                        Ops.data(), Ops.size());
1808  cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1809  return VStB;
1810}
1811
1812SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1813                                         bool isUpdating, unsigned NumVecs,
1814                                         unsigned *DOpcodes,
1815                                         unsigned *QOpcodes) {
1816  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1817  DebugLoc dl = N->getDebugLoc();
1818
1819  SDValue MemAddr, Align;
1820  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1821  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1822  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1823    return NULL;
1824
1825  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1826  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1827
1828  SDValue Chain = N->getOperand(0);
1829  unsigned Lane =
1830    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1831  EVT VT = N->getOperand(Vec0Idx).getValueType();
1832  bool is64BitVector = VT.is64BitVector();
1833
1834  unsigned Alignment = 0;
1835  if (NumVecs != 3) {
1836    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1837    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1838    if (Alignment > NumBytes)
1839      Alignment = NumBytes;
1840    if (Alignment < 8 && Alignment < NumBytes)
1841      Alignment = 0;
1842    // Alignment must be a power of two; make sure of that.
1843    Alignment = (Alignment & -Alignment);
1844    if (Alignment == 1)
1845      Alignment = 0;
1846  }
1847  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1848
1849  unsigned OpcodeIndex;
1850  switch (VT.getSimpleVT().SimpleTy) {
1851  default: llvm_unreachable("unhandled vld/vst lane type");
1852    // Double-register operations:
1853  case MVT::v8i8:  OpcodeIndex = 0; break;
1854  case MVT::v4i16: OpcodeIndex = 1; break;
1855  case MVT::v2f32:
1856  case MVT::v2i32: OpcodeIndex = 2; break;
1857    // Quad-register operations:
1858  case MVT::v8i16: OpcodeIndex = 0; break;
1859  case MVT::v4f32:
1860  case MVT::v4i32: OpcodeIndex = 1; break;
1861  }
1862
1863  std::vector<EVT> ResTys;
1864  if (IsLoad) {
1865    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1866    if (!is64BitVector)
1867      ResTyElts *= 2;
1868    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1869                                      MVT::i64, ResTyElts));
1870  }
1871  if (isUpdating)
1872    ResTys.push_back(MVT::i32);
1873  ResTys.push_back(MVT::Other);
1874
1875  SDValue Pred = getAL(CurDAG);
1876  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1877
1878  SmallVector<SDValue, 8> Ops;
1879  Ops.push_back(MemAddr);
1880  Ops.push_back(Align);
1881  if (isUpdating) {
1882    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1883    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1884  }
1885
1886  SDValue SuperReg;
1887  SDValue V0 = N->getOperand(Vec0Idx + 0);
1888  SDValue V1 = N->getOperand(Vec0Idx + 1);
1889  if (NumVecs == 2) {
1890    if (is64BitVector)
1891      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1892    else
1893      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1894  } else {
1895    SDValue V2 = N->getOperand(Vec0Idx + 2);
1896    SDValue V3 = (NumVecs == 3)
1897      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1898      : N->getOperand(Vec0Idx + 3);
1899    if (is64BitVector)
1900      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1901    else
1902      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1903  }
1904  Ops.push_back(SuperReg);
1905  Ops.push_back(getI32Imm(Lane));
1906  Ops.push_back(Pred);
1907  Ops.push_back(Reg0);
1908  Ops.push_back(Chain);
1909
1910  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1911                                  QOpcodes[OpcodeIndex]);
1912  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1913                                         Ops.data(), Ops.size());
1914  cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1915  if (!IsLoad)
1916    return VLdLn;
1917
1918  // Extract the subregisters.
1919  SuperReg = SDValue(VLdLn, 0);
1920  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1921         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1922  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1923  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1924    ReplaceUses(SDValue(N, Vec),
1925                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1926  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1927  if (isUpdating)
1928    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1929  return NULL;
1930}
1931
1932SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1933                                      unsigned NumVecs, unsigned *Opcodes) {
1934  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1935  DebugLoc dl = N->getDebugLoc();
1936
1937  SDValue MemAddr, Align;
1938  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1939    return NULL;
1940
1941  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1942  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1943
1944  SDValue Chain = N->getOperand(0);
1945  EVT VT = N->getValueType(0);
1946
1947  unsigned Alignment = 0;
1948  if (NumVecs != 3) {
1949    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1950    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1951    if (Alignment > NumBytes)
1952      Alignment = NumBytes;
1953    if (Alignment < 8 && Alignment < NumBytes)
1954      Alignment = 0;
1955    // Alignment must be a power of two; make sure of that.
1956    Alignment = (Alignment & -Alignment);
1957    if (Alignment == 1)
1958      Alignment = 0;
1959  }
1960  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1961
1962  unsigned OpcodeIndex;
1963  switch (VT.getSimpleVT().SimpleTy) {
1964  default: llvm_unreachable("unhandled vld-dup type");
1965  case MVT::v8i8:  OpcodeIndex = 0; break;
1966  case MVT::v4i16: OpcodeIndex = 1; break;
1967  case MVT::v2f32:
1968  case MVT::v2i32: OpcodeIndex = 2; break;
1969  }
1970
1971  SDValue Pred = getAL(CurDAG);
1972  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1973  SDValue SuperReg;
1974  unsigned Opc = Opcodes[OpcodeIndex];
1975  SmallVector<SDValue, 6> Ops;
1976  Ops.push_back(MemAddr);
1977  Ops.push_back(Align);
1978  if (isUpdating) {
1979    SDValue Inc = N->getOperand(2);
1980    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1981  }
1982  Ops.push_back(Pred);
1983  Ops.push_back(Reg0);
1984  Ops.push_back(Chain);
1985
1986  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1987  std::vector<EVT> ResTys;
1988  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
1989  if (isUpdating)
1990    ResTys.push_back(MVT::i32);
1991  ResTys.push_back(MVT::Other);
1992  SDNode *VLdDup =
1993    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1994  cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
1995  SuperReg = SDValue(VLdDup, 0);
1996
1997  // Extract the subregisters.
1998  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1999  unsigned SubIdx = ARM::dsub_0;
2000  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2001    ReplaceUses(SDValue(N, Vec),
2002                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2003  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2004  if (isUpdating)
2005    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2006  return NULL;
2007}
2008
2009SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2010                                    unsigned Opc) {
2011  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2012  DebugLoc dl = N->getDebugLoc();
2013  EVT VT = N->getValueType(0);
2014  unsigned FirstTblReg = IsExt ? 2 : 1;
2015
2016  // Form a REG_SEQUENCE to force register allocation.
2017  SDValue RegSeq;
2018  SDValue V0 = N->getOperand(FirstTblReg + 0);
2019  SDValue V1 = N->getOperand(FirstTblReg + 1);
2020  if (NumVecs == 2)
2021    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2022  else {
2023    SDValue V2 = N->getOperand(FirstTblReg + 2);
2024    // If it's a vtbl3, form a quad D-register and leave the last part as
2025    // an undef.
2026    SDValue V3 = (NumVecs == 3)
2027      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2028      : N->getOperand(FirstTblReg + 3);
2029    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2030  }
2031
2032  SmallVector<SDValue, 6> Ops;
2033  if (IsExt)
2034    Ops.push_back(N->getOperand(1));
2035  Ops.push_back(RegSeq);
2036  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2037  Ops.push_back(getAL(CurDAG)); // predicate
2038  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2039  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2040}
2041
2042SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2043                                                     bool isSigned) {
2044  if (!Subtarget->hasV6T2Ops())
2045    return NULL;
2046
2047  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2048    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2049
2050
2051  // For unsigned extracts, check for a shift right and mask
2052  unsigned And_imm = 0;
2053  if (N->getOpcode() == ISD::AND) {
2054    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2055
2056      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2057      if (And_imm & (And_imm + 1))
2058        return NULL;
2059
2060      unsigned Srl_imm = 0;
2061      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2062                                Srl_imm)) {
2063        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2064
2065        // Note: The width operand is encoded as width-1.
2066        unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2067        unsigned LSB = Srl_imm;
2068        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2069        SDValue Ops[] = { N->getOperand(0).getOperand(0),
2070                          CurDAG->getTargetConstant(LSB, MVT::i32),
2071                          CurDAG->getTargetConstant(Width, MVT::i32),
2072          getAL(CurDAG), Reg0 };
2073        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2074      }
2075    }
2076    return NULL;
2077  }
2078
2079  // Otherwise, we're looking for a shift of a shift
2080  unsigned Shl_imm = 0;
2081  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2082    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2083    unsigned Srl_imm = 0;
2084    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2085      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2086      // Note: The width operand is encoded as width-1.
2087      unsigned Width = 32 - Srl_imm - 1;
2088      int LSB = Srl_imm - Shl_imm;
2089      if (LSB < 0)
2090        return NULL;
2091      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2092      SDValue Ops[] = { N->getOperand(0).getOperand(0),
2093                        CurDAG->getTargetConstant(LSB, MVT::i32),
2094                        CurDAG->getTargetConstant(Width, MVT::i32),
2095                        getAL(CurDAG), Reg0 };
2096      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2097    }
2098  }
2099  return NULL;
2100}
2101
2102SDNode *ARMDAGToDAGISel::
2103SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2104                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2105  SDValue CPTmp0;
2106  SDValue CPTmp1;
2107  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2108    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2109    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2110    unsigned Opc = 0;
2111    switch (SOShOp) {
2112    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2113    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2114    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2115    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2116    default:
2117      llvm_unreachable("Unknown so_reg opcode!");
2118      break;
2119    }
2120    SDValue SOShImm =
2121      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2122    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2123    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2124    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2125  }
2126  return 0;
2127}
2128
2129SDNode *ARMDAGToDAGISel::
2130SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2131                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2132  SDValue CPTmp0;
2133  SDValue CPTmp1;
2134  SDValue CPTmp2;
2135  if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2136    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2137    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2138    return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2139  }
2140
2141  if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2142    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2143    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2144    return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2145  }
2146  return 0;
2147}
2148
2149SDNode *ARMDAGToDAGISel::
2150SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2151                  ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2152  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2153  if (!T)
2154    return 0;
2155
2156  unsigned Opc = 0;
2157  unsigned TrueImm = T->getZExtValue();
2158  if (is_t2_so_imm(TrueImm)) {
2159    Opc = ARM::t2MOVCCi;
2160  } else if (TrueImm <= 0xffff) {
2161    Opc = ARM::t2MOVCCi16;
2162  } else if (is_t2_so_imm_not(TrueImm)) {
2163    TrueImm = ~TrueImm;
2164    Opc = ARM::t2MVNCCi;
2165  } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2166    // Large immediate.
2167    Opc = ARM::t2MOVCCi32imm;
2168  }
2169
2170  if (Opc) {
2171    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2172    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2173    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2174    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2175  }
2176
2177  return 0;
2178}
2179
2180SDNode *ARMDAGToDAGISel::
2181SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2182                   ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2183  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2184  if (!T)
2185    return 0;
2186
2187  unsigned Opc = 0;
2188  unsigned TrueImm = T->getZExtValue();
2189  bool isSoImm = is_so_imm(TrueImm);
2190  if (isSoImm) {
2191    Opc = ARM::MOVCCi;
2192  } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2193    Opc = ARM::MOVCCi16;
2194  } else if (is_so_imm_not(TrueImm)) {
2195    TrueImm = ~TrueImm;
2196    Opc = ARM::MVNCCi;
2197  } else if (TrueVal.getNode()->hasOneUse() &&
2198             (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2199    // Large immediate.
2200    Opc = ARM::MOVCCi32imm;
2201  }
2202
2203  if (Opc) {
2204    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2205    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2206    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2207    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2208  }
2209
2210  return 0;
2211}
2212
2213SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2214  EVT VT = N->getValueType(0);
2215  SDValue FalseVal = N->getOperand(0);
2216  SDValue TrueVal  = N->getOperand(1);
2217  SDValue CC = N->getOperand(2);
2218  SDValue CCR = N->getOperand(3);
2219  SDValue InFlag = N->getOperand(4);
2220  assert(CC.getOpcode() == ISD::Constant);
2221  assert(CCR.getOpcode() == ISD::Register);
2222  ARMCC::CondCodes CCVal =
2223    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2224
2225  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2226    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2227    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2228    // Pattern complexity = 18  cost = 1  size = 0
2229    SDValue CPTmp0;
2230    SDValue CPTmp1;
2231    SDValue CPTmp2;
2232    if (Subtarget->isThumb()) {
2233      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2234                                        CCVal, CCR, InFlag);
2235      if (!Res)
2236        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2237                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2238      if (Res)
2239        return Res;
2240    } else {
2241      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2242                                         CCVal, CCR, InFlag);
2243      if (!Res)
2244        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2245                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2246      if (Res)
2247        return Res;
2248    }
2249
2250    // Pattern: (ARMcmov:i32 GPR:i32:$false,
2251    //             (imm:i32)<<P:Pred_so_imm>>:$true,
2252    //             (imm:i32):$cc)
2253    // Emits: (MOVCCi:i32 GPR:i32:$false,
2254    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2255    // Pattern complexity = 10  cost = 1  size = 0
2256    if (Subtarget->isThumb()) {
2257      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2258                                        CCVal, CCR, InFlag);
2259      if (!Res)
2260        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2261                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2262      if (Res)
2263        return Res;
2264    } else {
2265      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2266                                         CCVal, CCR, InFlag);
2267      if (!Res)
2268        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2269                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2270      if (Res)
2271        return Res;
2272    }
2273  }
2274
2275  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2276  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2277  // Pattern complexity = 6  cost = 1  size = 0
2278  //
2279  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2280  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2281  // Pattern complexity = 6  cost = 11  size = 0
2282  //
2283  // Also VMOVScc and VMOVDcc.
2284  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2285  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2286  unsigned Opc = 0;
2287  switch (VT.getSimpleVT().SimpleTy) {
2288  default: assert(false && "Illegal conditional move type!");
2289    break;
2290  case MVT::i32:
2291    Opc = Subtarget->isThumb()
2292      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2293      : ARM::MOVCCr;
2294    break;
2295  case MVT::f32:
2296    Opc = ARM::VMOVScc;
2297    break;
2298  case MVT::f64:
2299    Opc = ARM::VMOVDcc;
2300    break;
2301  }
2302  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2303}
2304
2305SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2306  // The only time a CONCAT_VECTORS operation can have legal types is when
2307  // two 64-bit vectors are concatenated to a 128-bit vector.
2308  EVT VT = N->getValueType(0);
2309  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2310    llvm_unreachable("unexpected CONCAT_VECTORS");
2311  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2312}
2313
2314SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2315  SDValue Chain = Node->getOperand(0);
2316  SDValue In1 = Node->getOperand(1);
2317  SDValue In2L = Node->getOperand(2);
2318  SDValue In2H = Node->getOperand(3);
2319  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2320  MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2321  const SDValue Ops[] = { In1, In2L, In2H, Chain};
2322  SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2323                                           MVT::i32, MVT::i32, MVT::Other, Ops,
2324                                           array_lengthof(Ops));
2325  cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2326  return ResNode;
2327}
2328
2329SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2330  DebugLoc dl = N->getDebugLoc();
2331
2332  if (N->isMachineOpcode())
2333    return NULL;   // Already selected.
2334
2335  switch (N->getOpcode()) {
2336  default: break;
2337  case ISD::Constant: {
2338    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2339    bool UseCP = true;
2340    if (Subtarget->hasThumb2())
2341      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2342      // be done with MOV + MOVT, at worst.
2343      UseCP = 0;
2344    else {
2345      if (Subtarget->isThumb()) {
2346        UseCP = (Val > 255 &&                          // MOV
2347                 ~Val > 255 &&                         // MOV + MVN
2348                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2349      } else
2350        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2351                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2352                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2353    }
2354
2355    if (UseCP) {
2356      SDValue CPIdx =
2357        CurDAG->getTargetConstantPool(ConstantInt::get(
2358                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2359                                      TLI.getPointerTy());
2360
2361      SDNode *ResNode;
2362      if (Subtarget->isThumb1Only()) {
2363        SDValue Pred = getAL(CurDAG);
2364        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2365        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2366        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2367                                         Ops, 4);
2368      } else {
2369        SDValue Ops[] = {
2370          CPIdx,
2371          CurDAG->getTargetConstant(0, MVT::i32),
2372          getAL(CurDAG),
2373          CurDAG->getRegister(0, MVT::i32),
2374          CurDAG->getEntryNode()
2375        };
2376        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2377                                       Ops, 5);
2378      }
2379      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2380      return NULL;
2381    }
2382
2383    // Other cases are autogenerated.
2384    break;
2385  }
2386  case ISD::FrameIndex: {
2387    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2388    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2389    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2390    if (Subtarget->isThumb1Only()) {
2391      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2392                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2393      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2394    } else {
2395      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2396                      ARM::t2ADDri : ARM::ADDri);
2397      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2398                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2399                        CurDAG->getRegister(0, MVT::i32) };
2400      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2401    }
2402  }
2403  case ISD::SRL:
2404    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2405      return I;
2406    break;
2407  case ISD::SRA:
2408    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2409      return I;
2410    break;
2411  case ISD::MUL:
2412    if (Subtarget->isThumb1Only())
2413      break;
2414    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2415      unsigned RHSV = C->getZExtValue();
2416      if (!RHSV) break;
2417      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2418        unsigned ShImm = Log2_32(RHSV-1);
2419        if (ShImm >= 32)
2420          break;
2421        SDValue V = N->getOperand(0);
2422        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2423        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2424        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2425        if (Subtarget->isThumb()) {
2426          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2427          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2428        } else {
2429          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2430          return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2431        }
2432      }
2433      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2434        unsigned ShImm = Log2_32(RHSV+1);
2435        if (ShImm >= 32)
2436          break;
2437        SDValue V = N->getOperand(0);
2438        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2439        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2440        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2441        if (Subtarget->isThumb()) {
2442          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2443          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2444        } else {
2445          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2446          return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2447        }
2448      }
2449    }
2450    break;
2451  case ISD::AND: {
2452    // Check for unsigned bitfield extract
2453    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2454      return I;
2455
2456    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2457    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2458    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2459    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2460    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2461    EVT VT = N->getValueType(0);
2462    if (VT != MVT::i32)
2463      break;
2464    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2465      ? ARM::t2MOVTi16
2466      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2467    if (!Opc)
2468      break;
2469    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2470    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2471    if (!N1C)
2472      break;
2473    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2474      SDValue N2 = N0.getOperand(1);
2475      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2476      if (!N2C)
2477        break;
2478      unsigned N1CVal = N1C->getZExtValue();
2479      unsigned N2CVal = N2C->getZExtValue();
2480      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2481          (N1CVal & 0xffffU) == 0xffffU &&
2482          (N2CVal & 0xffffU) == 0x0U) {
2483        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2484                                                  MVT::i32);
2485        SDValue Ops[] = { N0.getOperand(0), Imm16,
2486                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2487        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2488      }
2489    }
2490    break;
2491  }
2492  case ARMISD::VMOVRRD:
2493    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2494                                  N->getOperand(0), getAL(CurDAG),
2495                                  CurDAG->getRegister(0, MVT::i32));
2496  case ISD::UMUL_LOHI: {
2497    if (Subtarget->isThumb1Only())
2498      break;
2499    if (Subtarget->isThumb()) {
2500      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2501                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2502                        CurDAG->getRegister(0, MVT::i32) };
2503      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2504    } else {
2505      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2506                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2507                        CurDAG->getRegister(0, MVT::i32) };
2508      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2509                                    ARM::UMULL : ARM::UMULLv5,
2510                                    dl, MVT::i32, MVT::i32, Ops, 5);
2511    }
2512  }
2513  case ISD::SMUL_LOHI: {
2514    if (Subtarget->isThumb1Only())
2515      break;
2516    if (Subtarget->isThumb()) {
2517      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2518                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2519      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2520    } else {
2521      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2522                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2523                        CurDAG->getRegister(0, MVT::i32) };
2524      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2525                                    ARM::SMULL : ARM::SMULLv5,
2526                                    dl, MVT::i32, MVT::i32, Ops, 5);
2527    }
2528  }
2529  case ISD::LOAD: {
2530    SDNode *ResNode = 0;
2531    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2532      ResNode = SelectT2IndexedLoad(N);
2533    else
2534      ResNode = SelectARMIndexedLoad(N);
2535    if (ResNode)
2536      return ResNode;
2537    // Other cases are autogenerated.
2538    break;
2539  }
2540  case ARMISD::BRCOND: {
2541    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2542    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2543    // Pattern complexity = 6  cost = 1  size = 0
2544
2545    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2546    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2547    // Pattern complexity = 6  cost = 1  size = 0
2548
2549    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2550    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2551    // Pattern complexity = 6  cost = 1  size = 0
2552
2553    unsigned Opc = Subtarget->isThumb() ?
2554      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2555    SDValue Chain = N->getOperand(0);
2556    SDValue N1 = N->getOperand(1);
2557    SDValue N2 = N->getOperand(2);
2558    SDValue N3 = N->getOperand(3);
2559    SDValue InFlag = N->getOperand(4);
2560    assert(N1.getOpcode() == ISD::BasicBlock);
2561    assert(N2.getOpcode() == ISD::Constant);
2562    assert(N3.getOpcode() == ISD::Register);
2563
2564    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2565                               cast<ConstantSDNode>(N2)->getZExtValue()),
2566                               MVT::i32);
2567    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2568    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2569                                             MVT::Glue, Ops, 5);
2570    Chain = SDValue(ResNode, 0);
2571    if (N->getNumValues() == 2) {
2572      InFlag = SDValue(ResNode, 1);
2573      ReplaceUses(SDValue(N, 1), InFlag);
2574    }
2575    ReplaceUses(SDValue(N, 0),
2576                SDValue(Chain.getNode(), Chain.getResNo()));
2577    return NULL;
2578  }
2579  case ARMISD::CMOV:
2580    return SelectCMOVOp(N);
2581  case ARMISD::VZIP: {
2582    unsigned Opc = 0;
2583    EVT VT = N->getValueType(0);
2584    switch (VT.getSimpleVT().SimpleTy) {
2585    default: return NULL;
2586    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2587    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2588    case MVT::v2f32:
2589    case MVT::v2i32: Opc = ARM::VZIPd32; break;
2590    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2591    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2592    case MVT::v4f32:
2593    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2594    }
2595    SDValue Pred = getAL(CurDAG);
2596    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2597    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2598    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2599  }
2600  case ARMISD::VUZP: {
2601    unsigned Opc = 0;
2602    EVT VT = N->getValueType(0);
2603    switch (VT.getSimpleVT().SimpleTy) {
2604    default: return NULL;
2605    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2606    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2607    case MVT::v2f32:
2608    case MVT::v2i32: Opc = ARM::VUZPd32; break;
2609    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2610    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2611    case MVT::v4f32:
2612    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2613    }
2614    SDValue Pred = getAL(CurDAG);
2615    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2616    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2617    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2618  }
2619  case ARMISD::VTRN: {
2620    unsigned Opc = 0;
2621    EVT VT = N->getValueType(0);
2622    switch (VT.getSimpleVT().SimpleTy) {
2623    default: return NULL;
2624    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2625    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2626    case MVT::v2f32:
2627    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2628    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2629    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2630    case MVT::v4f32:
2631    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2632    }
2633    SDValue Pred = getAL(CurDAG);
2634    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2635    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2636    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2637  }
2638  case ARMISD::BUILD_VECTOR: {
2639    EVT VecVT = N->getValueType(0);
2640    EVT EltVT = VecVT.getVectorElementType();
2641    unsigned NumElts = VecVT.getVectorNumElements();
2642    if (EltVT == MVT::f64) {
2643      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2644      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2645    }
2646    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2647    if (NumElts == 2)
2648      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2649    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2650    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2651                     N->getOperand(2), N->getOperand(3));
2652  }
2653
2654  case ARMISD::VLD2DUP: {
2655    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2656                           ARM::VLD2DUPd32Pseudo };
2657    return SelectVLDDup(N, false, 2, Opcodes);
2658  }
2659
2660  case ARMISD::VLD3DUP: {
2661    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2662                           ARM::VLD3DUPd32Pseudo };
2663    return SelectVLDDup(N, false, 3, Opcodes);
2664  }
2665
2666  case ARMISD::VLD4DUP: {
2667    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2668                           ARM::VLD4DUPd32Pseudo };
2669    return SelectVLDDup(N, false, 4, Opcodes);
2670  }
2671
2672  case ARMISD::VLD2DUP_UPD: {
2673    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2674                           ARM::VLD2DUPd32Pseudo_UPD };
2675    return SelectVLDDup(N, true, 2, Opcodes);
2676  }
2677
2678  case ARMISD::VLD3DUP_UPD: {
2679    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2680                           ARM::VLD3DUPd32Pseudo_UPD };
2681    return SelectVLDDup(N, true, 3, Opcodes);
2682  }
2683
2684  case ARMISD::VLD4DUP_UPD: {
2685    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2686                           ARM::VLD4DUPd32Pseudo_UPD };
2687    return SelectVLDDup(N, true, 4, Opcodes);
2688  }
2689
2690  case ARMISD::VLD1_UPD: {
2691    unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
2692                            ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
2693    unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
2694                            ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2695    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2696  }
2697
2698  case ARMISD::VLD2_UPD: {
2699    unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2700                            ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2701    unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2702                            ARM::VLD2q32Pseudo_UPD };
2703    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2704  }
2705
2706  case ARMISD::VLD3_UPD: {
2707    unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2708                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
2709    unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2710                             ARM::VLD3q16Pseudo_UPD,
2711                             ARM::VLD3q32Pseudo_UPD };
2712    unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2713                             ARM::VLD3q16oddPseudo_UPD,
2714                             ARM::VLD3q32oddPseudo_UPD };
2715    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2716  }
2717
2718  case ARMISD::VLD4_UPD: {
2719    unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2720                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
2721    unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2722                             ARM::VLD4q16Pseudo_UPD,
2723                             ARM::VLD4q32Pseudo_UPD };
2724    unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2725                             ARM::VLD4q16oddPseudo_UPD,
2726                             ARM::VLD4q32oddPseudo_UPD };
2727    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2728  }
2729
2730  case ARMISD::VLD2LN_UPD: {
2731    unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2732                            ARM::VLD2LNd32Pseudo_UPD };
2733    unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2734                            ARM::VLD2LNq32Pseudo_UPD };
2735    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2736  }
2737
2738  case ARMISD::VLD3LN_UPD: {
2739    unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2740                            ARM::VLD3LNd32Pseudo_UPD };
2741    unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2742                            ARM::VLD3LNq32Pseudo_UPD };
2743    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2744  }
2745
2746  case ARMISD::VLD4LN_UPD: {
2747    unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2748                            ARM::VLD4LNd32Pseudo_UPD };
2749    unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2750                            ARM::VLD4LNq32Pseudo_UPD };
2751    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2752  }
2753
2754  case ARMISD::VST1_UPD: {
2755    unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2756                            ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2757    unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2758                            ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2759    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2760  }
2761
2762  case ARMISD::VST2_UPD: {
2763    unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2764                            ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2765    unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2766                            ARM::VST2q32Pseudo_UPD };
2767    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2768  }
2769
2770  case ARMISD::VST3_UPD: {
2771    unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2772                            ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2773    unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2774                             ARM::VST3q16Pseudo_UPD,
2775                             ARM::VST3q32Pseudo_UPD };
2776    unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2777                             ARM::VST3q16oddPseudo_UPD,
2778                             ARM::VST3q32oddPseudo_UPD };
2779    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2780  }
2781
2782  case ARMISD::VST4_UPD: {
2783    unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2784                            ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2785    unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2786                             ARM::VST4q16Pseudo_UPD,
2787                             ARM::VST4q32Pseudo_UPD };
2788    unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2789                             ARM::VST4q16oddPseudo_UPD,
2790                             ARM::VST4q32oddPseudo_UPD };
2791    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2792  }
2793
2794  case ARMISD::VST2LN_UPD: {
2795    unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2796                            ARM::VST2LNd32Pseudo_UPD };
2797    unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2798                            ARM::VST2LNq32Pseudo_UPD };
2799    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2800  }
2801
2802  case ARMISD::VST3LN_UPD: {
2803    unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2804                            ARM::VST3LNd32Pseudo_UPD };
2805    unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2806                            ARM::VST3LNq32Pseudo_UPD };
2807    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2808  }
2809
2810  case ARMISD::VST4LN_UPD: {
2811    unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2812                            ARM::VST4LNd32Pseudo_UPD };
2813    unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2814                            ARM::VST4LNq32Pseudo_UPD };
2815    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2816  }
2817
2818  case ISD::INTRINSIC_VOID:
2819  case ISD::INTRINSIC_W_CHAIN: {
2820    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2821    switch (IntNo) {
2822    default:
2823      break;
2824
2825    case Intrinsic::arm_ldrexd: {
2826      SDValue MemAddr = N->getOperand(2);
2827      DebugLoc dl = N->getDebugLoc();
2828      SDValue Chain = N->getOperand(0);
2829
2830      unsigned NewOpc = ARM::LDREXD;
2831      if (Subtarget->isThumb() && Subtarget->hasThumb2())
2832        NewOpc = ARM::t2LDREXD;
2833
2834      // arm_ldrexd returns a i64 value in {i32, i32}
2835      std::vector<EVT> ResTys;
2836      ResTys.push_back(MVT::i32);
2837      ResTys.push_back(MVT::i32);
2838      ResTys.push_back(MVT::Other);
2839
2840      // place arguments in the right order
2841      SmallVector<SDValue, 7> Ops;
2842      Ops.push_back(MemAddr);
2843      Ops.push_back(getAL(CurDAG));
2844      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2845      Ops.push_back(Chain);
2846      SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2847                                          Ops.size());
2848      // Transfer memoperands.
2849      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2850      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2851      cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2852
2853      // Until there's support for specifing explicit register constraints
2854      // like the use of even/odd register pair, hardcode ldrexd to always
2855      // use the pair [R0, R1] to hold the load result.
2856      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
2857                                   SDValue(Ld, 0), SDValue(0,0));
2858      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
2859                                   SDValue(Ld, 1), Chain.getValue(1));
2860
2861      // Remap uses.
2862      SDValue Glue = Chain.getValue(1);
2863      if (!SDValue(N, 0).use_empty()) {
2864        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2865                                                ARM::R0, MVT::i32, Glue);
2866        Glue = Result.getValue(2);
2867        ReplaceUses(SDValue(N, 0), Result);
2868      }
2869      if (!SDValue(N, 1).use_empty()) {
2870        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2871                                                ARM::R1, MVT::i32, Glue);
2872        Glue = Result.getValue(2);
2873        ReplaceUses(SDValue(N, 1), Result);
2874      }
2875
2876      ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
2877      return NULL;
2878    }
2879
2880    case Intrinsic::arm_strexd: {
2881      DebugLoc dl = N->getDebugLoc();
2882      SDValue Chain = N->getOperand(0);
2883      SDValue Val0 = N->getOperand(2);
2884      SDValue Val1 = N->getOperand(3);
2885      SDValue MemAddr = N->getOperand(4);
2886
2887      // Until there's support for specifing explicit register constraints
2888      // like the use of even/odd register pair, hardcode strexd to always
2889      // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
2890      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
2891                                   SDValue(0, 0));
2892      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
2893
2894      SDValue Glue = Chain.getValue(1);
2895      Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2896                                    ARM::R2, MVT::i32, Glue);
2897      Glue = Val0.getValue(1);
2898      Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2899                                    ARM::R3, MVT::i32, Glue);
2900
2901      // Store exclusive double return a i32 value which is the return status
2902      // of the issued store.
2903      std::vector<EVT> ResTys;
2904      ResTys.push_back(MVT::i32);
2905      ResTys.push_back(MVT::Other);
2906
2907      // place arguments in the right order
2908      SmallVector<SDValue, 7> Ops;
2909      Ops.push_back(Val0);
2910      Ops.push_back(Val1);
2911      Ops.push_back(MemAddr);
2912      Ops.push_back(getAL(CurDAG));
2913      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2914      Ops.push_back(Chain);
2915
2916      unsigned NewOpc = ARM::STREXD;
2917      if (Subtarget->isThumb() && Subtarget->hasThumb2())
2918        NewOpc = ARM::t2STREXD;
2919
2920      SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2921                                          Ops.size());
2922      // Transfer memoperands.
2923      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2924      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2925      cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
2926
2927      return St;
2928    }
2929
2930    case Intrinsic::arm_neon_vld1: {
2931      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2932                              ARM::VLD1d32, ARM::VLD1d64 };
2933      unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2934                              ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2935      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
2936    }
2937
2938    case Intrinsic::arm_neon_vld2: {
2939      unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2940                              ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2941      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2942                              ARM::VLD2q32Pseudo };
2943      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
2944    }
2945
2946    case Intrinsic::arm_neon_vld3: {
2947      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2948                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2949      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2950                               ARM::VLD3q16Pseudo_UPD,
2951                               ARM::VLD3q32Pseudo_UPD };
2952      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
2953                               ARM::VLD3q16oddPseudo,
2954                               ARM::VLD3q32oddPseudo };
2955      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2956    }
2957
2958    case Intrinsic::arm_neon_vld4: {
2959      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2960                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2961      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2962                               ARM::VLD4q16Pseudo_UPD,
2963                               ARM::VLD4q32Pseudo_UPD };
2964      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
2965                               ARM::VLD4q16oddPseudo,
2966                               ARM::VLD4q32oddPseudo };
2967      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2968    }
2969
2970    case Intrinsic::arm_neon_vld2lane: {
2971      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2972                              ARM::VLD2LNd32Pseudo };
2973      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2974      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
2975    }
2976
2977    case Intrinsic::arm_neon_vld3lane: {
2978      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2979                              ARM::VLD3LNd32Pseudo };
2980      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2981      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
2982    }
2983
2984    case Intrinsic::arm_neon_vld4lane: {
2985      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2986                              ARM::VLD4LNd32Pseudo };
2987      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2988      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
2989    }
2990
2991    case Intrinsic::arm_neon_vst1: {
2992      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2993                              ARM::VST1d32, ARM::VST1d64 };
2994      unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2995                              ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2996      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
2997    }
2998
2999    case Intrinsic::arm_neon_vst2: {
3000      unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
3001                              ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
3002      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3003                              ARM::VST2q32Pseudo };
3004      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3005    }
3006
3007    case Intrinsic::arm_neon_vst3: {
3008      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
3009                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
3010      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3011                               ARM::VST3q16Pseudo_UPD,
3012                               ARM::VST3q32Pseudo_UPD };
3013      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
3014                               ARM::VST3q16oddPseudo,
3015                               ARM::VST3q32oddPseudo };
3016      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3017    }
3018
3019    case Intrinsic::arm_neon_vst4: {
3020      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
3021                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
3022      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3023                               ARM::VST4q16Pseudo_UPD,
3024                               ARM::VST4q32Pseudo_UPD };
3025      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
3026                               ARM::VST4q16oddPseudo,
3027                               ARM::VST4q32oddPseudo };
3028      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3029    }
3030
3031    case Intrinsic::arm_neon_vst2lane: {
3032      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
3033                              ARM::VST2LNd32Pseudo };
3034      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
3035      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3036    }
3037
3038    case Intrinsic::arm_neon_vst3lane: {
3039      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
3040                              ARM::VST3LNd32Pseudo };
3041      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
3042      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3043    }
3044
3045    case Intrinsic::arm_neon_vst4lane: {
3046      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
3047                              ARM::VST4LNd32Pseudo };
3048      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
3049      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3050    }
3051    }
3052    break;
3053  }
3054
3055  case ISD::INTRINSIC_WO_CHAIN: {
3056    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3057    switch (IntNo) {
3058    default:
3059      break;
3060
3061    case Intrinsic::arm_neon_vtbl2:
3062      return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
3063    case Intrinsic::arm_neon_vtbl3:
3064      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3065    case Intrinsic::arm_neon_vtbl4:
3066      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3067
3068    case Intrinsic::arm_neon_vtbx2:
3069      return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
3070    case Intrinsic::arm_neon_vtbx3:
3071      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3072    case Intrinsic::arm_neon_vtbx4:
3073      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3074    }
3075    break;
3076  }
3077
3078  case ARMISD::VTBL1: {
3079    DebugLoc dl = N->getDebugLoc();
3080    EVT VT = N->getValueType(0);
3081    SmallVector<SDValue, 6> Ops;
3082
3083    Ops.push_back(N->getOperand(0));
3084    Ops.push_back(N->getOperand(1));
3085    Ops.push_back(getAL(CurDAG));                    // Predicate
3086    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3087    return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3088  }
3089  case ARMISD::VTBL2: {
3090    DebugLoc dl = N->getDebugLoc();
3091    EVT VT = N->getValueType(0);
3092
3093    // Form a REG_SEQUENCE to force register allocation.
3094    SDValue V0 = N->getOperand(0);
3095    SDValue V1 = N->getOperand(1);
3096    SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3097
3098    SmallVector<SDValue, 6> Ops;
3099    Ops.push_back(RegSeq);
3100    Ops.push_back(N->getOperand(2));
3101    Ops.push_back(getAL(CurDAG));                    // Predicate
3102    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3103    return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
3104                                  Ops.data(), Ops.size());
3105  }
3106
3107  case ISD::CONCAT_VECTORS:
3108    return SelectConcatVector(N);
3109
3110  case ARMISD::ATOMOR64_DAG:
3111    return SelectAtomic64(N, ARM::ATOMOR6432);
3112  case ARMISD::ATOMXOR64_DAG:
3113    return SelectAtomic64(N, ARM::ATOMXOR6432);
3114  case ARMISD::ATOMADD64_DAG:
3115    return SelectAtomic64(N, ARM::ATOMADD6432);
3116  case ARMISD::ATOMSUB64_DAG:
3117    return SelectAtomic64(N, ARM::ATOMSUB6432);
3118  case ARMISD::ATOMNAND64_DAG:
3119    return SelectAtomic64(N, ARM::ATOMNAND6432);
3120  case ARMISD::ATOMAND64_DAG:
3121    return SelectAtomic64(N, ARM::ATOMAND6432);
3122  case ARMISD::ATOMSWAP64_DAG:
3123    return SelectAtomic64(N, ARM::ATOMSWAP6432);
3124  }
3125
3126  return SelectCode(N);
3127}
3128
3129bool ARMDAGToDAGISel::
3130SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3131                             std::vector<SDValue> &OutOps) {
3132  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3133  // Require the address to be in a register.  That is safe for all ARM
3134  // variants and it is hard to do anything much smarter without knowing
3135  // how the operand is used.
3136  OutOps.push_back(Op);
3137  return false;
3138}
3139
3140/// createARMISelDag - This pass converts a legalized DAG into a
3141/// ARM-specific DAG, ready for instruction scheduling.
3142///
3143FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3144                                     CodeGenOpt::Level OptLevel) {
3145  return new ARMDAGToDAGISel(TM, OptLevel);
3146}
3147