ARMISelDAGToDAG.cpp revision 1c3ef90cab9a563427bdd3c2fcd875c717750562 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMAddressingModes.h"
18#include "ARMTargetMachine.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static cl::opt<bool>
41DisableShifterOp("disable-shifter-op", cl::Hidden,
42  cl::desc("Disable isel of shifter-op"),
43  cl::init(false));
44
45static cl::opt<bool>
46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47  cl::desc("Check fp vmla / vmls hazard at isel time"),
48  cl::init(false));
49
50//===--------------------------------------------------------------------===//
51/// ARMDAGToDAGISel - ARM specific code to select ARM machine
52/// instructions for SelectionDAG operations.
53///
54namespace {
55
56enum AddrMode2Type {
57  AM2_BASE, // Simple AM2 (+-imm12)
58  AM2_SHOP  // Shifter-op AM2
59};
60
61class ARMDAGToDAGISel : public SelectionDAGISel {
62  ARMBaseTargetMachine &TM;
63  const ARMBaseInstrInfo *TII;
64
65  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66  /// make the right decision when generating code for different targets.
67  const ARMSubtarget *Subtarget;
68
69public:
70  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71                           CodeGenOpt::Level OptLevel)
72    : SelectionDAGISel(tm, OptLevel), TM(tm),
73      TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
74      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
75  }
76
77  virtual const char *getPassName() const {
78    return "ARM Instruction Selection";
79  }
80
81  /// getI32Imm - Return a target constant of type i32 with the specified
82  /// value.
83  inline SDValue getI32Imm(unsigned Imm) {
84    return CurDAG->getTargetConstant(Imm, MVT::i32);
85  }
86
87  SDNode *Select(SDNode *N);
88
89
90  bool hasNoVMLxHazardUse(SDNode *N) const;
91  bool isShifterOpProfitable(const SDValue &Shift,
92                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93  bool SelectShifterOperandReg(SDValue N, SDValue &A,
94                               SDValue &B, SDValue &C);
95  bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
96                                    SDValue &B, SDValue &C);
97  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
98  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
99
100  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
101                                      SDValue &Offset, SDValue &Opc);
102  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
103                           SDValue &Opc) {
104    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
105  }
106
107  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
108                           SDValue &Opc) {
109    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
110  }
111
112  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
113                       SDValue &Opc) {
114    SelectAddrMode2Worker(N, Base, Offset, Opc);
115//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
116    // This always matches one way or another.
117    return true;
118  }
119
120  bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
121                             SDValue &Offset, SDValue &Opc);
122  bool SelectAddrMode3(SDValue N, SDValue &Base,
123                       SDValue &Offset, SDValue &Opc);
124  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
125                             SDValue &Offset, SDValue &Opc);
126  bool SelectAddrMode5(SDValue N, SDValue &Base,
127                       SDValue &Offset);
128  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
129
130  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
131
132  // Thumb Addressing Modes:
133  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
134  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
135                             unsigned Scale);
136  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
137  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
138  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
139  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
140                                SDValue &OffImm);
141  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
142                                 SDValue &OffImm);
143  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
144                                 SDValue &OffImm);
145  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
146                                 SDValue &OffImm);
147  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
148
149  // Thumb 2 Addressing Modes:
150  bool SelectT2ShifterOperandReg(SDValue N,
151                                 SDValue &BaseReg, SDValue &Opc);
152  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
153  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
154                            SDValue &OffImm);
155  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
156                                 SDValue &OffImm);
157  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
158                             SDValue &OffReg, SDValue &ShImm);
159
160  inline bool is_so_imm(unsigned Imm) const {
161    return ARM_AM::getSOImmVal(Imm) != -1;
162  }
163
164  inline bool is_so_imm_not(unsigned Imm) const {
165    return ARM_AM::getSOImmVal(~Imm) != -1;
166  }
167
168  inline bool is_t2_so_imm(unsigned Imm) const {
169    return ARM_AM::getT2SOImmVal(Imm) != -1;
170  }
171
172  inline bool is_t2_so_imm_not(unsigned Imm) const {
173    return ARM_AM::getT2SOImmVal(~Imm) != -1;
174  }
175
176  inline bool Pred_so_imm(SDNode *inN) const {
177    ConstantSDNode *N = cast<ConstantSDNode>(inN);
178    return is_so_imm(N->getZExtValue());
179  }
180
181  inline bool Pred_t2_so_imm(SDNode *inN) const {
182    ConstantSDNode *N = cast<ConstantSDNode>(inN);
183    return is_t2_so_imm(N->getZExtValue());
184  }
185
186  // Include the pieces autogenerated from the target description.
187#include "ARMGenDAGISel.inc"
188
189private:
190  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
191  /// ARM.
192  SDNode *SelectARMIndexedLoad(SDNode *N);
193  SDNode *SelectT2IndexedLoad(SDNode *N);
194
195  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
196  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
197  /// loads of D registers and even subregs and odd subregs of Q registers.
198  /// For NumVecs <= 2, QOpcodes1 is not used.
199  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
200                    unsigned *DOpcodes,
201                    unsigned *QOpcodes0, unsigned *QOpcodes1);
202
203  /// SelectVST - Select NEON store intrinsics.  NumVecs should
204  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
205  /// stores of D registers and even subregs and odd subregs of Q registers.
206  /// For NumVecs <= 2, QOpcodes1 is not used.
207  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
208                    unsigned *DOpcodes,
209                    unsigned *QOpcodes0, unsigned *QOpcodes1);
210
211  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
212  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
213  /// load/store of D registers and Q registers.
214  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
215                          bool isUpdating, unsigned NumVecs,
216                          unsigned *DOpcodes, unsigned *QOpcodes);
217
218  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
219  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
220  /// for loading D registers.  (Q registers are not supported.)
221  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
222                       unsigned *Opcodes);
223
224  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
225  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
226  /// generated to force the table registers to be consecutive.
227  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
228
229  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
230  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
231
232  /// SelectCMOVOp - Select CMOV instructions for ARM.
233  SDNode *SelectCMOVOp(SDNode *N);
234  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
235                              ARMCC::CondCodes CCVal, SDValue CCR,
236                              SDValue InFlag);
237  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
238                               ARMCC::CondCodes CCVal, SDValue CCR,
239                               SDValue InFlag);
240  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
241                              ARMCC::CondCodes CCVal, SDValue CCR,
242                              SDValue InFlag);
243  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
244                               ARMCC::CondCodes CCVal, SDValue CCR,
245                               SDValue InFlag);
246
247  SDNode *SelectConcatVector(SDNode *N);
248
249  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
250  /// inline asm expressions.
251  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
252                                            char ConstraintCode,
253                                            std::vector<SDValue> &OutOps);
254
255  // Form pairs of consecutive S, D, or Q registers.
256  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
257  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
258  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
259
260  // Form sequences of 4 consecutive S, D, or Q registers.
261  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
262  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
263  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
264
265  // Get the alignment operand for a NEON VLD or VST instruction.
266  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
267};
268}
269
270/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
271/// operand. If so Imm will receive the 32-bit value.
272static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
273  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
274    Imm = cast<ConstantSDNode>(N)->getZExtValue();
275    return true;
276  }
277  return false;
278}
279
280// isInt32Immediate - This method tests to see if a constant operand.
281// If so Imm will receive the 32 bit value.
282static bool isInt32Immediate(SDValue N, unsigned &Imm) {
283  return isInt32Immediate(N.getNode(), Imm);
284}
285
286// isOpcWithIntImmediate - This method tests to see if the node is a specific
287// opcode and that it has a immediate integer right operand.
288// If so Imm will receive the 32 bit value.
289static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
290  return N->getOpcode() == Opc &&
291         isInt32Immediate(N->getOperand(1).getNode(), Imm);
292}
293
294/// \brief Check whether a particular node is a constant value representable as
295/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
296///
297/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
298static bool isScaledConstantInRange(SDValue Node, unsigned Scale,
299                                    int RangeMin, int RangeMax,
300                                    int &ScaledConstant) {
301  assert(Scale && "Invalid scale!");
302
303  // Check that this is a constant.
304  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
305  if (!C)
306    return false;
307
308  ScaledConstant = (int) C->getZExtValue();
309  if ((ScaledConstant % Scale) != 0)
310    return false;
311
312  ScaledConstant /= Scale;
313  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
314}
315
316/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
317/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
318/// least on current ARM implementations) which should be avoidded.
319bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
320  if (OptLevel == CodeGenOpt::None)
321    return true;
322
323  if (!CheckVMLxHazard)
324    return true;
325
326  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
327    return true;
328
329  if (!N->hasOneUse())
330    return false;
331
332  SDNode *Use = *N->use_begin();
333  if (Use->getOpcode() == ISD::CopyToReg)
334    return true;
335  if (Use->isMachineOpcode()) {
336    const TargetInstrDesc &TID = TII->get(Use->getMachineOpcode());
337    if (TID.mayStore())
338      return true;
339    unsigned Opcode = TID.getOpcode();
340    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
341      return true;
342    // vmlx feeding into another vmlx. We actually want to unfold
343    // the use later in the MLxExpansion pass. e.g.
344    // vmla
345    // vmla (stall 8 cycles)
346    //
347    // vmul (5 cycles)
348    // vadd (5 cycles)
349    // vmla
350    // This adds up to about 18 - 19 cycles.
351    //
352    // vmla
353    // vmul (stall 4 cycles)
354    // vadd adds up to about 14 cycles.
355    return TII->isFpMLxInstruction(Opcode);
356  }
357
358  return false;
359}
360
361bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
362                                            ARM_AM::ShiftOpc ShOpcVal,
363                                            unsigned ShAmt) {
364  if (!Subtarget->isCortexA9())
365    return true;
366  if (Shift.hasOneUse())
367    return true;
368  // R << 2 is free.
369  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
370}
371
372bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
373                                              SDValue &BaseReg,
374                                              SDValue &ShReg,
375                                              SDValue &Opc) {
376  if (DisableShifterOp)
377    return false;
378
379  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
380
381  // Don't match base register only case. That is matched to a separate
382  // lower complexity pattern with explicit register operand.
383  if (ShOpcVal == ARM_AM::no_shift) return false;
384
385  BaseReg = N.getOperand(0);
386  unsigned ShImmVal = 0;
387  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
388    ShReg = CurDAG->getRegister(0, MVT::i32);
389    ShImmVal = RHS->getZExtValue() & 31;
390  } else {
391    ShReg = N.getOperand(1);
392    if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
393      return false;
394  }
395  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
396                                  MVT::i32);
397  return true;
398}
399
400bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
401                                                   SDValue &BaseReg,
402                                                   SDValue &ShReg,
403                                                   SDValue &Opc) {
404  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
405
406  // Don't match base register only case. That is matched to a separate
407  // lower complexity pattern with explicit register operand.
408  if (ShOpcVal == ARM_AM::no_shift) return false;
409
410  BaseReg = N.getOperand(0);
411  unsigned ShImmVal = 0;
412  // Do not check isShifterOpProfitable. This must return true.
413  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
414    ShReg = CurDAG->getRegister(0, MVT::i32);
415    ShImmVal = RHS->getZExtValue() & 31;
416  } else {
417    ShReg = N.getOperand(1);
418  }
419  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
420                                  MVT::i32);
421  return true;
422}
423
424bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
425                                          SDValue &Base,
426                                          SDValue &OffImm) {
427  // Match simple R + imm12 operands.
428
429  // Base only.
430  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
431    if (N.getOpcode() == ISD::FrameIndex) {
432      // Match frame index...
433      int FI = cast<FrameIndexSDNode>(N)->getIndex();
434      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
435      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
436      return true;
437    } else if (N.getOpcode() == ARMISD::Wrapper &&
438               !(Subtarget->useMovt() &&
439                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
440      Base = N.getOperand(0);
441    } else
442      Base = N;
443    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
444    return true;
445  }
446
447  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
448    int RHSC = (int)RHS->getZExtValue();
449    if (N.getOpcode() == ISD::SUB)
450      RHSC = -RHSC;
451
452    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
453      Base   = N.getOperand(0);
454      if (Base.getOpcode() == ISD::FrameIndex) {
455        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
456        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
457      }
458      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
459      return true;
460    }
461  }
462
463  // Base only.
464  Base = N;
465  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
466  return true;
467}
468
469
470
471bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
472                                      SDValue &Opc) {
473  if (N.getOpcode() == ISD::MUL &&
474      (!Subtarget->isCortexA9() || N.hasOneUse())) {
475    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
476      // X * [3,5,9] -> X + X * [2,4,8] etc.
477      int RHSC = (int)RHS->getZExtValue();
478      if (RHSC & 1) {
479        RHSC = RHSC & ~1;
480        ARM_AM::AddrOpc AddSub = ARM_AM::add;
481        if (RHSC < 0) {
482          AddSub = ARM_AM::sub;
483          RHSC = - RHSC;
484        }
485        if (isPowerOf2_32(RHSC)) {
486          unsigned ShAmt = Log2_32(RHSC);
487          Base = Offset = N.getOperand(0);
488          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
489                                                            ARM_AM::lsl),
490                                          MVT::i32);
491          return true;
492        }
493      }
494    }
495  }
496
497  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
498    return false;
499
500  // Leave simple R +/- imm12 operands for LDRi12
501  if (N.getOpcode() == ISD::ADD) {
502    int RHSC;
503    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
504                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
505      return false;
506  }
507
508  if (Subtarget->isCortexA9() && !N.hasOneUse())
509    // Compute R +/- (R << N) and reuse it.
510    return false;
511
512  // Otherwise this is R +/- [possibly shifted] R.
513  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
514  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
515  unsigned ShAmt = 0;
516
517  Base   = N.getOperand(0);
518  Offset = N.getOperand(1);
519
520  if (ShOpcVal != ARM_AM::no_shift) {
521    // Check to see if the RHS of the shift is a constant, if not, we can't fold
522    // it.
523    if (ConstantSDNode *Sh =
524           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
525      ShAmt = Sh->getZExtValue();
526      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
527        Offset = N.getOperand(1).getOperand(0);
528      else {
529        ShAmt = 0;
530        ShOpcVal = ARM_AM::no_shift;
531      }
532    } else {
533      ShOpcVal = ARM_AM::no_shift;
534    }
535  }
536
537  // Try matching (R shl C) + (R).
538  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
539      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
540    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
541    if (ShOpcVal != ARM_AM::no_shift) {
542      // Check to see if the RHS of the shift is a constant, if not, we can't
543      // fold it.
544      if (ConstantSDNode *Sh =
545          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
546        ShAmt = Sh->getZExtValue();
547        if (!Subtarget->isCortexA9() ||
548            (N.hasOneUse() &&
549             isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
550          Offset = N.getOperand(0).getOperand(0);
551          Base = N.getOperand(1);
552        } else {
553          ShAmt = 0;
554          ShOpcVal = ARM_AM::no_shift;
555        }
556      } else {
557        ShOpcVal = ARM_AM::no_shift;
558      }
559    }
560  }
561
562  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
563                                  MVT::i32);
564  return true;
565}
566
567
568
569
570//-----
571
572AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
573                                                     SDValue &Base,
574                                                     SDValue &Offset,
575                                                     SDValue &Opc) {
576  if (N.getOpcode() == ISD::MUL &&
577      (!Subtarget->isCortexA9() || N.hasOneUse())) {
578    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
579      // X * [3,5,9] -> X + X * [2,4,8] etc.
580      int RHSC = (int)RHS->getZExtValue();
581      if (RHSC & 1) {
582        RHSC = RHSC & ~1;
583        ARM_AM::AddrOpc AddSub = ARM_AM::add;
584        if (RHSC < 0) {
585          AddSub = ARM_AM::sub;
586          RHSC = - RHSC;
587        }
588        if (isPowerOf2_32(RHSC)) {
589          unsigned ShAmt = Log2_32(RHSC);
590          Base = Offset = N.getOperand(0);
591          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
592                                                            ARM_AM::lsl),
593                                          MVT::i32);
594          return AM2_SHOP;
595        }
596      }
597    }
598  }
599
600  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
601    Base = N;
602    if (N.getOpcode() == ISD::FrameIndex) {
603      int FI = cast<FrameIndexSDNode>(N)->getIndex();
604      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
605    } else if (N.getOpcode() == ARMISD::Wrapper &&
606               !(Subtarget->useMovt() &&
607                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
608      Base = N.getOperand(0);
609    }
610    Offset = CurDAG->getRegister(0, MVT::i32);
611    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
612                                                      ARM_AM::no_shift),
613                                    MVT::i32);
614    return AM2_BASE;
615  }
616
617  // Match simple R +/- imm12 operands.
618  if (N.getOpcode() == ISD::ADD) {
619    int RHSC;
620    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
621                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
622      Base = N.getOperand(0);
623      if (Base.getOpcode() == ISD::FrameIndex) {
624        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
625        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
626      }
627      Offset = CurDAG->getRegister(0, MVT::i32);
628
629      ARM_AM::AddrOpc AddSub = ARM_AM::add;
630      if (RHSC < 0) {
631        AddSub = ARM_AM::sub;
632        RHSC = - RHSC;
633      }
634      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
635                                                        ARM_AM::no_shift),
636                                      MVT::i32);
637      return AM2_BASE;
638    }
639  }
640
641  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
642    // Compute R +/- (R << N) and reuse it.
643    Base = N;
644    Offset = CurDAG->getRegister(0, MVT::i32);
645    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
646                                                      ARM_AM::no_shift),
647                                    MVT::i32);
648    return AM2_BASE;
649  }
650
651  // Otherwise this is R +/- [possibly shifted] R.
652  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
653  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
654  unsigned ShAmt = 0;
655
656  Base   = N.getOperand(0);
657  Offset = N.getOperand(1);
658
659  if (ShOpcVal != ARM_AM::no_shift) {
660    // Check to see if the RHS of the shift is a constant, if not, we can't fold
661    // it.
662    if (ConstantSDNode *Sh =
663           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
664      ShAmt = Sh->getZExtValue();
665      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
666        Offset = N.getOperand(1).getOperand(0);
667      else {
668        ShAmt = 0;
669        ShOpcVal = ARM_AM::no_shift;
670      }
671    } else {
672      ShOpcVal = ARM_AM::no_shift;
673    }
674  }
675
676  // Try matching (R shl C) + (R).
677  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
678      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
679    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
680    if (ShOpcVal != ARM_AM::no_shift) {
681      // Check to see if the RHS of the shift is a constant, if not, we can't
682      // fold it.
683      if (ConstantSDNode *Sh =
684          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
685        ShAmt = Sh->getZExtValue();
686        if (!Subtarget->isCortexA9() ||
687            (N.hasOneUse() &&
688             isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
689          Offset = N.getOperand(0).getOperand(0);
690          Base = N.getOperand(1);
691        } else {
692          ShAmt = 0;
693          ShOpcVal = ARM_AM::no_shift;
694        }
695      } else {
696        ShOpcVal = ARM_AM::no_shift;
697      }
698    }
699  }
700
701  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
702                                  MVT::i32);
703  return AM2_SHOP;
704}
705
706bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
707                                            SDValue &Offset, SDValue &Opc) {
708  unsigned Opcode = Op->getOpcode();
709  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
710    ? cast<LoadSDNode>(Op)->getAddressingMode()
711    : cast<StoreSDNode>(Op)->getAddressingMode();
712  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
713    ? ARM_AM::add : ARM_AM::sub;
714  int Val;
715  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
716    Offset = CurDAG->getRegister(0, MVT::i32);
717    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
718                                                      ARM_AM::no_shift),
719                                    MVT::i32);
720    return true;
721  }
722
723  Offset = N;
724  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
725  unsigned ShAmt = 0;
726  if (ShOpcVal != ARM_AM::no_shift) {
727    // Check to see if the RHS of the shift is a constant, if not, we can't fold
728    // it.
729    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
730      ShAmt = Sh->getZExtValue();
731      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
732        Offset = N.getOperand(0);
733      else {
734        ShAmt = 0;
735        ShOpcVal = ARM_AM::no_shift;
736      }
737    } else {
738      ShOpcVal = ARM_AM::no_shift;
739    }
740  }
741
742  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
743                                  MVT::i32);
744  return true;
745}
746
747
748bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
749                                      SDValue &Base, SDValue &Offset,
750                                      SDValue &Opc) {
751  if (N.getOpcode() == ISD::SUB) {
752    // X - C  is canonicalize to X + -C, no need to handle it here.
753    Base = N.getOperand(0);
754    Offset = N.getOperand(1);
755    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
756    return true;
757  }
758
759  if (N.getOpcode() != ISD::ADD) {
760    Base = N;
761    if (N.getOpcode() == ISD::FrameIndex) {
762      int FI = cast<FrameIndexSDNode>(N)->getIndex();
763      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
764    }
765    Offset = CurDAG->getRegister(0, MVT::i32);
766    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
767    return true;
768  }
769
770  // If the RHS is +/- imm8, fold into addr mode.
771  int RHSC;
772  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
773                              -256 + 1, 256, RHSC)) { // 8 bits.
774    Base = N.getOperand(0);
775    if (Base.getOpcode() == ISD::FrameIndex) {
776      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
777      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
778    }
779    Offset = CurDAG->getRegister(0, MVT::i32);
780
781    ARM_AM::AddrOpc AddSub = ARM_AM::add;
782    if (RHSC < 0) {
783      AddSub = ARM_AM::sub;
784      RHSC = - RHSC;
785    }
786    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
787    return true;
788  }
789
790  Base = N.getOperand(0);
791  Offset = N.getOperand(1);
792  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
793  return true;
794}
795
796bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
797                                            SDValue &Offset, SDValue &Opc) {
798  unsigned Opcode = Op->getOpcode();
799  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
800    ? cast<LoadSDNode>(Op)->getAddressingMode()
801    : cast<StoreSDNode>(Op)->getAddressingMode();
802  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
803    ? ARM_AM::add : ARM_AM::sub;
804  int Val;
805  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
806    Offset = CurDAG->getRegister(0, MVT::i32);
807    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
808    return true;
809  }
810
811  Offset = N;
812  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
813  return true;
814}
815
816bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
817                                      SDValue &Base, SDValue &Offset) {
818  if (N.getOpcode() != ISD::ADD) {
819    Base = N;
820    if (N.getOpcode() == ISD::FrameIndex) {
821      int FI = cast<FrameIndexSDNode>(N)->getIndex();
822      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
823    } else if (N.getOpcode() == ARMISD::Wrapper &&
824               !(Subtarget->useMovt() &&
825                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
826      Base = N.getOperand(0);
827    }
828    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
829                                       MVT::i32);
830    return true;
831  }
832
833  // If the RHS is +/- imm8, fold into addr mode.
834  int RHSC;
835  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
836                              -256 + 1, 256, RHSC)) {
837    Base = N.getOperand(0);
838    if (Base.getOpcode() == ISD::FrameIndex) {
839      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
840      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
841    }
842
843    ARM_AM::AddrOpc AddSub = ARM_AM::add;
844    if (RHSC < 0) {
845      AddSub = ARM_AM::sub;
846      RHSC = - RHSC;
847    }
848    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
849                                       MVT::i32);
850    return true;
851  }
852
853  Base = N;
854  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
855                                     MVT::i32);
856  return true;
857}
858
859bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
860                                      SDValue &Align) {
861  Addr = N;
862
863  unsigned Alignment = 0;
864  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
865    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
866    // The maximum alignment is equal to the memory size being referenced.
867    unsigned LSNAlign = LSN->getAlignment();
868    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
869    if (LSNAlign > MemSize && MemSize > 1)
870      Alignment = MemSize;
871  } else {
872    // All other uses of addrmode6 are for intrinsics.  For now just record
873    // the raw alignment value; it will be refined later based on the legal
874    // alignment operands for the intrinsic.
875    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
876  }
877
878  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
879  return true;
880}
881
882bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
883                                       SDValue &Offset, SDValue &Label) {
884  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
885    Offset = N.getOperand(0);
886    SDValue N1 = N.getOperand(1);
887    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
888                                      MVT::i32);
889    return true;
890  }
891
892  return false;
893}
894
895
896//===----------------------------------------------------------------------===//
897//                         Thumb Addressing Modes
898//===----------------------------------------------------------------------===//
899
900bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
901                                            SDValue &Base, SDValue &Offset){
902  // FIXME dl should come from the parent load or store, not the address
903  if (N.getOpcode() != ISD::ADD) {
904    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
905    if (!NC || !NC->isNullValue())
906      return false;
907
908    Base = Offset = N;
909    return true;
910  }
911
912  Base = N.getOperand(0);
913  Offset = N.getOperand(1);
914  return true;
915}
916
917bool
918ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
919                                       SDValue &Offset, unsigned Scale) {
920  if (Scale == 4) {
921    SDValue TmpBase, TmpOffImm;
922    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
923      return false;  // We want to select tLDRspi / tSTRspi instead.
924
925    if (N.getOpcode() == ARMISD::Wrapper &&
926        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
927      return false;  // We want to select tLDRpci instead.
928  }
929
930  if (N.getOpcode() != ISD::ADD)
931    return false;
932
933  // Thumb does not have [sp, r] address mode.
934  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
935  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
936  if ((LHSR && LHSR->getReg() == ARM::SP) ||
937      (RHSR && RHSR->getReg() == ARM::SP))
938    return false;
939
940  // FIXME: Why do we explicitly check for a match here and then return false?
941  // Presumably to allow something else to match, but shouldn't this be
942  // documented?
943  int RHSC;
944  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
945    return false;
946
947  Base = N.getOperand(0);
948  Offset = N.getOperand(1);
949  return true;
950}
951
952bool
953ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
954                                          SDValue &Base,
955                                          SDValue &Offset) {
956  return SelectThumbAddrModeRI(N, Base, Offset, 1);
957}
958
959bool
960ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
961                                          SDValue &Base,
962                                          SDValue &Offset) {
963  return SelectThumbAddrModeRI(N, Base, Offset, 2);
964}
965
966bool
967ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
968                                          SDValue &Base,
969                                          SDValue &Offset) {
970  return SelectThumbAddrModeRI(N, Base, Offset, 4);
971}
972
973bool
974ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
975                                          SDValue &Base, SDValue &OffImm) {
976  if (Scale == 4) {
977    SDValue TmpBase, TmpOffImm;
978    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
979      return false;  // We want to select tLDRspi / tSTRspi instead.
980
981    if (N.getOpcode() == ARMISD::Wrapper &&
982        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
983      return false;  // We want to select tLDRpci instead.
984  }
985
986  if (N.getOpcode() != ISD::ADD) {
987    if (N.getOpcode() == ARMISD::Wrapper &&
988        !(Subtarget->useMovt() &&
989          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
990      Base = N.getOperand(0);
991    } else {
992      Base = N;
993    }
994
995    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
996    return true;
997  }
998
999  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1000  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1001  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1002      (RHSR && RHSR->getReg() == ARM::SP)) {
1003    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1004    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1005    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1006    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1007
1008    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1009    if (LHSC != 0 || RHSC != 0) return false;
1010
1011    Base = N;
1012    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1013    return true;
1014  }
1015
1016  // If the RHS is + imm5 * scale, fold into addr mode.
1017  int RHSC;
1018  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1019    Base = N.getOperand(0);
1020    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1021    return true;
1022  }
1023
1024  Base = N.getOperand(0);
1025  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1026  return true;
1027}
1028
1029bool
1030ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1031                                           SDValue &OffImm) {
1032  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1033}
1034
1035bool
1036ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1037                                           SDValue &OffImm) {
1038  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1039}
1040
1041bool
1042ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1043                                           SDValue &OffImm) {
1044  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1045}
1046
1047bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1048                                            SDValue &Base, SDValue &OffImm) {
1049  if (N.getOpcode() == ISD::FrameIndex) {
1050    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1051    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1052    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1053    return true;
1054  }
1055
1056  if (N.getOpcode() != ISD::ADD)
1057    return false;
1058
1059  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1060  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1061      (LHSR && LHSR->getReg() == ARM::SP)) {
1062    // If the RHS is + imm8 * scale, fold into addr mode.
1063    int RHSC;
1064    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1065      Base = N.getOperand(0);
1066      if (Base.getOpcode() == ISD::FrameIndex) {
1067        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1068        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1069      }
1070      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1071      return true;
1072    }
1073  }
1074
1075  return false;
1076}
1077
1078
1079//===----------------------------------------------------------------------===//
1080//                        Thumb 2 Addressing Modes
1081//===----------------------------------------------------------------------===//
1082
1083
1084bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1085                                                SDValue &Opc) {
1086  if (DisableShifterOp)
1087    return false;
1088
1089  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
1090
1091  // Don't match base register only case. That is matched to a separate
1092  // lower complexity pattern with explicit register operand.
1093  if (ShOpcVal == ARM_AM::no_shift) return false;
1094
1095  BaseReg = N.getOperand(0);
1096  unsigned ShImmVal = 0;
1097  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1098    ShImmVal = RHS->getZExtValue() & 31;
1099    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1100    return true;
1101  }
1102
1103  return false;
1104}
1105
1106bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1107                                            SDValue &Base, SDValue &OffImm) {
1108  // Match simple R + imm12 operands.
1109
1110  // Base only.
1111  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
1112    if (N.getOpcode() == ISD::FrameIndex) {
1113      // Match frame index...
1114      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1115      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1116      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1117      return true;
1118    } else if (N.getOpcode() == ARMISD::Wrapper &&
1119               !(Subtarget->useMovt() &&
1120                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1121      Base = N.getOperand(0);
1122      if (Base.getOpcode() == ISD::TargetConstantPool)
1123        return false;  // We want to select t2LDRpci instead.
1124    } else
1125      Base = N;
1126    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1127    return true;
1128  }
1129
1130  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1131    if (SelectT2AddrModeImm8(N, Base, OffImm))
1132      // Let t2LDRi8 handle (R - imm8).
1133      return false;
1134
1135    int RHSC = (int)RHS->getZExtValue();
1136    if (N.getOpcode() == ISD::SUB)
1137      RHSC = -RHSC;
1138
1139    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1140      Base   = N.getOperand(0);
1141      if (Base.getOpcode() == ISD::FrameIndex) {
1142        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1143        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1144      }
1145      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1146      return true;
1147    }
1148  }
1149
1150  // Base only.
1151  Base = N;
1152  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1153  return true;
1154}
1155
1156bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1157                                           SDValue &Base, SDValue &OffImm) {
1158  // Match simple R - imm8 operands.
1159  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
1160    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1161      int RHSC = (int)RHS->getSExtValue();
1162      if (N.getOpcode() == ISD::SUB)
1163        RHSC = -RHSC;
1164
1165      if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1166        Base = N.getOperand(0);
1167        if (Base.getOpcode() == ISD::FrameIndex) {
1168          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1169          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1170        }
1171        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1172        return true;
1173      }
1174    }
1175  }
1176
1177  return false;
1178}
1179
1180bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1181                                                 SDValue &OffImm){
1182  unsigned Opcode = Op->getOpcode();
1183  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1184    ? cast<LoadSDNode>(Op)->getAddressingMode()
1185    : cast<StoreSDNode>(Op)->getAddressingMode();
1186  int RHSC;
1187  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1188    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1189      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1190      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1191    return true;
1192  }
1193
1194  return false;
1195}
1196
1197bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1198                                            SDValue &Base,
1199                                            SDValue &OffReg, SDValue &ShImm) {
1200  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1201  if (N.getOpcode() != ISD::ADD)
1202    return false;
1203
1204  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1205  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1206    int RHSC = (int)RHS->getZExtValue();
1207    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1208      return false;
1209    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1210      return false;
1211  }
1212
1213  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1214    // Compute R + (R << [1,2,3]) and reuse it.
1215    Base = N;
1216    return false;
1217  }
1218
1219  // Look for (R + R) or (R + (R << [1,2,3])).
1220  unsigned ShAmt = 0;
1221  Base   = N.getOperand(0);
1222  OffReg = N.getOperand(1);
1223
1224  // Swap if it is ((R << c) + R).
1225  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1226  if (ShOpcVal != ARM_AM::lsl) {
1227    ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1228    if (ShOpcVal == ARM_AM::lsl)
1229      std::swap(Base, OffReg);
1230  }
1231
1232  if (ShOpcVal == ARM_AM::lsl) {
1233    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1234    // it.
1235    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1236      ShAmt = Sh->getZExtValue();
1237      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1238        OffReg = OffReg.getOperand(0);
1239      else {
1240        ShAmt = 0;
1241        ShOpcVal = ARM_AM::no_shift;
1242      }
1243    } else {
1244      ShOpcVal = ARM_AM::no_shift;
1245    }
1246  }
1247
1248  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1249
1250  return true;
1251}
1252
1253//===--------------------------------------------------------------------===//
1254
1255/// getAL - Returns a ARMCC::AL immediate node.
1256static inline SDValue getAL(SelectionDAG *CurDAG) {
1257  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1258}
1259
1260SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1261  LoadSDNode *LD = cast<LoadSDNode>(N);
1262  ISD::MemIndexedMode AM = LD->getAddressingMode();
1263  if (AM == ISD::UNINDEXED)
1264    return NULL;
1265
1266  EVT LoadedVT = LD->getMemoryVT();
1267  SDValue Offset, AMOpc;
1268  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1269  unsigned Opcode = 0;
1270  bool Match = false;
1271  if (LoadedVT == MVT::i32 &&
1272      SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1273    Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1274    Match = true;
1275  } else if (LoadedVT == MVT::i16 &&
1276             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1277    Match = true;
1278    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1279      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1280      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1281  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1282    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1283      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1284        Match = true;
1285        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1286      }
1287    } else {
1288      if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1289        Match = true;
1290        Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1291      }
1292    }
1293  }
1294
1295  if (Match) {
1296    SDValue Chain = LD->getChain();
1297    SDValue Base = LD->getBasePtr();
1298    SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1299                     CurDAG->getRegister(0, MVT::i32), Chain };
1300    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1301                                  MVT::Other, Ops, 6);
1302  }
1303
1304  return NULL;
1305}
1306
1307SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1308  LoadSDNode *LD = cast<LoadSDNode>(N);
1309  ISD::MemIndexedMode AM = LD->getAddressingMode();
1310  if (AM == ISD::UNINDEXED)
1311    return NULL;
1312
1313  EVT LoadedVT = LD->getMemoryVT();
1314  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1315  SDValue Offset;
1316  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1317  unsigned Opcode = 0;
1318  bool Match = false;
1319  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1320    switch (LoadedVT.getSimpleVT().SimpleTy) {
1321    case MVT::i32:
1322      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1323      break;
1324    case MVT::i16:
1325      if (isSExtLd)
1326        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1327      else
1328        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1329      break;
1330    case MVT::i8:
1331    case MVT::i1:
1332      if (isSExtLd)
1333        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1334      else
1335        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1336      break;
1337    default:
1338      return NULL;
1339    }
1340    Match = true;
1341  }
1342
1343  if (Match) {
1344    SDValue Chain = LD->getChain();
1345    SDValue Base = LD->getBasePtr();
1346    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1347                     CurDAG->getRegister(0, MVT::i32), Chain };
1348    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1349                                  MVT::Other, Ops, 5);
1350  }
1351
1352  return NULL;
1353}
1354
1355/// PairSRegs - Form a D register from a pair of S registers.
1356///
1357SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1358  DebugLoc dl = V0.getNode()->getDebugLoc();
1359  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1360  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1361  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1362  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1363}
1364
1365/// PairDRegs - Form a quad register from a pair of D registers.
1366///
1367SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1368  DebugLoc dl = V0.getNode()->getDebugLoc();
1369  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1370  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1371  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1372  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1373}
1374
1375/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1376///
1377SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1378  DebugLoc dl = V0.getNode()->getDebugLoc();
1379  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1380  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1381  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1382  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1383}
1384
1385/// QuadSRegs - Form 4 consecutive S registers.
1386///
1387SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1388                                   SDValue V2, SDValue V3) {
1389  DebugLoc dl = V0.getNode()->getDebugLoc();
1390  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1391  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1392  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1393  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1394  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1395  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1396}
1397
1398/// QuadDRegs - Form 4 consecutive D registers.
1399///
1400SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1401                                   SDValue V2, SDValue V3) {
1402  DebugLoc dl = V0.getNode()->getDebugLoc();
1403  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1404  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1405  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1406  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1407  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1408  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1409}
1410
1411/// QuadQRegs - Form 4 consecutive Q registers.
1412///
1413SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1414                                   SDValue V2, SDValue V3) {
1415  DebugLoc dl = V0.getNode()->getDebugLoc();
1416  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1417  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1418  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1419  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1420  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1421  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1422}
1423
1424/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1425/// of a NEON VLD or VST instruction.  The supported values depend on the
1426/// number of registers being loaded.
1427SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1428                                       bool is64BitVector) {
1429  unsigned NumRegs = NumVecs;
1430  if (!is64BitVector && NumVecs < 3)
1431    NumRegs *= 2;
1432
1433  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1434  if (Alignment >= 32 && NumRegs == 4)
1435    Alignment = 32;
1436  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1437    Alignment = 16;
1438  else if (Alignment >= 8)
1439    Alignment = 8;
1440  else
1441    Alignment = 0;
1442
1443  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1444}
1445
1446SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1447                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1448                                   unsigned *QOpcodes1) {
1449  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1450  DebugLoc dl = N->getDebugLoc();
1451
1452  SDValue MemAddr, Align;
1453  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1454  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1455    return NULL;
1456
1457  SDValue Chain = N->getOperand(0);
1458  EVT VT = N->getValueType(0);
1459  bool is64BitVector = VT.is64BitVector();
1460  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1461
1462  unsigned OpcodeIndex;
1463  switch (VT.getSimpleVT().SimpleTy) {
1464  default: llvm_unreachable("unhandled vld type");
1465    // Double-register operations:
1466  case MVT::v8i8:  OpcodeIndex = 0; break;
1467  case MVT::v4i16: OpcodeIndex = 1; break;
1468  case MVT::v2f32:
1469  case MVT::v2i32: OpcodeIndex = 2; break;
1470  case MVT::v1i64: OpcodeIndex = 3; break;
1471    // Quad-register operations:
1472  case MVT::v16i8: OpcodeIndex = 0; break;
1473  case MVT::v8i16: OpcodeIndex = 1; break;
1474  case MVT::v4f32:
1475  case MVT::v4i32: OpcodeIndex = 2; break;
1476  case MVT::v2i64: OpcodeIndex = 3;
1477    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1478    break;
1479  }
1480
1481  EVT ResTy;
1482  if (NumVecs == 1)
1483    ResTy = VT;
1484  else {
1485    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1486    if (!is64BitVector)
1487      ResTyElts *= 2;
1488    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1489  }
1490  std::vector<EVT> ResTys;
1491  ResTys.push_back(ResTy);
1492  if (isUpdating)
1493    ResTys.push_back(MVT::i32);
1494  ResTys.push_back(MVT::Other);
1495
1496  SDValue Pred = getAL(CurDAG);
1497  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1498  SDNode *VLd;
1499  SmallVector<SDValue, 7> Ops;
1500
1501  // Double registers and VLD1/VLD2 quad registers are directly supported.
1502  if (is64BitVector || NumVecs <= 2) {
1503    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1504                    QOpcodes0[OpcodeIndex]);
1505    Ops.push_back(MemAddr);
1506    Ops.push_back(Align);
1507    if (isUpdating) {
1508      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1509      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1510    }
1511    Ops.push_back(Pred);
1512    Ops.push_back(Reg0);
1513    Ops.push_back(Chain);
1514    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1515
1516  } else {
1517    // Otherwise, quad registers are loaded with two separate instructions,
1518    // where one loads the even registers and the other loads the odd registers.
1519    EVT AddrTy = MemAddr.getValueType();
1520
1521    // Load the even subregs.  This is always an updating load, so that it
1522    // provides the address to the second load for the odd subregs.
1523    SDValue ImplDef =
1524      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1525    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1526    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1527                                          ResTy, AddrTy, MVT::Other, OpsA, 7);
1528    Chain = SDValue(VLdA, 2);
1529
1530    // Load the odd subregs.
1531    Ops.push_back(SDValue(VLdA, 1));
1532    Ops.push_back(Align);
1533    if (isUpdating) {
1534      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1535      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1536             "only constant post-increment update allowed for VLD3/4");
1537      (void)Inc;
1538      Ops.push_back(Reg0);
1539    }
1540    Ops.push_back(SDValue(VLdA, 0));
1541    Ops.push_back(Pred);
1542    Ops.push_back(Reg0);
1543    Ops.push_back(Chain);
1544    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1545                                 Ops.data(), Ops.size());
1546  }
1547
1548  if (NumVecs == 1)
1549    return VLd;
1550
1551  // Extract out the subregisters.
1552  SDValue SuperReg = SDValue(VLd, 0);
1553  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1554         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1555  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1556  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1557    ReplaceUses(SDValue(N, Vec),
1558                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1559  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1560  if (isUpdating)
1561    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1562  return NULL;
1563}
1564
1565SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1566                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1567                                   unsigned *QOpcodes1) {
1568  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1569  DebugLoc dl = N->getDebugLoc();
1570
1571  SDValue MemAddr, Align;
1572  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1573  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1574  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1575    return NULL;
1576
1577  SDValue Chain = N->getOperand(0);
1578  EVT VT = N->getOperand(Vec0Idx).getValueType();
1579  bool is64BitVector = VT.is64BitVector();
1580  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1581
1582  unsigned OpcodeIndex;
1583  switch (VT.getSimpleVT().SimpleTy) {
1584  default: llvm_unreachable("unhandled vst type");
1585    // Double-register operations:
1586  case MVT::v8i8:  OpcodeIndex = 0; break;
1587  case MVT::v4i16: OpcodeIndex = 1; break;
1588  case MVT::v2f32:
1589  case MVT::v2i32: OpcodeIndex = 2; break;
1590  case MVT::v1i64: OpcodeIndex = 3; break;
1591    // Quad-register operations:
1592  case MVT::v16i8: OpcodeIndex = 0; break;
1593  case MVT::v8i16: OpcodeIndex = 1; break;
1594  case MVT::v4f32:
1595  case MVT::v4i32: OpcodeIndex = 2; break;
1596  case MVT::v2i64: OpcodeIndex = 3;
1597    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1598    break;
1599  }
1600
1601  std::vector<EVT> ResTys;
1602  if (isUpdating)
1603    ResTys.push_back(MVT::i32);
1604  ResTys.push_back(MVT::Other);
1605
1606  SDValue Pred = getAL(CurDAG);
1607  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1608  SmallVector<SDValue, 7> Ops;
1609
1610  // Double registers and VST1/VST2 quad registers are directly supported.
1611  if (is64BitVector || NumVecs <= 2) {
1612    SDValue SrcReg;
1613    if (NumVecs == 1) {
1614      SrcReg = N->getOperand(Vec0Idx);
1615    } else if (is64BitVector) {
1616      // Form a REG_SEQUENCE to force register allocation.
1617      SDValue V0 = N->getOperand(Vec0Idx + 0);
1618      SDValue V1 = N->getOperand(Vec0Idx + 1);
1619      if (NumVecs == 2)
1620        SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1621      else {
1622        SDValue V2 = N->getOperand(Vec0Idx + 2);
1623        // If it's a vst3, form a quad D-register and leave the last part as
1624        // an undef.
1625        SDValue V3 = (NumVecs == 3)
1626          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1627          : N->getOperand(Vec0Idx + 3);
1628        SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1629      }
1630    } else {
1631      // Form a QQ register.
1632      SDValue Q0 = N->getOperand(Vec0Idx);
1633      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1634      SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1635    }
1636
1637    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1638                    QOpcodes0[OpcodeIndex]);
1639    Ops.push_back(MemAddr);
1640    Ops.push_back(Align);
1641    if (isUpdating) {
1642      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1643      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1644    }
1645    Ops.push_back(SrcReg);
1646    Ops.push_back(Pred);
1647    Ops.push_back(Reg0);
1648    Ops.push_back(Chain);
1649    return CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1650  }
1651
1652  // Otherwise, quad registers are stored with two separate instructions,
1653  // where one stores the even registers and the other stores the odd registers.
1654
1655  // Form the QQQQ REG_SEQUENCE.
1656  SDValue V0 = N->getOperand(Vec0Idx + 0);
1657  SDValue V1 = N->getOperand(Vec0Idx + 1);
1658  SDValue V2 = N->getOperand(Vec0Idx + 2);
1659  SDValue V3 = (NumVecs == 3)
1660    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1661    : N->getOperand(Vec0Idx + 3);
1662  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1663
1664  // Store the even D registers.  This is always an updating store, so that it
1665  // provides the address to the second store for the odd subregs.
1666  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1667  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1668                                        MemAddr.getValueType(),
1669                                        MVT::Other, OpsA, 7);
1670  Chain = SDValue(VStA, 1);
1671
1672  // Store the odd D registers.
1673  Ops.push_back(SDValue(VStA, 0));
1674  Ops.push_back(Align);
1675  if (isUpdating) {
1676    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1677    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1678           "only constant post-increment update allowed for VST3/4");
1679    (void)Inc;
1680    Ops.push_back(Reg0);
1681  }
1682  Ops.push_back(RegSeq);
1683  Ops.push_back(Pred);
1684  Ops.push_back(Reg0);
1685  Ops.push_back(Chain);
1686  return CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1687                                Ops.data(), Ops.size());
1688}
1689
1690SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1691                                         bool isUpdating, unsigned NumVecs,
1692                                         unsigned *DOpcodes,
1693                                         unsigned *QOpcodes) {
1694  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1695  DebugLoc dl = N->getDebugLoc();
1696
1697  SDValue MemAddr, Align;
1698  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1699  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1700  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1701    return NULL;
1702
1703  SDValue Chain = N->getOperand(0);
1704  unsigned Lane =
1705    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1706  EVT VT = N->getOperand(Vec0Idx).getValueType();
1707  bool is64BitVector = VT.is64BitVector();
1708
1709  unsigned Alignment = 0;
1710  if (NumVecs != 3) {
1711    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1712    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1713    if (Alignment > NumBytes)
1714      Alignment = NumBytes;
1715    if (Alignment < 8 && Alignment < NumBytes)
1716      Alignment = 0;
1717    // Alignment must be a power of two; make sure of that.
1718    Alignment = (Alignment & -Alignment);
1719    if (Alignment == 1)
1720      Alignment = 0;
1721  }
1722  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1723
1724  unsigned OpcodeIndex;
1725  switch (VT.getSimpleVT().SimpleTy) {
1726  default: llvm_unreachable("unhandled vld/vst lane type");
1727    // Double-register operations:
1728  case MVT::v8i8:  OpcodeIndex = 0; break;
1729  case MVT::v4i16: OpcodeIndex = 1; break;
1730  case MVT::v2f32:
1731  case MVT::v2i32: OpcodeIndex = 2; break;
1732    // Quad-register operations:
1733  case MVT::v8i16: OpcodeIndex = 0; break;
1734  case MVT::v4f32:
1735  case MVT::v4i32: OpcodeIndex = 1; break;
1736  }
1737
1738  std::vector<EVT> ResTys;
1739  if (IsLoad) {
1740    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1741    if (!is64BitVector)
1742      ResTyElts *= 2;
1743    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1744                                      MVT::i64, ResTyElts));
1745  }
1746  if (isUpdating)
1747    ResTys.push_back(MVT::i32);
1748  ResTys.push_back(MVT::Other);
1749
1750  SDValue Pred = getAL(CurDAG);
1751  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1752
1753  SmallVector<SDValue, 8> Ops;
1754  Ops.push_back(MemAddr);
1755  Ops.push_back(Align);
1756  if (isUpdating) {
1757    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1758    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1759  }
1760
1761  SDValue SuperReg;
1762  SDValue V0 = N->getOperand(Vec0Idx + 0);
1763  SDValue V1 = N->getOperand(Vec0Idx + 1);
1764  if (NumVecs == 2) {
1765    if (is64BitVector)
1766      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1767    else
1768      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1769  } else {
1770    SDValue V2 = N->getOperand(Vec0Idx + 2);
1771    SDValue V3 = (NumVecs == 3)
1772      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1773      : N->getOperand(Vec0Idx + 3);
1774    if (is64BitVector)
1775      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1776    else
1777      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1778  }
1779  Ops.push_back(SuperReg);
1780  Ops.push_back(getI32Imm(Lane));
1781  Ops.push_back(Pred);
1782  Ops.push_back(Reg0);
1783  Ops.push_back(Chain);
1784
1785  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1786                                  QOpcodes[OpcodeIndex]);
1787  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1788                                         Ops.data(), Ops.size());
1789  if (!IsLoad)
1790    return VLdLn;
1791
1792  // Extract the subregisters.
1793  SuperReg = SDValue(VLdLn, 0);
1794  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1795         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1796  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1797  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1798    ReplaceUses(SDValue(N, Vec),
1799                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1800  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1801  if (isUpdating)
1802    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1803  return NULL;
1804}
1805
1806SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1807                                      unsigned NumVecs, unsigned *Opcodes) {
1808  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1809  DebugLoc dl = N->getDebugLoc();
1810
1811  SDValue MemAddr, Align;
1812  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1813    return NULL;
1814
1815  SDValue Chain = N->getOperand(0);
1816  EVT VT = N->getValueType(0);
1817
1818  unsigned Alignment = 0;
1819  if (NumVecs != 3) {
1820    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1821    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1822    if (Alignment > NumBytes)
1823      Alignment = NumBytes;
1824    if (Alignment < 8 && Alignment < NumBytes)
1825      Alignment = 0;
1826    // Alignment must be a power of two; make sure of that.
1827    Alignment = (Alignment & -Alignment);
1828    if (Alignment == 1)
1829      Alignment = 0;
1830  }
1831  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1832
1833  unsigned OpcodeIndex;
1834  switch (VT.getSimpleVT().SimpleTy) {
1835  default: llvm_unreachable("unhandled vld-dup type");
1836  case MVT::v8i8:  OpcodeIndex = 0; break;
1837  case MVT::v4i16: OpcodeIndex = 1; break;
1838  case MVT::v2f32:
1839  case MVT::v2i32: OpcodeIndex = 2; break;
1840  }
1841
1842  SDValue Pred = getAL(CurDAG);
1843  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1844  SDValue SuperReg;
1845  unsigned Opc = Opcodes[OpcodeIndex];
1846  SmallVector<SDValue, 6> Ops;
1847  Ops.push_back(MemAddr);
1848  Ops.push_back(Align);
1849  if (isUpdating) {
1850    SDValue Inc = N->getOperand(2);
1851    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1852  }
1853  Ops.push_back(Pred);
1854  Ops.push_back(Reg0);
1855  Ops.push_back(Chain);
1856
1857  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1858  std::vector<EVT> ResTys;
1859  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts));
1860  if (isUpdating)
1861    ResTys.push_back(MVT::i32);
1862  ResTys.push_back(MVT::Other);
1863  SDNode *VLdDup =
1864    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1865  SuperReg = SDValue(VLdDup, 0);
1866
1867  // Extract the subregisters.
1868  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1869  unsigned SubIdx = ARM::dsub_0;
1870  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1871    ReplaceUses(SDValue(N, Vec),
1872                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1873  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
1874  if (isUpdating)
1875    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
1876  return NULL;
1877}
1878
1879SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1880                                    unsigned Opc) {
1881  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1882  DebugLoc dl = N->getDebugLoc();
1883  EVT VT = N->getValueType(0);
1884  unsigned FirstTblReg = IsExt ? 2 : 1;
1885
1886  // Form a REG_SEQUENCE to force register allocation.
1887  SDValue RegSeq;
1888  SDValue V0 = N->getOperand(FirstTblReg + 0);
1889  SDValue V1 = N->getOperand(FirstTblReg + 1);
1890  if (NumVecs == 2)
1891    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1892  else {
1893    SDValue V2 = N->getOperand(FirstTblReg + 2);
1894    // If it's a vtbl3, form a quad D-register and leave the last part as
1895    // an undef.
1896    SDValue V3 = (NumVecs == 3)
1897      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1898      : N->getOperand(FirstTblReg + 3);
1899    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1900  }
1901
1902  SmallVector<SDValue, 6> Ops;
1903  if (IsExt)
1904    Ops.push_back(N->getOperand(1));
1905  Ops.push_back(RegSeq);
1906  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1907  Ops.push_back(getAL(CurDAG)); // predicate
1908  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1909  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1910}
1911
1912SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1913                                                     bool isSigned) {
1914  if (!Subtarget->hasV6T2Ops())
1915    return NULL;
1916
1917  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1918    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1919
1920
1921  // For unsigned extracts, check for a shift right and mask
1922  unsigned And_imm = 0;
1923  if (N->getOpcode() == ISD::AND) {
1924    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1925
1926      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1927      if (And_imm & (And_imm + 1))
1928        return NULL;
1929
1930      unsigned Srl_imm = 0;
1931      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1932                                Srl_imm)) {
1933        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1934
1935        unsigned Width = CountTrailingOnes_32(And_imm);
1936        unsigned LSB = Srl_imm;
1937        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1938        SDValue Ops[] = { N->getOperand(0).getOperand(0),
1939                          CurDAG->getTargetConstant(LSB, MVT::i32),
1940                          CurDAG->getTargetConstant(Width, MVT::i32),
1941          getAL(CurDAG), Reg0 };
1942        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1943      }
1944    }
1945    return NULL;
1946  }
1947
1948  // Otherwise, we're looking for a shift of a shift
1949  unsigned Shl_imm = 0;
1950  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1951    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1952    unsigned Srl_imm = 0;
1953    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1954      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1955      unsigned Width = 32 - Srl_imm;
1956      int LSB = Srl_imm - Shl_imm;
1957      if (LSB < 0)
1958        return NULL;
1959      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1960      SDValue Ops[] = { N->getOperand(0).getOperand(0),
1961                        CurDAG->getTargetConstant(LSB, MVT::i32),
1962                        CurDAG->getTargetConstant(Width, MVT::i32),
1963                        getAL(CurDAG), Reg0 };
1964      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1965    }
1966  }
1967  return NULL;
1968}
1969
1970SDNode *ARMDAGToDAGISel::
1971SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1972                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1973  SDValue CPTmp0;
1974  SDValue CPTmp1;
1975  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1976    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1977    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1978    unsigned Opc = 0;
1979    switch (SOShOp) {
1980    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1981    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1982    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1983    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1984    default:
1985      llvm_unreachable("Unknown so_reg opcode!");
1986      break;
1987    }
1988    SDValue SOShImm =
1989      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1990    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1991    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1992    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1993  }
1994  return 0;
1995}
1996
1997SDNode *ARMDAGToDAGISel::
1998SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1999                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2000  SDValue CPTmp0;
2001  SDValue CPTmp1;
2002  SDValue CPTmp2;
2003  if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2004    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2005    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2006    return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
2007  }
2008  return 0;
2009}
2010
2011SDNode *ARMDAGToDAGISel::
2012SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2013                  ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2014  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2015  if (!T)
2016    return 0;
2017
2018  unsigned Opc = 0;
2019  unsigned TrueImm = T->getZExtValue();
2020  if (is_t2_so_imm(TrueImm)) {
2021    Opc = ARM::t2MOVCCi;
2022  } else if (TrueImm <= 0xffff) {
2023    Opc = ARM::t2MOVCCi16;
2024  } else if (is_t2_so_imm_not(TrueImm)) {
2025    TrueImm = ~TrueImm;
2026    Opc = ARM::t2MVNCCi;
2027  } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2028    // Large immediate.
2029    Opc = ARM::t2MOVCCi32imm;
2030  }
2031
2032  if (Opc) {
2033    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2034    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2035    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2036    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2037  }
2038
2039  return 0;
2040}
2041
2042SDNode *ARMDAGToDAGISel::
2043SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2044                   ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2045  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2046  if (!T)
2047    return 0;
2048
2049  unsigned Opc = 0;
2050  unsigned TrueImm = T->getZExtValue();
2051  bool isSoImm = is_so_imm(TrueImm);
2052  if (isSoImm) {
2053    Opc = ARM::MOVCCi;
2054  } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2055    Opc = ARM::MOVCCi16;
2056  } else if (is_so_imm_not(TrueImm)) {
2057    TrueImm = ~TrueImm;
2058    Opc = ARM::MVNCCi;
2059  } else if (TrueVal.getNode()->hasOneUse() &&
2060             (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2061    // Large immediate.
2062    Opc = ARM::MOVCCi32imm;
2063  }
2064
2065  if (Opc) {
2066    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2067    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2068    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2069    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2070  }
2071
2072  return 0;
2073}
2074
2075SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2076  EVT VT = N->getValueType(0);
2077  SDValue FalseVal = N->getOperand(0);
2078  SDValue TrueVal  = N->getOperand(1);
2079  SDValue CC = N->getOperand(2);
2080  SDValue CCR = N->getOperand(3);
2081  SDValue InFlag = N->getOperand(4);
2082  assert(CC.getOpcode() == ISD::Constant);
2083  assert(CCR.getOpcode() == ISD::Register);
2084  ARMCC::CondCodes CCVal =
2085    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2086
2087  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2088    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2089    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2090    // Pattern complexity = 18  cost = 1  size = 0
2091    SDValue CPTmp0;
2092    SDValue CPTmp1;
2093    SDValue CPTmp2;
2094    if (Subtarget->isThumb()) {
2095      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2096                                        CCVal, CCR, InFlag);
2097      if (!Res)
2098        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2099                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2100      if (Res)
2101        return Res;
2102    } else {
2103      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2104                                         CCVal, CCR, InFlag);
2105      if (!Res)
2106        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2107                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2108      if (Res)
2109        return Res;
2110    }
2111
2112    // Pattern: (ARMcmov:i32 GPR:i32:$false,
2113    //             (imm:i32)<<P:Pred_so_imm>>:$true,
2114    //             (imm:i32):$cc)
2115    // Emits: (MOVCCi:i32 GPR:i32:$false,
2116    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2117    // Pattern complexity = 10  cost = 1  size = 0
2118    if (Subtarget->isThumb()) {
2119      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2120                                        CCVal, CCR, InFlag);
2121      if (!Res)
2122        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2123                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2124      if (Res)
2125        return Res;
2126    } else {
2127      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2128                                         CCVal, CCR, InFlag);
2129      if (!Res)
2130        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2131                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2132      if (Res)
2133        return Res;
2134    }
2135  }
2136
2137  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2138  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2139  // Pattern complexity = 6  cost = 1  size = 0
2140  //
2141  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2142  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2143  // Pattern complexity = 6  cost = 11  size = 0
2144  //
2145  // Also FCPYScc and FCPYDcc.
2146  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2147  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2148  unsigned Opc = 0;
2149  switch (VT.getSimpleVT().SimpleTy) {
2150  default: assert(false && "Illegal conditional move type!");
2151    break;
2152  case MVT::i32:
2153    Opc = Subtarget->isThumb()
2154      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2155      : ARM::MOVCCr;
2156    break;
2157  case MVT::f32:
2158    Opc = ARM::VMOVScc;
2159    break;
2160  case MVT::f64:
2161    Opc = ARM::VMOVDcc;
2162    break;
2163  }
2164  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2165}
2166
2167SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2168  // The only time a CONCAT_VECTORS operation can have legal types is when
2169  // two 64-bit vectors are concatenated to a 128-bit vector.
2170  EVT VT = N->getValueType(0);
2171  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2172    llvm_unreachable("unexpected CONCAT_VECTORS");
2173  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2174}
2175
2176SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2177  DebugLoc dl = N->getDebugLoc();
2178
2179  if (N->isMachineOpcode())
2180    return NULL;   // Already selected.
2181
2182  switch (N->getOpcode()) {
2183  default: break;
2184  case ISD::Constant: {
2185    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2186    bool UseCP = true;
2187    if (Subtarget->hasThumb2())
2188      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2189      // be done with MOV + MOVT, at worst.
2190      UseCP = 0;
2191    else {
2192      if (Subtarget->isThumb()) {
2193        UseCP = (Val > 255 &&                          // MOV
2194                 ~Val > 255 &&                         // MOV + MVN
2195                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2196      } else
2197        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2198                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2199                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2200    }
2201
2202    if (UseCP) {
2203      SDValue CPIdx =
2204        CurDAG->getTargetConstantPool(ConstantInt::get(
2205                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2206                                      TLI.getPointerTy());
2207
2208      SDNode *ResNode;
2209      if (Subtarget->isThumb1Only()) {
2210        SDValue Pred = getAL(CurDAG);
2211        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2212        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2213        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2214                                         Ops, 4);
2215      } else {
2216        SDValue Ops[] = {
2217          CPIdx,
2218          CurDAG->getTargetConstant(0, MVT::i32),
2219          getAL(CurDAG),
2220          CurDAG->getRegister(0, MVT::i32),
2221          CurDAG->getEntryNode()
2222        };
2223        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2224                                       Ops, 5);
2225      }
2226      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2227      return NULL;
2228    }
2229
2230    // Other cases are autogenerated.
2231    break;
2232  }
2233  case ISD::FrameIndex: {
2234    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2235    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2236    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2237    if (Subtarget->isThumb1Only()) {
2238      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
2239                                  CurDAG->getTargetConstant(0, MVT::i32));
2240    } else {
2241      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2242                      ARM::t2ADDri : ARM::ADDri);
2243      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2244                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2245                        CurDAG->getRegister(0, MVT::i32) };
2246      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2247    }
2248  }
2249  case ISD::SRL:
2250    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2251      return I;
2252    break;
2253  case ISD::SRA:
2254    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2255      return I;
2256    break;
2257  case ISD::MUL:
2258    if (Subtarget->isThumb1Only())
2259      break;
2260    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2261      unsigned RHSV = C->getZExtValue();
2262      if (!RHSV) break;
2263      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2264        unsigned ShImm = Log2_32(RHSV-1);
2265        if (ShImm >= 32)
2266          break;
2267        SDValue V = N->getOperand(0);
2268        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2269        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2270        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2271        if (Subtarget->isThumb()) {
2272          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2273          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2274        } else {
2275          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2276          return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2277        }
2278      }
2279      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2280        unsigned ShImm = Log2_32(RHSV+1);
2281        if (ShImm >= 32)
2282          break;
2283        SDValue V = N->getOperand(0);
2284        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2285        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2286        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2287        if (Subtarget->isThumb()) {
2288          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2289          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2290        } else {
2291          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2292          return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2293        }
2294      }
2295    }
2296    break;
2297  case ISD::AND: {
2298    // Check for unsigned bitfield extract
2299    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2300      return I;
2301
2302    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2303    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2304    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2305    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2306    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2307    EVT VT = N->getValueType(0);
2308    if (VT != MVT::i32)
2309      break;
2310    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2311      ? ARM::t2MOVTi16
2312      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2313    if (!Opc)
2314      break;
2315    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2316    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2317    if (!N1C)
2318      break;
2319    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2320      SDValue N2 = N0.getOperand(1);
2321      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2322      if (!N2C)
2323        break;
2324      unsigned N1CVal = N1C->getZExtValue();
2325      unsigned N2CVal = N2C->getZExtValue();
2326      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2327          (N1CVal & 0xffffU) == 0xffffU &&
2328          (N2CVal & 0xffffU) == 0x0U) {
2329        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2330                                                  MVT::i32);
2331        SDValue Ops[] = { N0.getOperand(0), Imm16,
2332                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2333        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2334      }
2335    }
2336    break;
2337  }
2338  case ARMISD::VMOVRRD:
2339    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2340                                  N->getOperand(0), getAL(CurDAG),
2341                                  CurDAG->getRegister(0, MVT::i32));
2342  case ISD::UMUL_LOHI: {
2343    if (Subtarget->isThumb1Only())
2344      break;
2345    if (Subtarget->isThumb()) {
2346      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2347                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2348                        CurDAG->getRegister(0, MVT::i32) };
2349      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2350    } else {
2351      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2352                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2353                        CurDAG->getRegister(0, MVT::i32) };
2354      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2355                                    ARM::UMULL : ARM::UMULLv5,
2356                                    dl, MVT::i32, MVT::i32, Ops, 5);
2357    }
2358  }
2359  case ISD::SMUL_LOHI: {
2360    if (Subtarget->isThumb1Only())
2361      break;
2362    if (Subtarget->isThumb()) {
2363      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2364                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2365      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2366    } else {
2367      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2368                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2369                        CurDAG->getRegister(0, MVT::i32) };
2370      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2371                                    ARM::SMULL : ARM::SMULLv5,
2372                                    dl, MVT::i32, MVT::i32, Ops, 5);
2373    }
2374  }
2375  case ISD::LOAD: {
2376    SDNode *ResNode = 0;
2377    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2378      ResNode = SelectT2IndexedLoad(N);
2379    else
2380      ResNode = SelectARMIndexedLoad(N);
2381    if (ResNode)
2382      return ResNode;
2383    // Other cases are autogenerated.
2384    break;
2385  }
2386  case ARMISD::BRCOND: {
2387    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2388    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2389    // Pattern complexity = 6  cost = 1  size = 0
2390
2391    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2392    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2393    // Pattern complexity = 6  cost = 1  size = 0
2394
2395    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2396    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2397    // Pattern complexity = 6  cost = 1  size = 0
2398
2399    unsigned Opc = Subtarget->isThumb() ?
2400      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2401    SDValue Chain = N->getOperand(0);
2402    SDValue N1 = N->getOperand(1);
2403    SDValue N2 = N->getOperand(2);
2404    SDValue N3 = N->getOperand(3);
2405    SDValue InFlag = N->getOperand(4);
2406    assert(N1.getOpcode() == ISD::BasicBlock);
2407    assert(N2.getOpcode() == ISD::Constant);
2408    assert(N3.getOpcode() == ISD::Register);
2409
2410    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2411                               cast<ConstantSDNode>(N2)->getZExtValue()),
2412                               MVT::i32);
2413    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2414    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2415                                             MVT::Glue, Ops, 5);
2416    Chain = SDValue(ResNode, 0);
2417    if (N->getNumValues() == 2) {
2418      InFlag = SDValue(ResNode, 1);
2419      ReplaceUses(SDValue(N, 1), InFlag);
2420    }
2421    ReplaceUses(SDValue(N, 0),
2422                SDValue(Chain.getNode(), Chain.getResNo()));
2423    return NULL;
2424  }
2425  case ARMISD::CMOV:
2426    return SelectCMOVOp(N);
2427  case ARMISD::CNEG: {
2428    EVT VT = N->getValueType(0);
2429    SDValue N0 = N->getOperand(0);
2430    SDValue N1 = N->getOperand(1);
2431    SDValue N2 = N->getOperand(2);
2432    SDValue N3 = N->getOperand(3);
2433    SDValue InFlag = N->getOperand(4);
2434    assert(N2.getOpcode() == ISD::Constant);
2435    assert(N3.getOpcode() == ISD::Register);
2436
2437    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2438                               cast<ConstantSDNode>(N2)->getZExtValue()),
2439                               MVT::i32);
2440    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2441    unsigned Opc = 0;
2442    switch (VT.getSimpleVT().SimpleTy) {
2443    default: assert(false && "Illegal conditional move type!");
2444      break;
2445    case MVT::f32:
2446      Opc = ARM::VNEGScc;
2447      break;
2448    case MVT::f64:
2449      Opc = ARM::VNEGDcc;
2450      break;
2451    }
2452    return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2453  }
2454
2455  case ARMISD::VZIP: {
2456    unsigned Opc = 0;
2457    EVT VT = N->getValueType(0);
2458    switch (VT.getSimpleVT().SimpleTy) {
2459    default: return NULL;
2460    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2461    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2462    case MVT::v2f32:
2463    case MVT::v2i32: Opc = ARM::VZIPd32; break;
2464    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2465    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2466    case MVT::v4f32:
2467    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2468    }
2469    SDValue Pred = getAL(CurDAG);
2470    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2471    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2472    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2473  }
2474  case ARMISD::VUZP: {
2475    unsigned Opc = 0;
2476    EVT VT = N->getValueType(0);
2477    switch (VT.getSimpleVT().SimpleTy) {
2478    default: return NULL;
2479    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2480    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2481    case MVT::v2f32:
2482    case MVT::v2i32: Opc = ARM::VUZPd32; break;
2483    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2484    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2485    case MVT::v4f32:
2486    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2487    }
2488    SDValue Pred = getAL(CurDAG);
2489    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2490    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2491    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2492  }
2493  case ARMISD::VTRN: {
2494    unsigned Opc = 0;
2495    EVT VT = N->getValueType(0);
2496    switch (VT.getSimpleVT().SimpleTy) {
2497    default: return NULL;
2498    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2499    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2500    case MVT::v2f32:
2501    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2502    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2503    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2504    case MVT::v4f32:
2505    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2506    }
2507    SDValue Pred = getAL(CurDAG);
2508    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2509    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2510    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2511  }
2512  case ARMISD::BUILD_VECTOR: {
2513    EVT VecVT = N->getValueType(0);
2514    EVT EltVT = VecVT.getVectorElementType();
2515    unsigned NumElts = VecVT.getVectorNumElements();
2516    if (EltVT == MVT::f64) {
2517      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2518      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2519    }
2520    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2521    if (NumElts == 2)
2522      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2523    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2524    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2525                     N->getOperand(2), N->getOperand(3));
2526  }
2527
2528  case ARMISD::VLD2DUP: {
2529    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2530                           ARM::VLD2DUPd32Pseudo };
2531    return SelectVLDDup(N, false, 2, Opcodes);
2532  }
2533
2534  case ARMISD::VLD3DUP: {
2535    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2536                           ARM::VLD3DUPd32Pseudo };
2537    return SelectVLDDup(N, false, 3, Opcodes);
2538  }
2539
2540  case ARMISD::VLD4DUP: {
2541    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2542                           ARM::VLD4DUPd32Pseudo };
2543    return SelectVLDDup(N, false, 4, Opcodes);
2544  }
2545
2546  case ARMISD::VLD2DUP_UPD: {
2547    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2548                           ARM::VLD2DUPd32Pseudo_UPD };
2549    return SelectVLDDup(N, true, 2, Opcodes);
2550  }
2551
2552  case ARMISD::VLD3DUP_UPD: {
2553    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2554                           ARM::VLD3DUPd32Pseudo_UPD };
2555    return SelectVLDDup(N, true, 3, Opcodes);
2556  }
2557
2558  case ARMISD::VLD4DUP_UPD: {
2559    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2560                           ARM::VLD4DUPd32Pseudo_UPD };
2561    return SelectVLDDup(N, true, 4, Opcodes);
2562  }
2563
2564  case ARMISD::VLD1_UPD: {
2565    unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
2566                            ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
2567    unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
2568                            ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2569    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2570  }
2571
2572  case ARMISD::VLD2_UPD: {
2573    unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2574                            ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2575    unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2576                            ARM::VLD2q32Pseudo_UPD };
2577    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2578  }
2579
2580  case ARMISD::VLD3_UPD: {
2581    unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2582                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
2583    unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2584                             ARM::VLD3q16Pseudo_UPD,
2585                             ARM::VLD3q32Pseudo_UPD };
2586    unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2587                             ARM::VLD3q16oddPseudo_UPD,
2588                             ARM::VLD3q32oddPseudo_UPD };
2589    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2590  }
2591
2592  case ARMISD::VLD4_UPD: {
2593    unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2594                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
2595    unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2596                             ARM::VLD4q16Pseudo_UPD,
2597                             ARM::VLD4q32Pseudo_UPD };
2598    unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2599                             ARM::VLD4q16oddPseudo_UPD,
2600                             ARM::VLD4q32oddPseudo_UPD };
2601    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2602  }
2603
2604  case ARMISD::VLD2LN_UPD: {
2605    unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2606                            ARM::VLD2LNd32Pseudo_UPD };
2607    unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2608                            ARM::VLD2LNq32Pseudo_UPD };
2609    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2610  }
2611
2612  case ARMISD::VLD3LN_UPD: {
2613    unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2614                            ARM::VLD3LNd32Pseudo_UPD };
2615    unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2616                            ARM::VLD3LNq32Pseudo_UPD };
2617    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2618  }
2619
2620  case ARMISD::VLD4LN_UPD: {
2621    unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2622                            ARM::VLD4LNd32Pseudo_UPD };
2623    unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2624                            ARM::VLD4LNq32Pseudo_UPD };
2625    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2626  }
2627
2628  case ARMISD::VST1_UPD: {
2629    unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2630                            ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2631    unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2632                            ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2633    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2634  }
2635
2636  case ARMISD::VST2_UPD: {
2637    unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2638                            ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2639    unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2640                            ARM::VST2q32Pseudo_UPD };
2641    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2642  }
2643
2644  case ARMISD::VST3_UPD: {
2645    unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2646                            ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2647    unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2648                             ARM::VST3q16Pseudo_UPD,
2649                             ARM::VST3q32Pseudo_UPD };
2650    unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2651                             ARM::VST3q16oddPseudo_UPD,
2652                             ARM::VST3q32oddPseudo_UPD };
2653    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2654  }
2655
2656  case ARMISD::VST4_UPD: {
2657    unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2658                            ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2659    unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2660                             ARM::VST4q16Pseudo_UPD,
2661                             ARM::VST4q32Pseudo_UPD };
2662    unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2663                             ARM::VST4q16oddPseudo_UPD,
2664                             ARM::VST4q32oddPseudo_UPD };
2665    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2666  }
2667
2668  case ARMISD::VST2LN_UPD: {
2669    unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2670                            ARM::VST2LNd32Pseudo_UPD };
2671    unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2672                            ARM::VST2LNq32Pseudo_UPD };
2673    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2674  }
2675
2676  case ARMISD::VST3LN_UPD: {
2677    unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2678                            ARM::VST3LNd32Pseudo_UPD };
2679    unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2680                            ARM::VST3LNq32Pseudo_UPD };
2681    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2682  }
2683
2684  case ARMISD::VST4LN_UPD: {
2685    unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2686                            ARM::VST4LNd32Pseudo_UPD };
2687    unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2688                            ARM::VST4LNq32Pseudo_UPD };
2689    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2690  }
2691
2692  case ISD::INTRINSIC_VOID:
2693  case ISD::INTRINSIC_W_CHAIN: {
2694    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2695    switch (IntNo) {
2696    default:
2697      break;
2698
2699    case Intrinsic::arm_neon_vld1: {
2700      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2701                              ARM::VLD1d32, ARM::VLD1d64 };
2702      unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2703                              ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2704      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
2705    }
2706
2707    case Intrinsic::arm_neon_vld2: {
2708      unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2709                              ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2710      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2711                              ARM::VLD2q32Pseudo };
2712      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
2713    }
2714
2715    case Intrinsic::arm_neon_vld3: {
2716      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2717                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2718      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2719                               ARM::VLD3q16Pseudo_UPD,
2720                               ARM::VLD3q32Pseudo_UPD };
2721      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
2722                               ARM::VLD3q16oddPseudo,
2723                               ARM::VLD3q32oddPseudo };
2724      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2725    }
2726
2727    case Intrinsic::arm_neon_vld4: {
2728      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2729                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2730      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2731                               ARM::VLD4q16Pseudo_UPD,
2732                               ARM::VLD4q32Pseudo_UPD };
2733      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
2734                               ARM::VLD4q16oddPseudo,
2735                               ARM::VLD4q32oddPseudo };
2736      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2737    }
2738
2739    case Intrinsic::arm_neon_vld2lane: {
2740      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2741                              ARM::VLD2LNd32Pseudo };
2742      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2743      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
2744    }
2745
2746    case Intrinsic::arm_neon_vld3lane: {
2747      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2748                              ARM::VLD3LNd32Pseudo };
2749      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2750      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
2751    }
2752
2753    case Intrinsic::arm_neon_vld4lane: {
2754      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2755                              ARM::VLD4LNd32Pseudo };
2756      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2757      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
2758    }
2759
2760    case Intrinsic::arm_neon_vst1: {
2761      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2762                              ARM::VST1d32, ARM::VST1d64 };
2763      unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2764                              ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2765      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
2766    }
2767
2768    case Intrinsic::arm_neon_vst2: {
2769      unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2770                              ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2771      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2772                              ARM::VST2q32Pseudo };
2773      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
2774    }
2775
2776    case Intrinsic::arm_neon_vst3: {
2777      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2778                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2779      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2780                               ARM::VST3q16Pseudo_UPD,
2781                               ARM::VST3q32Pseudo_UPD };
2782      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
2783                               ARM::VST3q16oddPseudo,
2784                               ARM::VST3q32oddPseudo };
2785      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2786    }
2787
2788    case Intrinsic::arm_neon_vst4: {
2789      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2790                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2791      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2792                               ARM::VST4q16Pseudo_UPD,
2793                               ARM::VST4q32Pseudo_UPD };
2794      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
2795                               ARM::VST4q16oddPseudo,
2796                               ARM::VST4q32oddPseudo };
2797      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2798    }
2799
2800    case Intrinsic::arm_neon_vst2lane: {
2801      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2802                              ARM::VST2LNd32Pseudo };
2803      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2804      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
2805    }
2806
2807    case Intrinsic::arm_neon_vst3lane: {
2808      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2809                              ARM::VST3LNd32Pseudo };
2810      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2811      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
2812    }
2813
2814    case Intrinsic::arm_neon_vst4lane: {
2815      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2816                              ARM::VST4LNd32Pseudo };
2817      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2818      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
2819    }
2820    }
2821    break;
2822  }
2823
2824  case ISD::INTRINSIC_WO_CHAIN: {
2825    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2826    switch (IntNo) {
2827    default:
2828      break;
2829
2830    case Intrinsic::arm_neon_vtbl2:
2831      return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2832    case Intrinsic::arm_neon_vtbl3:
2833      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2834    case Intrinsic::arm_neon_vtbl4:
2835      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2836
2837    case Intrinsic::arm_neon_vtbx2:
2838      return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2839    case Intrinsic::arm_neon_vtbx3:
2840      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2841    case Intrinsic::arm_neon_vtbx4:
2842      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2843    }
2844    break;
2845  }
2846
2847  case ISD::CONCAT_VECTORS:
2848    return SelectConcatVector(N);
2849  }
2850
2851  return SelectCode(N);
2852}
2853
2854bool ARMDAGToDAGISel::
2855SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2856                             std::vector<SDValue> &OutOps) {
2857  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2858  // Require the address to be in a register.  That is safe for all ARM
2859  // variants and it is hard to do anything much smarter without knowing
2860  // how the operand is used.
2861  OutOps.push_back(Op);
2862  return false;
2863}
2864
2865/// createARMISelDag - This pass converts a legalized DAG into a
2866/// ARM-specific DAG, ready for instruction scheduling.
2867///
2868FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2869                                     CodeGenOpt::Level OptLevel) {
2870  return new ARMDAGToDAGISel(TM, OptLevel);
2871}
2872