Lines Matching defs:Reg0

1782   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1794 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1802 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1805 Ops.push_back(Reg0);
1818 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1831 Ops.push_back(Reg0);
1835 Ops.push_back(Reg0);
1908 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1944 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1952 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1956 Ops.push_back(Reg0);
1980 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1995 Ops.push_back(Reg0);
1999 Ops.push_back(Reg0);
2071 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2078 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2102 Ops.push_back(Reg0);
2167 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2181 Ops.push_back(Reg0);
2184 Ops.push_back(Reg0);
2269 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2277 getAL(CurDAG), Reg0, Reg0 };
2287 getAL(CurDAG), Reg0, Reg0 };
2294 getAL(CurDAG), Reg0 };
2313 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2317 getAL(CurDAG), Reg0 };
2699 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2701 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2704 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2715 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2717 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2720 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
3557 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3580 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3596 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,