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Searched defs:Insn (Results 1 - 9 of 9) sorted by relevance

/external/dexmaker/src/dx/java/com/android/dx/rop/code/
H A D	Insn.java	`30 public abstract class Insn implements ToHuman { class in inherits:ToHuman 51 public Insn(Rop opcode, SourcePosition position, RegisterSpec result, method in class:Insn 225 public abstract Insn withAddedCatch(Type type); 234 public abstract Insn withRegisterOffset(int delta); 245 public Insn withSourceLiteral() { 250 * Returns an exact copy of this Insn 254 public Insn copy() { 271 * Compares Insn contents, since {@code Insn.equals()} is defined 272 * to be an identity compare. Insn' [all...]`
/external/llvm/utils/TableGen/
H A D	PseudoLoweringEmitter.cpp	`55 CodeGenInstruction &Insn, 73 addDagOperandMapping(Record Rec, DagInit Dag, CodeGenInstruction &Insn, argument 92 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) 96 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 100 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 102 OpsAdded += Insn.Operands[i].MINumOperands; 111 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); 139 CodeGenInstruction Insn(Operator); 141 if (Insn.isCodeGenOnly \|\| Insn [all...]`
H A D	FixedLenDecoderEmitter.cpp	`374 void insnWithID(insn_t &Insn, unsigned Opcode) const { argument 387 Insn.push_back(BIT_UNSET); 389 Insn.push_back(bitFromBits(Bits, i)); 403 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit, 434 const insn_t &Insn) const; 511 insn_t Insn; local 514 Owner->insnWithID(Insn, Owner->Opcodes[i]); 518 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits); 931 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, 936 if (Insn[StartBi [all...]`
/external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/
H A D	gen_x86_insn.py	`380 class Insn(object): class in inherits:object 461 return Insn(self.groupname, 505 opts.append(Insn(groupname, **kwargs))`
/external/llvm/lib/Target/Mips/Disassembler/
H A D	MipsDisassembler.cpp	132 unsigned Insn, 162 unsigned Insn, 167 unsigned Insn, 171 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 176 unsigned Insn, 181 unsigned Insn, 186 unsigned Insn, 274 uint32_t Insn; local 277 Insn, isBigEndian); 282 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Addres 299 uint32_t Insn; local 415 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 437 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 526 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 537 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 545 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 556 DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument [all...]
/external/llvm/lib/Target/XCore/Disassembler/
H A D	XCoreDisassembler.cpp	104 unsigned Insn, 109 unsigned Insn, 114 unsigned Insn, 119 unsigned Insn, 124 unsigned Insn, 129 unsigned Insn, 134 unsigned Insn, 139 unsigned Insn, 144 unsigned Insn, 149 unsigned Insn, 252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) argument 270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3) argument 286 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 356 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 369 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 382 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 395 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 409 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 422 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 435 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 449 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 520 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 534 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 548 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 561 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 574 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 587 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 600 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 614 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 629 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 643 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 657 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 677 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 691 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 711 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 730 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument [all...]
/external/llvm/lib/Target/AArch64/Disassembler/
H A D	AArch64Disassembler.cpp	141 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 145 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 150 unsigned Insn, 471 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, argument 474 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 475 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 476 unsigned ImmS = fieldFromInstruction(Insn, 10, 6); 477 unsigned ImmR = fieldFromInstruction(Insn, 16, 6); 478 unsigned SF = fieldFromInstruction(Insn, 31, 1); 483 Opc = (OpcTypes)fieldFromInstruction(Insn, 2 563 DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 587 DecodeLDSTPairInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 751 DecodeSingleIndexedInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...]
/external/llvm/lib/Transforms/Scalar/
H A D	CodeGenPrepare.cpp	`332 Instruction Insn = dyn_cast<Instruction>(UPN->getIncomingValue(I)); local 333 if (Insn && Insn->getParent() == BB && 334 Insn->getParent() != UPN->getIncomingBlock(I)) 1989 Instruction Insn = BI; ++BI; local 1990 DbgValueInst *DVI = dyn_cast<DbgValueInst>(Insn); 1992 PrevNonDbgInst = Insn;`
/external/llvm/lib/Target/ARM/Disassembler/
H A D	ARMDisassembler.cpp	201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 206 unsigned Insn, 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 219 unsigned Insn, 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1295 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1440 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1589 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1780 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1809 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1832 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1923 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1970 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2012 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2036 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2063 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2136 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2163 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2206 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2480 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2493 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2508 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2521 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2531 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2802 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2849 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2897 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2932 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2987 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3032 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3075 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3111 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void Decoder) argument 3234 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3305 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3369 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3434 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3473 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3621 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3708 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void Decoder) argument 3719 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void Decoder) argument 3744 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void Decoder) argument 3755 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3802 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3818 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3948 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3969 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3994 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4019 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4047 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4072 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4097 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4164 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4230 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4297 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4361 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4431 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4495 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4576 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4648 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4674 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4700 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4720 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4757 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4791 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void Decoder) argument 4817 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4844 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4874 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4904 DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...]

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