Searched defs:Vd (Results 1 - 5 of 5) sorted by relevance
/external/chromium_org/v8/src/arm/ |
H A D | disasm-arm.cc | 113 void FormatNeonList(int Vd, int type); 391 // vmov.32 has Vd in a different place. 423 void Decoder::FormatNeonList(int Vd, int type) { argument 426 "{d%d}", Vd); 429 "{d%d, d%d}", Vd, Vd + 1); 432 "{d%d, d%d, d%d}", Vd, Vd + 1, Vd + 2); 435 "{d%d, d%d, d%d, d%d}", Vd, V 1569 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local 1582 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local 1594 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local 1607 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local [all...] |
H A D | assembler-arm.cc | 2106 // Vd(15-12) | 1011(11-8) | offset 2192 // Vd(15-12) | 1011(11-8) | (offset/4) 2421 // Vd(15-12) | 101(11-9) | sz=1(8) | imm4L(3-0) 2497 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0000(19-16) | Vd(15-12) | 2515 // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0) 2675 int D, Vd, M, Vm; local 2677 SplitRegCode(dst_type, dst_code, &Vd, &D); 2683 // Vd(15-12) | 101(11-9) | sz(8) | op(7) | 1(6) | M(5) | 0(4) | Vm(3-0) 2700 Vd*B12 | 0x5*B9 | sz*B8 | op*B7 | B6 | M*B5 | Vm); 2705 // Vd(1 [all...] |
H A D | simulator-arm.cc | 3458 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local 3472 set_q_register(Vd, reinterpret_cast<uint64_t*>(to)); 3481 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local 3495 set_q_register(Vd, reinterpret_cast<uint64_t*>(to)); 3503 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local 3529 get_d_register(Vd + r, data); 3544 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local 3572 set_d_register(Vd + r, data);
|
/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1223 unsigned Vd = fieldFromInstruction(Val, 8, 5); local 1227 if (regs == 0 || (Vd + regs) > 32) { 1228 regs = Vd + regs > 32 ? 32 - Vd : regs; 1233 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1236 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1247 unsigned Vd = fieldFromInstruction(Val, 8, 5); local 1251 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1252 regs = Vd + regs > 32 ? 32 - Vd 4846 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); local 4876 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); local [all...] |
/external/valgrind/main/VEX/priv/ |
H A D | guest_arm_toIR.c | 12334 cond 1110 1D11 1p1U Vd 101f x1i0 imm4 12349 UInt Vd = INSN(15,12); local 12359 UInt d = dp_op ? ((bD << 4) | Vd) : ((Vd << 1) | bD);
|
Completed in 277 milliseconds