/external/valgrind/main/VEX/priv/ |
H A D | host_amd64_defs.c | 178 HChar* showAMD64CondCode ( AMD64CondCode cond ) 180 switch (cond) { 696 AMD64Instr* AMD64Instr_Call ( AMD64CondCode cond, Addr64 target, Int regparms ) { argument 699 i->Ain.Call.cond = cond; 707 AMD64CondCode cond, Bool toFastEP ) { 712 i->Ain.XDirect.cond = cond; 717 AMD64CondCode cond ) { 722 i->Ain.XIndir.cond 706 AMD64Instr_XDirect( Addr64 dstGA, AMD64AMode* amRIP, AMD64CondCode cond, Bool toFastEP ) argument 725 AMD64Instr_XAssisted( HReg dstGA, AMD64AMode* amRIP, AMD64CondCode cond, IRJumpKind jk ) argument 736 AMD64Instr_CMov64( AMD64CondCode cond, AMD64RM* src, HReg dst ) argument 773 AMD64Instr_Set64( AMD64CondCode cond, HReg dst ) argument 961 AMD64Instr_SseCMov( AMD64CondCode cond, HReg src, HReg dst ) argument [all...] |
H A D | host_arm_isel.c | 1573 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); local 1575 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); 1581 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); local 1584 perhaps mvn{cond} dst, #0 as the second insn? 1587 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); 1599 //zz X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg); 1600 //zz addInstr(env, X86Instr_Set32(cond,dst)); 1767 IRExpr* cond = e->Iex.Mux0X.cond; local 1771 && cond 2019 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); local 5802 ARMCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data); local [all...] |
H A D | host_mips_defs.h | 463 MIPSCondCode cond; member in struct:__anon27620::__anon27621::__anon27626 485 If cond is != Mcc_ALWAYS, src is checked. 488 MIPSCondCode cond; member in struct:__anon27620::__anon27621::__anon27629 499 MIPSCondCode cond; /* can be MIPScc_AL */ member in struct:__anon27620::__anon27621::__anon27630 507 MIPSCondCode cond; /* can be MIPScc_AL */ member in struct:__anon27620::__anon27621::__anon27631 514 MIPSCondCode cond; /* can be MIPScc_AL */ member in struct:__anon27620::__anon27621::__anon27632 608 MIPSCondCode cond; member in struct:__anon27620::__anon27621::__anon27647 657 MIPSCondCode cond, Bool toFastEP); 659 MIPSCondCode cond); 661 MIPSCondCode cond, IRJumpKin [all...] |
H A D | host_s390_defs.h | 259 s390_cc_invert(s390_cc_t cond) argument 261 return S390_CC_ALWAYS - cond; 282 s390_cc_t cond; member in struct:__anon27759::__anon27760::__anon27764 338 s390_cc_t cond; member in struct:__anon27759::__anon27760::__anon27775 364 s390_cc_t cond; member in struct:__anon27759::__anon27760::__anon27778 428 s390_cc_t cond; member in struct:__anon27759::__anon27760::__anon27787 436 s390_cc_t cond; member in struct:__anon27759::__anon27760::__anon27788 443 s390_cc_t cond; member in struct:__anon27759::__anon27760::__anon27789 466 s390_insn *s390_insn_cond_move(UChar size, s390_cc_t cond, HReg dst, 489 s390_insn *s390_insn_helper_call(s390_cc_t cond, Addr6 [all...] |
H A D | host_s390_isel.c | 1159 s390_cc_t cond = s390_isel_cc(env, arg); local 1161 addInstr(env, s390_insn_cc2bool(dst, cond)); 1385 s390_opnd_RMI cond, r0, zero; local 1387 cond_expr = expr->Iex.Mux0X.cond; 1406 cond = s390_isel_int_expr_RMI(env, cond_expr); 1408 /* tmp = cond & 0xFF */ 1411 addInstr(env, s390_insn_alu(4, S390_ALU_AND, tmp, cond)); 2003 s390_isel_cc(ISelEnv *env, IRExpr *cond) argument 2007 vassert(typeOfIRExpr(env->type_env, cond) == Ity_I1); 2010 if (cond 2411 s390_cc_t cond = s390_isel_cc(env, stmt->Ist.WrTmp.data); local 2545 s390_cc_t cond; local [all...] |
H A D | host_x86_defs.c | 134 HChar* showX86CondCode ( X86CondCode cond ) 136 switch (cond) { 641 X86Instr* X86Instr_Call ( X86CondCode cond, Addr32 target, Int regparms ) { argument 644 i->Xin.Call.cond = cond; 651 X86CondCode cond, Bool toFastEP ) { 656 i->Xin.XDirect.cond = cond; 661 X86CondCode cond ) { 666 i->Xin.XIndir.cond 650 X86Instr_XDirect( Addr32 dstGA, X86AMode* amEIP, X86CondCode cond, Bool toFastEP ) argument 669 X86Instr_XAssisted( HReg dstGA, X86AMode* amEIP, X86CondCode cond, IRJumpKind jk ) argument 679 X86Instr_CMov32( X86CondCode cond, X86RM* src, HReg dst ) argument 708 X86Instr_Set32( X86CondCode cond, HReg dst ) argument 793 X86Instr_FpCMov( X86CondCode cond, HReg src, HReg dst ) argument 891 X86Instr_SseCMov( X86CondCode cond, HReg src, HReg dst ) argument [all...] |
H A D | host_x86_isel.c | 1198 X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg); local 1199 addInstr(env, X86Instr_Set32(cond,dst)); 1207 X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg); local 1208 addInstr(env, X86Instr_Set32(cond,dst)); 1371 && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) { 1377 r8 = iselIntExpr_RM(env, e->Iex.Mux0X.cond); 2035 r8 = iselIntExpr_RM(env, e->Iex.Mux0X.cond); 2055 r8 = iselIntExpr_RM(env, e->Iex.Mux0X.cond); 2078 r8 = iselIntExpr_RM(env, e->Iex.Mux0X.cond); 2573 X86CondCode cond local 3912 X86CondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data); local [all...] |
H A D | ir_defs.c | 1114 ppIRExpr(e->Iex.Mux0X.cond); 1580 IRExpr* IRExpr_Mux0X ( IRExpr* cond, IRExpr* expr0, IRExpr* exprX ) { argument 1583 e->Iex.Mux0X.cond = cond; 1969 return IRExpr_Mux0X(deepCopyIRExpr(e->Iex.Mux0X.cond), 3067 isIRAtom(e->Iex.Mux0X.cond) 3237 useBeforeDef_Expr(bb,stmt,expr->Iex.Mux0X.cond,def_counts); 3498 tcExpr(bb,stmt, expr->Iex.Mux0X.cond, gWordTy); 3501 if (typeOfIRExpr(tyenv, expr->Iex.Mux0X.cond) != Ity_I8) 3502 sanityCheckFail(bb,stmt,"Iex.Mux0X.cond [all...] |
H A D | guest_amd64_helpers.c | 735 ULong amd64g_calculate_condition ( ULong/*AMD64Condcode*/ cond, argument 744 ULong inv = cond & 1; 748 tab_cond[cc_op][cond]++; 753 switch (cond) { 806 cond, cc_op, cc_dep1, cc_dep2, cc_ndep ); 900 IRExpr *cond, *cc_op, *cc_dep1, *cc_dep2; local 902 cond = args[0]; 909 if (isU64(cc_op, AMD64G_CC_OP_ADDQ) && isU64(cond, AMD64CondZ)) { 919 if (isU64(cc_op, AMD64G_CC_OP_SUBQ) && isU64(cond, AMD64CondZ)) { 924 if (isU64(cc_op, AMD64G_CC_OP_SUBQ) && isU64(cond, AMD64CondN [all...] |
H A D | host_amd64_defs.h | 470 AMD64CondCode cond; member in struct:__anon27441::__anon27442::__anon27454 479 AMD64CondCode cond; /* can be Acc_ALWAYS */ member in struct:__anon27441::__anon27442::__anon27455 487 AMD64CondCode cond; /* can be Acc_ALWAYS */ member in struct:__anon27441::__anon27442::__anon27456 494 AMD64CondCode cond; /* can be Acc_ALWAYS */ member in struct:__anon27441::__anon27442::__anon27457 500 AMD64CondCode cond; member in struct:__anon27441::__anon27442::__anon27458 525 AMD64CondCode cond; member in struct:__anon27441::__anon27442::__anon27462 657 AMD64CondCode cond; member in struct:__anon27441::__anon27442::__anon27484 703 AMD64CondCode cond, Bool toFastEP ); 705 AMD64CondCode cond ); 707 AMD64CondCode cond, IRJumpKin [all...] |
H A D | host_amd64_isel.c | 1425 AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg); local 1426 addInstr(env, AMD64Instr_Set64(cond,dst)); 1435 AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg); local 1436 addInstr(env, AMD64Instr_Set64(cond,dst)); 1702 && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) { 1708 r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond); 2792 vassert(typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8); 2793 r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond); 3367 HReg r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond); 3861 AMD64CondCode cond local [all...] |
/external/valgrind/main/VEX/ |
H A D | test_main.c | 1022 IRAtom* cond; local 1038 cond = mkPCastTo( mce, Ity_I1, vatom ); 1039 /* cond will be 0 if all defined, and 1 if any not defined. */ 1071 di->guard = cond; 2091 IRAtom* cond, IRAtom* expr0, IRAtom* exprX ) 2095 /* Given Mux0X(cond,expr0,exprX), generate 2096 Mux0X(cond,expr0#,exprX#) `UifU` PCast(cond#) 2100 tl_assert(isOriginalAtom(mce, cond)); 2104 vbitsC = expr2vbits(mce, cond); 2090 expr2vbits_Mux0X( MCEnv* mce, IRAtom* cond, IRAtom* expr0, IRAtom* exprX ) argument [all...] |
/external/blktrace/ |
H A D | blktrace.c | 522 static void t_pthread_cond_wait(pthread_cond_t *cond, pthread_mutex_t *mutex) argument 527 pthread_cond_timedwait(cond, mutex, &ts);
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/external/chromium_org/third_party/angle/src/compiler/ |
H A D | intermediate.h | 298 cond(aCond), 310 TIntermTyped* getCondition() { return cond; } 320 TIntermTyped* cond; // loop exit condition member in class:TIntermLoop 537 TIntermSelection(TIntermTyped* cond, TIntermNode* trueB, TIntermNode* falseB) : argument 538 TIntermTyped(TType(EbtVoid, EbpUndefined)), condition(cond), trueBlock(trueB), falseBlock(falseB) {} 539 TIntermSelection(TIntermTyped* cond, TIntermNode* trueB, TIntermNode* falseB, const TType& type) : argument 540 TIntermTyped(type), condition(cond), trueBlock(trueB), falseBlock(falseB) {}
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/external/chromium_org/v8/src/arm/ |
H A D | assembler-arm.h | 844 void b(int branch_offset, Condition cond = al); 845 void bl(int branch_offset, Condition cond = al); 847 void blx(Register target, Condition cond = al); // v5 and above 848 void bx(Register target, Condition cond = al); // v5 and above, plus v4t 851 void b(Label* L, Condition cond = al) { 852 b(branch_offset(L, cond == al), cond); local 854 void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); } local 855 void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); } local 856 void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); } local [all...] |
H A D | constants-arm.h | 109 inline Condition NegateCondition(Condition cond) { argument 110 ASSERT(cond != al); 111 return static_cast<Condition>(cond ^ ne); 116 inline Condition ReverseCondition(Condition cond) { argument 117 switch (cond) { 135 return cond;
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/external/chromium_org/v8/src/mips/ |
H A D | assembler-mips.cc | 1875 void Assembler::c(FPUCondition cond, SecondaryField fmt, argument 1880 | cc << 8 | 3 << 4 | cond; 1886 FPUCondition cond) { 1890 c(cond, D, src1, f14, 0); 1885 fcmp(FPURegister src1, const double src2, FPUCondition cond) argument
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngine.cpp | 249 SVal cond, bool assumption) { 250 return getCheckerManager().runCheckersForEvalAssume(state, cond, assumption); 248 processAssume(ProgramStateRef state, SVal cond, bool assumption) argument
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/external/iproute2/misc/ |
H A D | ss.c | 841 struct inet_diag_hostcond *cond = (struct inet_diag_hostcond*)(ptr+4); local 844 cond->family = a->addr.family; 845 cond->port = a->port; 846 cond->prefix_len = a->addr.bitlen; 847 memcpy(cond->addr, a->addr.data, alen);
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/external/qemu/tcg/ |
H A D | tcg-op.h | 627 static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, argument 630 tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); 633 static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, argument 637 tcg_gen_brcond_i32(cond, arg1, t0, label_index); 641 static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, argument 644 tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); 647 static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, argument 651 tcg_gen_setcond_i32(cond, ret, arg1, t0); 971 static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, argument 976 TCGV_HIGH(arg2), cond, label_inde 979 tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) argument 1236 tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, int label_index) argument 1242 tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) argument 1387 tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, int label_index) argument 1395 tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) argument [all...] |
/external/v8/src/arm/ |
H A D | assembler-arm.h | 769 void b(int branch_offset, Condition cond = al); 770 void bl(int branch_offset, Condition cond = al); 772 void blx(Register target, Condition cond = al); // v5 and above 773 void bx(Register target, Condition cond = al); // v5 and above, plus v4t 776 void b(Label* L, Condition cond = al) { 777 b(branch_offset(L, cond == al), cond); local 779 void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); } local 780 void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); } local 781 void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); } local [all...] |
H A D | constants-arm.h | 147 inline Condition NegateCondition(Condition cond) { argument 148 ASSERT(cond != al); 149 return static_cast<Condition>(cond ^ ne); 154 inline Condition ReverseCondition(Condition cond) { argument 155 switch (cond) { 173 return cond;
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H A D | full-codegen-arm.cc | 700 void FullCodeGenerator::Split(Condition cond, argument 705 __ b(cond, if_true); 707 __ b(NegateCondition(cond), if_false); 709 __ b(cond, if_true); 4239 Condition cond = eq; local 4243 cond = eq; 4246 cond = lt; 4249 cond = gt; 4252 cond = le; 4255 cond [all...] |
/external/v8/src/mips/ |
H A D | assembler-mips.cc | 1860 void Assembler::c(FPUCondition cond, SecondaryField fmt, argument 1866 | cc << 8 | 3 << 4 | cond; 1872 FPUCondition cond) { 1877 c(cond, D, src1, f14, 0); 1871 fcmp(FPURegister src1, const double src2, FPUCondition cond) argument
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H A D | macro-assembler-mips.cc | 62 Condition cond, 64 Branch(2, NegateCondition(cond), src1, src2); 77 Condition cond, 79 Branch(2, NegateCondition(cond), src1, src2); 1588 #define BRANCH_ARGS_CHECK(cond, rs, rt) ASSERT( \ 1589 (cond == cc_always && rs.is(zero_reg) && rt.rm().is(zero_reg)) || \ 1590 (cond != cc_always && (!rs.is(zero_reg) || !rt.rm().is(zero_reg)))) 1598 void MacroAssembler::Branch(int16_t offset, Condition cond, Register rs, 1601 BranchShort(offset, cond, rs, rt, bdslot); 1622 void MacroAssembler::Branch(Label* L, Condition cond, Registe 60 LoadRoot(Register destination, Heap::RootListIndex index, Condition cond, Register src1, const Operand& src2) argument 75 StoreRoot(Register source, Heap::RootListIndex index, Condition cond, Register src1, const Operand& src2) argument 5409 ChangeBranchCondition(Condition cond) argument [all...] |